1/* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Eddie Huang <eddie.huang@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/clock/mt8173-clk.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/memory/mt8173-larb-port.h> 18#include <dt-bindings/phy/phy.h> 19#include <dt-bindings/power/mt8173-power.h> 20#include <dt-bindings/reset/mt8173-resets.h> 21#include "mt8173-pinfunc.h" 22 23/ { 24 compatible = "mediatek,mt8173"; 25 interrupt-parent = <&sysirq>; 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 aliases { 30 ovl0 = &ovl0; 31 ovl1 = &ovl1; 32 rdma0 = &rdma0; 33 rdma1 = &rdma1; 34 rdma2 = &rdma2; 35 wdma0 = &wdma0; 36 wdma1 = &wdma1; 37 color0 = &color0; 38 color1 = &color1; 39 split0 = &split0; 40 split1 = &split1; 41 dpi0 = &dpi0; 42 dsi0 = &dsi0; 43 dsi1 = &dsi1; 44 mdp_rdma0 = &mdp_rdma0; 45 mdp_rdma1 = &mdp_rdma1; 46 mdp_rsz0 = &mdp_rsz0; 47 mdp_rsz1 = &mdp_rsz1; 48 mdp_rsz2 = &mdp_rsz2; 49 mdp_wdma0 = &mdp_wdma0; 50 mdp_wrot0 = &mdp_wrot0; 51 mdp_wrot1 = &mdp_wrot1; 52 }; 53 54 cpus { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 cpu-map { 59 cluster0 { 60 core0 { 61 cpu = <&cpu0>; 62 }; 63 core1 { 64 cpu = <&cpu1>; 65 }; 66 }; 67 68 cluster1 { 69 core0 { 70 cpu = <&cpu2>; 71 }; 72 core1 { 73 cpu = <&cpu3>; 74 }; 75 }; 76 }; 77 78 cpu0: cpu@0 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a53"; 81 reg = <0x000>; 82 enable-method = "psci"; 83 cpu-idle-states = <&CPU_SLEEP_0>; 84 }; 85 86 cpu1: cpu@1 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a53"; 89 reg = <0x001>; 90 enable-method = "psci"; 91 cpu-idle-states = <&CPU_SLEEP_0>; 92 }; 93 94 cpu2: cpu@100 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a57"; 97 reg = <0x100>; 98 enable-method = "psci"; 99 cpu-idle-states = <&CPU_SLEEP_0>; 100 }; 101 102 cpu3: cpu@101 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a57"; 105 reg = <0x101>; 106 enable-method = "psci"; 107 cpu-idle-states = <&CPU_SLEEP_0>; 108 }; 109 110 idle-states { 111 entry-method = "psci"; 112 113 CPU_SLEEP_0: cpu-sleep-0 { 114 compatible = "arm,idle-state"; 115 local-timer-stop; 116 entry-latency-us = <639>; 117 exit-latency-us = <680>; 118 min-residency-us = <1088>; 119 arm,psci-suspend-param = <0x0010000>; 120 }; 121 }; 122 }; 123 124 psci { 125 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 126 method = "smc"; 127 cpu_suspend = <0x84000001>; 128 cpu_off = <0x84000002>; 129 cpu_on = <0x84000003>; 130 }; 131 132 clk26m: oscillator@0 { 133 compatible = "fixed-clock"; 134 #clock-cells = <0>; 135 clock-frequency = <26000000>; 136 clock-output-names = "clk26m"; 137 }; 138 139 clk32k: oscillator@1 { 140 compatible = "fixed-clock"; 141 #clock-cells = <0>; 142 clock-frequency = <32000>; 143 clock-output-names = "clk32k"; 144 }; 145 146 cpum_ck: oscillator@2 { 147 compatible = "fixed-clock"; 148 #clock-cells = <0>; 149 clock-frequency = <0>; 150 clock-output-names = "cpum_ck"; 151 }; 152 153 thermal-zones { 154 cpu_thermal: cpu_thermal { 155 polling-delay-passive = <1000>; /* milliseconds */ 156 polling-delay = <1000>; /* milliseconds */ 157 158 thermal-sensors = <&thermal>; 159 sustainable-power = <1500>; /* milliwatts */ 160 161 trips { 162 threshold: trip-point@0 { 163 temperature = <68000>; 164 hysteresis = <2000>; 165 type = "passive"; 166 }; 167 168 target: trip-point@1 { 169 temperature = <85000>; 170 hysteresis = <2000>; 171 type = "passive"; 172 }; 173 174 cpu_crit: cpu_crit@0 { 175 temperature = <115000>; 176 hysteresis = <2000>; 177 type = "critical"; 178 }; 179 }; 180 181 cooling-maps { 182 map@0 { 183 trip = <&target>; 184 cooling-device = <&cpu0 0 0>; 185 contribution = <1024>; 186 }; 187 map@1 { 188 trip = <&target>; 189 cooling-device = <&cpu2 0 0>; 190 contribution = <2048>; 191 }; 192 }; 193 }; 194 }; 195 196 reserved-memory { 197 #address-cells = <2>; 198 #size-cells = <2>; 199 ranges; 200 vpu_dma_reserved: vpu_dma_mem_region { 201 compatible = "shared-dma-pool"; 202 reg = <0 0xb7000000 0 0x500000>; 203 alignment = <0x1000>; 204 no-map; 205 }; 206 }; 207 208 timer { 209 compatible = "arm,armv8-timer"; 210 interrupt-parent = <&gic>; 211 interrupts = <GIC_PPI 13 212 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 213 <GIC_PPI 14 214 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 215 <GIC_PPI 11 216 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 217 <GIC_PPI 10 218 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 219 }; 220 221 soc { 222 #address-cells = <2>; 223 #size-cells = <2>; 224 compatible = "simple-bus"; 225 ranges; 226 227 topckgen: clock-controller@10000000 { 228 compatible = "mediatek,mt8173-topckgen"; 229 reg = <0 0x10000000 0 0x1000>; 230 #clock-cells = <1>; 231 }; 232 233 infracfg: power-controller@10001000 { 234 compatible = "mediatek,mt8173-infracfg", "syscon"; 235 reg = <0 0x10001000 0 0x1000>; 236 #clock-cells = <1>; 237 #reset-cells = <1>; 238 }; 239 240 pericfg: power-controller@10003000 { 241 compatible = "mediatek,mt8173-pericfg", "syscon"; 242 reg = <0 0x10003000 0 0x1000>; 243 #clock-cells = <1>; 244 #reset-cells = <1>; 245 }; 246 247 syscfg_pctl_a: syscfg_pctl_a@10005000 { 248 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 249 reg = <0 0x10005000 0 0x1000>; 250 }; 251 252 pio: pinctrl@0x10005000 { 253 compatible = "mediatek,mt8173-pinctrl"; 254 reg = <0 0x1000b000 0 0x1000>; 255 mediatek,pctl-regmap = <&syscfg_pctl_a>; 256 pins-are-numbered; 257 gpio-controller; 258 #gpio-cells = <2>; 259 interrupt-controller; 260 #interrupt-cells = <2>; 261 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 264 265 hdmi_pin: xxx { 266 267 /*hdmi htplg pin*/ 268 pins1 { 269 pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>; 270 input-enable; 271 bias-pull-down; 272 }; 273 }; 274 275 i2c0_pins_a: i2c0 { 276 pins1 { 277 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 278 <MT8173_PIN_46_SCL0__FUNC_SCL0>; 279 bias-disable; 280 }; 281 }; 282 283 i2c1_pins_a: i2c1 { 284 pins1 { 285 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 286 <MT8173_PIN_126_SCL1__FUNC_SCL1>; 287 bias-disable; 288 }; 289 }; 290 291 i2c2_pins_a: i2c2 { 292 pins1 { 293 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 294 <MT8173_PIN_44_SCL2__FUNC_SCL2>; 295 bias-disable; 296 }; 297 }; 298 299 i2c3_pins_a: i2c3 { 300 pins1 { 301 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 302 <MT8173_PIN_107_SCL3__FUNC_SCL3>; 303 bias-disable; 304 }; 305 }; 306 307 i2c4_pins_a: i2c4 { 308 pins1 { 309 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 310 <MT8173_PIN_134_SCL4__FUNC_SCL4>; 311 bias-disable; 312 }; 313 }; 314 315 i2c6_pins_a: i2c6 { 316 pins1 { 317 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 318 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 319 bias-disable; 320 }; 321 }; 322 }; 323 324 scpsys: scpsys@10006000 { 325 compatible = "mediatek,mt8173-scpsys"; 326 #power-domain-cells = <1>; 327 reg = <0 0x10006000 0 0x1000>; 328 clocks = <&clk26m>, 329 <&topckgen CLK_TOP_MM_SEL>, 330 <&topckgen CLK_TOP_VENC_SEL>, 331 <&topckgen CLK_TOP_VENC_LT_SEL>; 332 clock-names = "mfg", "mm", "venc", "venc_lt"; 333 infracfg = <&infracfg>; 334 }; 335 336 watchdog: watchdog@10007000 { 337 compatible = "mediatek,mt8173-wdt", 338 "mediatek,mt6589-wdt"; 339 reg = <0 0x10007000 0 0x100>; 340 }; 341 342 timer: timer@10008000 { 343 compatible = "mediatek,mt8173-timer", 344 "mediatek,mt6577-timer"; 345 reg = <0 0x10008000 0 0x1000>; 346 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 347 clocks = <&infracfg CLK_INFRA_CLK_13M>, 348 <&topckgen CLK_TOP_RTC_SEL>; 349 }; 350 351 pwrap: pwrap@1000d000 { 352 compatible = "mediatek,mt8173-pwrap"; 353 reg = <0 0x1000d000 0 0x1000>; 354 reg-names = "pwrap"; 355 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 356 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 357 reset-names = "pwrap"; 358 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 359 clock-names = "spi", "wrap"; 360 }; 361 362 cec: cec@10013000 { 363 compatible = "mediatek,mt8173-cec"; 364 reg = <0 0x10013000 0 0xbc>; 365 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; 366 clocks = <&infracfg CLK_INFRA_CEC>; 367 status = "disabled"; 368 }; 369 370 vpu: vpu@10020000 { 371 compatible = "mediatek,mt8173-vpu"; 372 reg = <0 0x10020000 0 0x30000>, 373 <0 0x10050000 0 0x100>; 374 reg-names = "tcm", "cfg_reg"; 375 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&topckgen CLK_TOP_SCP_SEL>; 377 clock-names = "main"; 378 memory-region = <&vpu_dma_reserved>; 379 }; 380 381 sysirq: intpol-controller@10200620 { 382 compatible = "mediatek,mt8173-sysirq", 383 "mediatek,mt6577-sysirq"; 384 interrupt-controller; 385 #interrupt-cells = <3>; 386 interrupt-parent = <&gic>; 387 reg = <0 0x10200620 0 0x20>; 388 }; 389 390 iommu: iommu@10205000 { 391 compatible = "mediatek,mt8173-m4u"; 392 reg = <0 0x10205000 0 0x1000>; 393 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 394 clocks = <&infracfg CLK_INFRA_M4U>; 395 clock-names = "bclk"; 396 mediatek,larbs = <&larb0 &larb1 &larb2 397 &larb3 &larb4 &larb5>; 398 #iommu-cells = <1>; 399 }; 400 401 efuse: efuse@10206000 { 402 compatible = "mediatek,mt8173-efuse"; 403 reg = <0 0x10206000 0 0x1000>; 404 }; 405 406 apmixedsys: clock-controller@10209000 { 407 compatible = "mediatek,mt8173-apmixedsys"; 408 reg = <0 0x10209000 0 0x1000>; 409 #clock-cells = <1>; 410 }; 411 412 hdmi_phy: hdmi-phy@10209100 { 413 compatible = "mediatek,mt8173-hdmi-phy"; 414 reg = <0 0x10209100 0 0x24>; 415 clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; 416 clock-names = "pll_ref"; 417 clock-output-names = "hdmitx_dig_cts"; 418 mediatek,ibias = <0xa>; 419 mediatek,ibias_up = <0x1c>; 420 #clock-cells = <0>; 421 #phy-cells = <0>; 422 status = "disabled"; 423 }; 424 425 mipi_tx0: mipi-dphy@10215000 { 426 compatible = "mediatek,mt8173-mipi-tx"; 427 reg = <0 0x10215000 0 0x1000>; 428 clocks = <&clk26m>; 429 clock-output-names = "mipi_tx0_pll"; 430 #clock-cells = <0>; 431 #phy-cells = <0>; 432 status = "disabled"; 433 }; 434 435 mipi_tx1: mipi-dphy@10216000 { 436 compatible = "mediatek,mt8173-mipi-tx"; 437 reg = <0 0x10216000 0 0x1000>; 438 clocks = <&clk26m>; 439 clock-output-names = "mipi_tx1_pll"; 440 #clock-cells = <0>; 441 #phy-cells = <0>; 442 status = "disabled"; 443 }; 444 445 gic: interrupt-controller@10220000 { 446 compatible = "arm,gic-400"; 447 #interrupt-cells = <3>; 448 interrupt-parent = <&gic>; 449 interrupt-controller; 450 reg = <0 0x10221000 0 0x1000>, 451 <0 0x10222000 0 0x2000>, 452 <0 0x10224000 0 0x2000>, 453 <0 0x10226000 0 0x2000>; 454 interrupts = <GIC_PPI 9 455 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 456 }; 457 458 auxadc: auxadc@11001000 { 459 compatible = "mediatek,mt8173-auxadc"; 460 reg = <0 0x11001000 0 0x1000>; 461 }; 462 463 uart0: serial@11002000 { 464 compatible = "mediatek,mt8173-uart", 465 "mediatek,mt6577-uart"; 466 reg = <0 0x11002000 0 0x400>; 467 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 468 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 469 clock-names = "baud", "bus"; 470 status = "disabled"; 471 }; 472 473 uart1: serial@11003000 { 474 compatible = "mediatek,mt8173-uart", 475 "mediatek,mt6577-uart"; 476 reg = <0 0x11003000 0 0x400>; 477 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 478 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 479 clock-names = "baud", "bus"; 480 status = "disabled"; 481 }; 482 483 uart2: serial@11004000 { 484 compatible = "mediatek,mt8173-uart", 485 "mediatek,mt6577-uart"; 486 reg = <0 0x11004000 0 0x400>; 487 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 488 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 489 clock-names = "baud", "bus"; 490 status = "disabled"; 491 }; 492 493 uart3: serial@11005000 { 494 compatible = "mediatek,mt8173-uart", 495 "mediatek,mt6577-uart"; 496 reg = <0 0x11005000 0 0x400>; 497 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 498 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 499 clock-names = "baud", "bus"; 500 status = "disabled"; 501 }; 502 503 i2c0: i2c@11007000 { 504 compatible = "mediatek,mt8173-i2c"; 505 reg = <0 0x11007000 0 0x70>, 506 <0 0x11000100 0 0x80>; 507 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 508 clock-div = <16>; 509 clocks = <&pericfg CLK_PERI_I2C0>, 510 <&pericfg CLK_PERI_AP_DMA>; 511 clock-names = "main", "dma"; 512 pinctrl-names = "default"; 513 pinctrl-0 = <&i2c0_pins_a>; 514 #address-cells = <1>; 515 #size-cells = <0>; 516 status = "disabled"; 517 }; 518 519 i2c1: i2c@11008000 { 520 compatible = "mediatek,mt8173-i2c"; 521 reg = <0 0x11008000 0 0x70>, 522 <0 0x11000180 0 0x80>; 523 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 524 clock-div = <16>; 525 clocks = <&pericfg CLK_PERI_I2C1>, 526 <&pericfg CLK_PERI_AP_DMA>; 527 clock-names = "main", "dma"; 528 pinctrl-names = "default"; 529 pinctrl-0 = <&i2c1_pins_a>; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 status = "disabled"; 533 }; 534 535 i2c2: i2c@11009000 { 536 compatible = "mediatek,mt8173-i2c"; 537 reg = <0 0x11009000 0 0x70>, 538 <0 0x11000200 0 0x80>; 539 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 540 clock-div = <16>; 541 clocks = <&pericfg CLK_PERI_I2C2>, 542 <&pericfg CLK_PERI_AP_DMA>; 543 clock-names = "main", "dma"; 544 pinctrl-names = "default"; 545 pinctrl-0 = <&i2c2_pins_a>; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 status = "disabled"; 549 }; 550 551 spi: spi@1100a000 { 552 compatible = "mediatek,mt8173-spi"; 553 #address-cells = <1>; 554 #size-cells = <0>; 555 reg = <0 0x1100a000 0 0x1000>; 556 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 557 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 558 <&topckgen CLK_TOP_SPI_SEL>, 559 <&pericfg CLK_PERI_SPI0>; 560 clock-names = "parent-clk", "sel-clk", "spi-clk"; 561 status = "disabled"; 562 }; 563 564 thermal: thermal@1100b000 { 565 #thermal-sensor-cells = <0>; 566 compatible = "mediatek,mt8173-thermal"; 567 reg = <0 0x1100b000 0 0x1000>; 568 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 569 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 570 clock-names = "therm", "auxadc"; 571 resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 572 mediatek,auxadc = <&auxadc>; 573 mediatek,apmixedsys = <&apmixedsys>; 574 }; 575 576 nor_flash: spi@1100d000 { 577 compatible = "mediatek,mt8173-nor"; 578 reg = <0 0x1100d000 0 0xe0>; 579 clocks = <&pericfg CLK_PERI_SPI>, 580 <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 581 clock-names = "spi", "sf"; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 status = "disabled"; 585 }; 586 587 i2c3: i2c@11010000 { 588 compatible = "mediatek,mt8173-i2c"; 589 reg = <0 0x11010000 0 0x70>, 590 <0 0x11000280 0 0x80>; 591 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 592 clock-div = <16>; 593 clocks = <&pericfg CLK_PERI_I2C3>, 594 <&pericfg CLK_PERI_AP_DMA>; 595 clock-names = "main", "dma"; 596 pinctrl-names = "default"; 597 pinctrl-0 = <&i2c3_pins_a>; 598 #address-cells = <1>; 599 #size-cells = <0>; 600 status = "disabled"; 601 }; 602 603 i2c4: i2c@11011000 { 604 compatible = "mediatek,mt8173-i2c"; 605 reg = <0 0x11011000 0 0x70>, 606 <0 0x11000300 0 0x80>; 607 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 608 clock-div = <16>; 609 clocks = <&pericfg CLK_PERI_I2C4>, 610 <&pericfg CLK_PERI_AP_DMA>; 611 clock-names = "main", "dma"; 612 pinctrl-names = "default"; 613 pinctrl-0 = <&i2c4_pins_a>; 614 #address-cells = <1>; 615 #size-cells = <0>; 616 status = "disabled"; 617 }; 618 619 hdmiddc0: i2c@11012000 { 620 compatible = "mediatek,mt8173-hdmi-ddc"; 621 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 622 reg = <0 0x11012000 0 0x1C>; 623 clocks = <&pericfg CLK_PERI_I2C5>; 624 clock-names = "ddc-i2c"; 625 }; 626 627 i2c6: i2c@11013000 { 628 compatible = "mediatek,mt8173-i2c"; 629 reg = <0 0x11013000 0 0x70>, 630 <0 0x11000080 0 0x80>; 631 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 632 clock-div = <16>; 633 clocks = <&pericfg CLK_PERI_I2C6>, 634 <&pericfg CLK_PERI_AP_DMA>; 635 clock-names = "main", "dma"; 636 pinctrl-names = "default"; 637 pinctrl-0 = <&i2c6_pins_a>; 638 #address-cells = <1>; 639 #size-cells = <0>; 640 status = "disabled"; 641 }; 642 643 afe: audio-controller@11220000 { 644 compatible = "mediatek,mt8173-afe-pcm"; 645 reg = <0 0x11220000 0 0x1000>; 646 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 647 power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; 648 clocks = <&infracfg CLK_INFRA_AUDIO>, 649 <&topckgen CLK_TOP_AUDIO_SEL>, 650 <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 651 <&topckgen CLK_TOP_APLL1_DIV0>, 652 <&topckgen CLK_TOP_APLL2_DIV0>, 653 <&topckgen CLK_TOP_I2S0_M_SEL>, 654 <&topckgen CLK_TOP_I2S1_M_SEL>, 655 <&topckgen CLK_TOP_I2S2_M_SEL>, 656 <&topckgen CLK_TOP_I2S3_M_SEL>, 657 <&topckgen CLK_TOP_I2S3_B_SEL>; 658 clock-names = "infra_sys_audio_clk", 659 "top_pdn_audio", 660 "top_pdn_aud_intbus", 661 "bck0", 662 "bck1", 663 "i2s0_m", 664 "i2s1_m", 665 "i2s2_m", 666 "i2s3_m", 667 "i2s3_b"; 668 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 669 <&topckgen CLK_TOP_AUD_2_SEL>; 670 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 671 <&topckgen CLK_TOP_APLL2>; 672 }; 673 674 mmc0: mmc@11230000 { 675 compatible = "mediatek,mt8173-mmc", 676 "mediatek,mt8135-mmc"; 677 reg = <0 0x11230000 0 0x1000>; 678 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 679 clocks = <&pericfg CLK_PERI_MSDC30_0>, 680 <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 681 clock-names = "source", "hclk"; 682 status = "disabled"; 683 }; 684 685 mmc1: mmc@11240000 { 686 compatible = "mediatek,mt8173-mmc", 687 "mediatek,mt8135-mmc"; 688 reg = <0 0x11240000 0 0x1000>; 689 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 690 clocks = <&pericfg CLK_PERI_MSDC30_1>, 691 <&topckgen CLK_TOP_AXI_SEL>; 692 clock-names = "source", "hclk"; 693 status = "disabled"; 694 }; 695 696 mmc2: mmc@11250000 { 697 compatible = "mediatek,mt8173-mmc", 698 "mediatek,mt8135-mmc"; 699 reg = <0 0x11250000 0 0x1000>; 700 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 701 clocks = <&pericfg CLK_PERI_MSDC30_2>, 702 <&topckgen CLK_TOP_AXI_SEL>; 703 clock-names = "source", "hclk"; 704 status = "disabled"; 705 }; 706 707 mmc3: mmc@11260000 { 708 compatible = "mediatek,mt8173-mmc", 709 "mediatek,mt8135-mmc"; 710 reg = <0 0x11260000 0 0x1000>; 711 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 712 clocks = <&pericfg CLK_PERI_MSDC30_3>, 713 <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 714 clock-names = "source", "hclk"; 715 status = "disabled"; 716 }; 717 718 usb30: usb@11270000 { 719 compatible = "mediatek,mt8173-xhci"; 720 reg = <0 0x11270000 0 0x1000>, 721 <0 0x11280700 0 0x0100>; 722 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 723 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 724 clocks = <&topckgen CLK_TOP_USB30_SEL>, 725 <&pericfg CLK_PERI_USB0>, 726 <&pericfg CLK_PERI_USB1>; 727 clock-names = "sys_ck", 728 "wakeup_deb_p0", 729 "wakeup_deb_p1"; 730 phys = <&phy_port0 PHY_TYPE_USB3>, 731 <&phy_port1 PHY_TYPE_USB2>; 732 mediatek,syscon-wakeup = <&pericfg>; 733 status = "okay"; 734 }; 735 736 u3phy: usb-phy@11290000 { 737 compatible = "mediatek,mt8173-u3phy"; 738 reg = <0 0x11290000 0 0x800>; 739 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 740 clock-names = "u3phya_ref"; 741 #address-cells = <2>; 742 #size-cells = <2>; 743 ranges; 744 status = "okay"; 745 746 phy_port0: port@11290800 { 747 reg = <0 0x11290800 0 0x800>; 748 #phy-cells = <1>; 749 status = "okay"; 750 }; 751 752 phy_port1: port@11291000 { 753 reg = <0 0x11291000 0 0x800>; 754 #phy-cells = <1>; 755 status = "okay"; 756 }; 757 }; 758 759 mmsys: clock-controller@14000000 { 760 compatible = "mediatek,mt8173-mmsys", "syscon"; 761 reg = <0 0x14000000 0 0x1000>; 762 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 763 #clock-cells = <1>; 764 }; 765 766 mdp { 767 compatible = "mediatek,mt8173-mdp"; 768 #address-cells = <2>; 769 #size-cells = <2>; 770 ranges; 771 mediatek,vpu = <&vpu>; 772 773 mdp_rdma0: rdma@14001000 { 774 compatible = "mediatek,mt8173-mdp-rdma"; 775 reg = <0 0x14001000 0 0x1000>; 776 clocks = <&mmsys CLK_MM_MDP_RDMA0>, 777 <&mmsys CLK_MM_MUTEX_32K>; 778 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 779 iommus = <&iommu M4U_PORT_MDP_RDMA0>; 780 mediatek,larb = <&larb0>; 781 }; 782 783 mdp_rdma1: rdma@14002000 { 784 compatible = "mediatek,mt8173-mdp-rdma"; 785 reg = <0 0x14002000 0 0x1000>; 786 clocks = <&mmsys CLK_MM_MDP_RDMA1>, 787 <&mmsys CLK_MM_MUTEX_32K>; 788 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 789 iommus = <&iommu M4U_PORT_MDP_RDMA1>; 790 mediatek,larb = <&larb4>; 791 }; 792 793 mdp_rsz0: rsz@14003000 { 794 compatible = "mediatek,mt8173-mdp-rsz"; 795 reg = <0 0x14003000 0 0x1000>; 796 clocks = <&mmsys CLK_MM_MDP_RSZ0>; 797 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 798 }; 799 800 mdp_rsz1: rsz@14004000 { 801 compatible = "mediatek,mt8173-mdp-rsz"; 802 reg = <0 0x14004000 0 0x1000>; 803 clocks = <&mmsys CLK_MM_MDP_RSZ1>; 804 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 805 }; 806 807 mdp_rsz2: rsz@14005000 { 808 compatible = "mediatek,mt8173-mdp-rsz"; 809 reg = <0 0x14005000 0 0x1000>; 810 clocks = <&mmsys CLK_MM_MDP_RSZ2>; 811 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 812 }; 813 814 mdp_wdma0: wdma@14006000 { 815 compatible = "mediatek,mt8173-mdp-wdma"; 816 reg = <0 0x14006000 0 0x1000>; 817 clocks = <&mmsys CLK_MM_MDP_WDMA>; 818 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 819 iommus = <&iommu M4U_PORT_MDP_WDMA>; 820 mediatek,larb = <&larb0>; 821 }; 822 823 mdp_wrot0: wrot@14007000 { 824 compatible = "mediatek,mt8173-mdp-wrot"; 825 reg = <0 0x14007000 0 0x1000>; 826 clocks = <&mmsys CLK_MM_MDP_WROT0>; 827 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 828 iommus = <&iommu M4U_PORT_MDP_WROT0>; 829 mediatek,larb = <&larb0>; 830 }; 831 832 mdp_wrot1: wrot@14008000 { 833 compatible = "mediatek,mt8173-mdp-wrot"; 834 reg = <0 0x14008000 0 0x1000>; 835 clocks = <&mmsys CLK_MM_MDP_WROT1>; 836 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 837 iommus = <&iommu M4U_PORT_MDP_WROT1>; 838 mediatek,larb = <&larb4>; 839 }; 840 }; 841 842 ovl0: ovl@1400c000 { 843 compatible = "mediatek,mt8173-disp-ovl"; 844 reg = <0 0x1400c000 0 0x1000>; 845 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 846 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 847 clocks = <&mmsys CLK_MM_DISP_OVL0>; 848 iommus = <&iommu M4U_PORT_DISP_OVL0>; 849 mediatek,larb = <&larb0>; 850 }; 851 852 ovl1: ovl@1400d000 { 853 compatible = "mediatek,mt8173-disp-ovl"; 854 reg = <0 0x1400d000 0 0x1000>; 855 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; 856 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 857 clocks = <&mmsys CLK_MM_DISP_OVL1>; 858 iommus = <&iommu M4U_PORT_DISP_OVL1>; 859 mediatek,larb = <&larb4>; 860 }; 861 862 rdma0: rdma@1400e000 { 863 compatible = "mediatek,mt8173-disp-rdma"; 864 reg = <0 0x1400e000 0 0x1000>; 865 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 866 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 867 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 868 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 869 mediatek,larb = <&larb0>; 870 }; 871 872 rdma1: rdma@1400f000 { 873 compatible = "mediatek,mt8173-disp-rdma"; 874 reg = <0 0x1400f000 0 0x1000>; 875 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; 876 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 877 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 878 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 879 mediatek,larb = <&larb4>; 880 }; 881 882 rdma2: rdma@14010000 { 883 compatible = "mediatek,mt8173-disp-rdma"; 884 reg = <0 0x14010000 0 0x1000>; 885 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; 886 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 887 clocks = <&mmsys CLK_MM_DISP_RDMA2>; 888 iommus = <&iommu M4U_PORT_DISP_RDMA2>; 889 mediatek,larb = <&larb4>; 890 }; 891 892 wdma0: wdma@14011000 { 893 compatible = "mediatek,mt8173-disp-wdma"; 894 reg = <0 0x14011000 0 0x1000>; 895 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 896 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 897 clocks = <&mmsys CLK_MM_DISP_WDMA0>; 898 iommus = <&iommu M4U_PORT_DISP_WDMA0>; 899 mediatek,larb = <&larb0>; 900 }; 901 902 wdma1: wdma@14012000 { 903 compatible = "mediatek,mt8173-disp-wdma"; 904 reg = <0 0x14012000 0 0x1000>; 905 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; 906 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 907 clocks = <&mmsys CLK_MM_DISP_WDMA1>; 908 iommus = <&iommu M4U_PORT_DISP_WDMA1>; 909 mediatek,larb = <&larb4>; 910 }; 911 912 color0: color@14013000 { 913 compatible = "mediatek,mt8173-disp-color"; 914 reg = <0 0x14013000 0 0x1000>; 915 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; 916 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 917 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 918 }; 919 920 color1: color@14014000 { 921 compatible = "mediatek,mt8173-disp-color"; 922 reg = <0 0x14014000 0 0x1000>; 923 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 924 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 925 clocks = <&mmsys CLK_MM_DISP_COLOR1>; 926 }; 927 928 aal@14015000 { 929 compatible = "mediatek,mt8173-disp-aal"; 930 reg = <0 0x14015000 0 0x1000>; 931 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 932 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 933 clocks = <&mmsys CLK_MM_DISP_AAL>; 934 }; 935 936 gamma@14016000 { 937 compatible = "mediatek,mt8173-disp-gamma"; 938 reg = <0 0x14016000 0 0x1000>; 939 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 940 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 941 clocks = <&mmsys CLK_MM_DISP_GAMMA>; 942 }; 943 944 merge@14017000 { 945 compatible = "mediatek,mt8173-disp-merge"; 946 reg = <0 0x14017000 0 0x1000>; 947 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 948 clocks = <&mmsys CLK_MM_DISP_MERGE>; 949 }; 950 951 split0: split@14018000 { 952 compatible = "mediatek,mt8173-disp-split"; 953 reg = <0 0x14018000 0 0x1000>; 954 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 955 clocks = <&mmsys CLK_MM_DISP_SPLIT0>; 956 }; 957 958 split1: split@14019000 { 959 compatible = "mediatek,mt8173-disp-split"; 960 reg = <0 0x14019000 0 0x1000>; 961 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 962 clocks = <&mmsys CLK_MM_DISP_SPLIT1>; 963 }; 964 965 ufoe@1401a000 { 966 compatible = "mediatek,mt8173-disp-ufoe"; 967 reg = <0 0x1401a000 0 0x1000>; 968 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 969 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 970 clocks = <&mmsys CLK_MM_DISP_UFOE>; 971 }; 972 973 dsi0: dsi@1401b000 { 974 compatible = "mediatek,mt8173-dsi"; 975 reg = <0 0x1401b000 0 0x1000>; 976 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 977 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 978 clocks = <&mmsys CLK_MM_DSI0_ENGINE>, 979 <&mmsys CLK_MM_DSI0_DIGITAL>, 980 <&mipi_tx0>; 981 clock-names = "engine", "digital", "hs"; 982 phys = <&mipi_tx0>; 983 phy-names = "dphy"; 984 status = "disabled"; 985 }; 986 987 dsi1: dsi@1401c000 { 988 compatible = "mediatek,mt8173-dsi"; 989 reg = <0 0x1401c000 0 0x1000>; 990 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 991 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 992 clocks = <&mmsys CLK_MM_DSI1_ENGINE>, 993 <&mmsys CLK_MM_DSI1_DIGITAL>, 994 <&mipi_tx1>; 995 clock-names = "engine", "digital", "hs"; 996 phy = <&mipi_tx1>; 997 phy-names = "dphy"; 998 status = "disabled"; 999 }; 1000 1001 dpi0: dpi@1401d000 { 1002 compatible = "mediatek,mt8173-dpi"; 1003 reg = <0 0x1401d000 0 0x1000>; 1004 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 1005 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1006 clocks = <&mmsys CLK_MM_DPI_PIXEL>, 1007 <&mmsys CLK_MM_DPI_ENGINE>, 1008 <&apmixedsys CLK_APMIXED_TVDPLL>; 1009 clock-names = "pixel", "engine", "pll"; 1010 status = "disabled"; 1011 1012 port { 1013 dpi0_out: endpoint { 1014 remote-endpoint = <&hdmi0_in>; 1015 }; 1016 }; 1017 }; 1018 1019 pwm0: pwm@1401e000 { 1020 compatible = "mediatek,mt8173-disp-pwm", 1021 "mediatek,mt6595-disp-pwm"; 1022 reg = <0 0x1401e000 0 0x1000>; 1023 #pwm-cells = <2>; 1024 clocks = <&mmsys CLK_MM_DISP_PWM026M>, 1025 <&mmsys CLK_MM_DISP_PWM0MM>; 1026 clock-names = "main", "mm"; 1027 status = "disabled"; 1028 }; 1029 1030 pwm1: pwm@1401f000 { 1031 compatible = "mediatek,mt8173-disp-pwm", 1032 "mediatek,mt6595-disp-pwm"; 1033 reg = <0 0x1401f000 0 0x1000>; 1034 #pwm-cells = <2>; 1035 clocks = <&mmsys CLK_MM_DISP_PWM126M>, 1036 <&mmsys CLK_MM_DISP_PWM1MM>; 1037 clock-names = "main", "mm"; 1038 status = "disabled"; 1039 }; 1040 1041 mutex: mutex@14020000 { 1042 compatible = "mediatek,mt8173-disp-mutex"; 1043 reg = <0 0x14020000 0 0x1000>; 1044 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 1045 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1046 clocks = <&mmsys CLK_MM_MUTEX_32K>; 1047 }; 1048 1049 larb0: larb@14021000 { 1050 compatible = "mediatek,mt8173-smi-larb"; 1051 reg = <0 0x14021000 0 0x1000>; 1052 mediatek,smi = <&smi_common>; 1053 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1054 clocks = <&mmsys CLK_MM_SMI_LARB0>, 1055 <&mmsys CLK_MM_SMI_LARB0>; 1056 clock-names = "apb", "smi"; 1057 }; 1058 1059 smi_common: smi@14022000 { 1060 compatible = "mediatek,mt8173-smi-common"; 1061 reg = <0 0x14022000 0 0x1000>; 1062 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1063 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1064 <&mmsys CLK_MM_SMI_COMMON>; 1065 clock-names = "apb", "smi"; 1066 }; 1067 1068 od@14023000 { 1069 compatible = "mediatek,mt8173-disp-od"; 1070 reg = <0 0x14023000 0 0x1000>; 1071 clocks = <&mmsys CLK_MM_DISP_OD>; 1072 }; 1073 1074 hdmi0: hdmi@14025000 { 1075 compatible = "mediatek,mt8173-hdmi"; 1076 reg = <0 0x14025000 0 0x400>; 1077 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>; 1078 clocks = <&mmsys CLK_MM_HDMI_PIXEL>, 1079 <&mmsys CLK_MM_HDMI_PLLCK>, 1080 <&mmsys CLK_MM_HDMI_AUDIO>, 1081 <&mmsys CLK_MM_HDMI_SPDIF>; 1082 clock-names = "pixel", "pll", "bclk", "spdif"; 1083 pinctrl-names = "default"; 1084 pinctrl-0 = <&hdmi_pin>; 1085 phys = <&hdmi_phy>; 1086 phy-names = "hdmi"; 1087 mediatek,syscon-hdmi = <&mmsys 0x900>; 1088 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; 1089 assigned-clock-parents = <&hdmi_phy>; 1090 status = "disabled"; 1091 1092 ports { 1093 #address-cells = <1>; 1094 #size-cells = <0>; 1095 1096 port@0 { 1097 reg = <0>; 1098 1099 hdmi0_in: endpoint { 1100 remote-endpoint = <&dpi0_out>; 1101 }; 1102 }; 1103 }; 1104 }; 1105 1106 larb4: larb@14027000 { 1107 compatible = "mediatek,mt8173-smi-larb"; 1108 reg = <0 0x14027000 0 0x1000>; 1109 mediatek,smi = <&smi_common>; 1110 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1111 clocks = <&mmsys CLK_MM_SMI_LARB4>, 1112 <&mmsys CLK_MM_SMI_LARB4>; 1113 clock-names = "apb", "smi"; 1114 }; 1115 1116 imgsys: clock-controller@15000000 { 1117 compatible = "mediatek,mt8173-imgsys", "syscon"; 1118 reg = <0 0x15000000 0 0x1000>; 1119 #clock-cells = <1>; 1120 }; 1121 1122 larb2: larb@15001000 { 1123 compatible = "mediatek,mt8173-smi-larb"; 1124 reg = <0 0x15001000 0 0x1000>; 1125 mediatek,smi = <&smi_common>; 1126 power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>; 1127 clocks = <&imgsys CLK_IMG_LARB2_SMI>, 1128 <&imgsys CLK_IMG_LARB2_SMI>; 1129 clock-names = "apb", "smi"; 1130 }; 1131 1132 vdecsys: clock-controller@16000000 { 1133 compatible = "mediatek,mt8173-vdecsys", "syscon"; 1134 reg = <0 0x16000000 0 0x1000>; 1135 #clock-cells = <1>; 1136 }; 1137 1138 vcodec_dec: vcodec@16000000 { 1139 compatible = "mediatek,mt8173-vcodec-dec"; 1140 reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */ 1141 <0 0x16020000 0 0x1000>, /* VDEC_MISC */ 1142 <0 0x16021000 0 0x800>, /* VDEC_LD */ 1143 <0 0x16021800 0 0x800>, /* VDEC_TOP */ 1144 <0 0x16022000 0 0x1000>, /* VDEC_CM */ 1145 <0 0x16023000 0 0x1000>, /* VDEC_AD */ 1146 <0 0x16024000 0 0x1000>, /* VDEC_AV */ 1147 <0 0x16025000 0 0x1000>, /* VDEC_PP */ 1148 <0 0x16026800 0 0x800>, /* VDEC_HWD */ 1149 <0 0x16027000 0 0x800>, /* VDEC_HWQ */ 1150 <0 0x16027800 0 0x800>, /* VDEC_HWB */ 1151 <0 0x16028400 0 0x400>; /* VDEC_HWG */ 1152 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; 1153 mediatek,larb = <&larb1>; 1154 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, 1155 <&iommu M4U_PORT_HW_VDEC_PP_EXT>, 1156 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, 1157 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, 1158 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, 1159 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, 1160 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, 1161 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; 1162 mediatek,vpu = <&vpu>; 1163 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 1164 clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, 1165 <&topckgen CLK_TOP_UNIVPLL_D2>, 1166 <&topckgen CLK_TOP_CCI400_SEL>, 1167 <&topckgen CLK_TOP_VDEC_SEL>, 1168 <&topckgen CLK_TOP_VCODECPLL>, 1169 <&apmixedsys CLK_APMIXED_VENCPLL>, 1170 <&topckgen CLK_TOP_VENC_LT_SEL>, 1171 <&topckgen CLK_TOP_VCODECPLL_370P5>; 1172 clock-names = "vcodecpll", 1173 "univpll_d2", 1174 "clk_cci400_sel", 1175 "vdec_sel", 1176 "vdecpll", 1177 "vencpll", 1178 "venc_lt_sel", 1179 "vdec_bus_clk_src"; 1180 }; 1181 1182 larb1: larb@16010000 { 1183 compatible = "mediatek,mt8173-smi-larb"; 1184 reg = <0 0x16010000 0 0x1000>; 1185 mediatek,smi = <&smi_common>; 1186 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 1187 clocks = <&vdecsys CLK_VDEC_CKEN>, 1188 <&vdecsys CLK_VDEC_LARB_CKEN>; 1189 clock-names = "apb", "smi"; 1190 }; 1191 1192 vencsys: clock-controller@18000000 { 1193 compatible = "mediatek,mt8173-vencsys", "syscon"; 1194 reg = <0 0x18000000 0 0x1000>; 1195 #clock-cells = <1>; 1196 }; 1197 1198 larb3: larb@18001000 { 1199 compatible = "mediatek,mt8173-smi-larb"; 1200 reg = <0 0x18001000 0 0x1000>; 1201 mediatek,smi = <&smi_common>; 1202 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 1203 clocks = <&vencsys CLK_VENC_CKE1>, 1204 <&vencsys CLK_VENC_CKE0>; 1205 clock-names = "apb", "smi"; 1206 }; 1207 1208 vcodec_enc: vcodec@18002000 { 1209 compatible = "mediatek,mt8173-vcodec-enc"; 1210 reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */ 1211 <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ 1212 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>, 1213 <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; 1214 mediatek,larb = <&larb3>, 1215 <&larb5>; 1216 iommus = <&iommu M4U_PORT_VENC_RCPU>, 1217 <&iommu M4U_PORT_VENC_REC>, 1218 <&iommu M4U_PORT_VENC_BSDMA>, 1219 <&iommu M4U_PORT_VENC_SV_COMV>, 1220 <&iommu M4U_PORT_VENC_RD_COMV>, 1221 <&iommu M4U_PORT_VENC_CUR_LUMA>, 1222 <&iommu M4U_PORT_VENC_CUR_CHROMA>, 1223 <&iommu M4U_PORT_VENC_REF_LUMA>, 1224 <&iommu M4U_PORT_VENC_REF_CHROMA>, 1225 <&iommu M4U_PORT_VENC_NBM_RDMA>, 1226 <&iommu M4U_PORT_VENC_NBM_WDMA>, 1227 <&iommu M4U_PORT_VENC_RCPU_SET2>, 1228 <&iommu M4U_PORT_VENC_REC_FRM_SET2>, 1229 <&iommu M4U_PORT_VENC_BSDMA_SET2>, 1230 <&iommu M4U_PORT_VENC_SV_COMA_SET2>, 1231 <&iommu M4U_PORT_VENC_RD_COMA_SET2>, 1232 <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, 1233 <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, 1234 <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, 1235 <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; 1236 mediatek,vpu = <&vpu>; 1237 clocks = <&topckgen CLK_TOP_VENCPLL_D2>, 1238 <&topckgen CLK_TOP_VENC_SEL>, 1239 <&topckgen CLK_TOP_UNIVPLL1_D2>, 1240 <&topckgen CLK_TOP_VENC_LT_SEL>; 1241 clock-names = "venc_sel_src", 1242 "venc_sel", 1243 "venc_lt_sel_src", 1244 "venc_lt_sel"; 1245 }; 1246 1247 vencltsys: clock-controller@19000000 { 1248 compatible = "mediatek,mt8173-vencltsys", "syscon"; 1249 reg = <0 0x19000000 0 0x1000>; 1250 #clock-cells = <1>; 1251 }; 1252 1253 larb5: larb@19001000 { 1254 compatible = "mediatek,mt8173-smi-larb"; 1255 reg = <0 0x19001000 0 0x1000>; 1256 mediatek,smi = <&smi_common>; 1257 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; 1258 clocks = <&vencltsys CLK_VENCLT_CKE1>, 1259 <&vencltsys CLK_VENCLT_CKE0>; 1260 clock-names = "apb", "smi"; 1261 }; 1262 }; 1263}; 1264 1265