1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Eddie Huang <eddie.huang@mediatek.com> 5 */ 6 7#include <dt-bindings/clock/mt8173-clk.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/memory/mt8173-larb-port.h> 11#include <dt-bindings/phy/phy.h> 12#include <dt-bindings/power/mt8173-power.h> 13#include <dt-bindings/reset/mt8173-resets.h> 14#include <dt-bindings/gce/mt8173-gce.h> 15#include <dt-bindings/thermal/thermal.h> 16#include "mt8173-pinfunc.h" 17 18/ { 19 compatible = "mediatek,mt8173"; 20 interrupt-parent = <&sysirq>; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 aliases { 25 ovl0 = &ovl0; 26 ovl1 = &ovl1; 27 rdma0 = &rdma0; 28 rdma1 = &rdma1; 29 rdma2 = &rdma2; 30 wdma0 = &wdma0; 31 wdma1 = &wdma1; 32 color0 = &color0; 33 color1 = &color1; 34 split0 = &split0; 35 split1 = &split1; 36 dpi0 = &dpi0; 37 dsi0 = &dsi0; 38 dsi1 = &dsi1; 39 mdp-rdma0 = &mdp_rdma0; 40 mdp-rdma1 = &mdp_rdma1; 41 mdp-rsz0 = &mdp_rsz0; 42 mdp-rsz1 = &mdp_rsz1; 43 mdp-rsz2 = &mdp_rsz2; 44 mdp-wdma0 = &mdp_wdma0; 45 mdp-wrot0 = &mdp_wrot0; 46 mdp-wrot1 = &mdp_wrot1; 47 serial0 = &uart0; 48 serial1 = &uart1; 49 serial2 = &uart2; 50 serial3 = &uart3; 51 }; 52 53 cluster0_opp: opp-table-0 { 54 compatible = "operating-points-v2"; 55 opp-shared; 56 opp-507000000 { 57 opp-hz = /bits/ 64 <507000000>; 58 opp-microvolt = <859000>; 59 }; 60 opp-702000000 { 61 opp-hz = /bits/ 64 <702000000>; 62 opp-microvolt = <908000>; 63 }; 64 opp-1001000000 { 65 opp-hz = /bits/ 64 <1001000000>; 66 opp-microvolt = <983000>; 67 }; 68 opp-1105000000 { 69 opp-hz = /bits/ 64 <1105000000>; 70 opp-microvolt = <1009000>; 71 }; 72 opp-1209000000 { 73 opp-hz = /bits/ 64 <1209000000>; 74 opp-microvolt = <1034000>; 75 }; 76 opp-1300000000 { 77 opp-hz = /bits/ 64 <1300000000>; 78 opp-microvolt = <1057000>; 79 }; 80 opp-1508000000 { 81 opp-hz = /bits/ 64 <1508000000>; 82 opp-microvolt = <1109000>; 83 }; 84 opp-1703000000 { 85 opp-hz = /bits/ 64 <1703000000>; 86 opp-microvolt = <1125000>; 87 }; 88 }; 89 90 cluster1_opp: opp-table-1 { 91 compatible = "operating-points-v2"; 92 opp-shared; 93 opp-507000000 { 94 opp-hz = /bits/ 64 <507000000>; 95 opp-microvolt = <828000>; 96 }; 97 opp-702000000 { 98 opp-hz = /bits/ 64 <702000000>; 99 opp-microvolt = <867000>; 100 }; 101 opp-1001000000 { 102 opp-hz = /bits/ 64 <1001000000>; 103 opp-microvolt = <927000>; 104 }; 105 opp-1209000000 { 106 opp-hz = /bits/ 64 <1209000000>; 107 opp-microvolt = <968000>; 108 }; 109 opp-1404000000 { 110 opp-hz = /bits/ 64 <1404000000>; 111 opp-microvolt = <1007000>; 112 }; 113 opp-1612000000 { 114 opp-hz = /bits/ 64 <1612000000>; 115 opp-microvolt = <1049000>; 116 }; 117 opp-1807000000 { 118 opp-hz = /bits/ 64 <1807000000>; 119 opp-microvolt = <1089000>; 120 }; 121 opp-2106000000 { 122 opp-hz = /bits/ 64 <2106000000>; 123 opp-microvolt = <1125000>; 124 }; 125 }; 126 127 cpus { 128 #address-cells = <1>; 129 #size-cells = <0>; 130 131 cpu-map { 132 cluster0 { 133 core0 { 134 cpu = <&cpu0>; 135 }; 136 core1 { 137 cpu = <&cpu1>; 138 }; 139 }; 140 141 cluster1 { 142 core0 { 143 cpu = <&cpu2>; 144 }; 145 core1 { 146 cpu = <&cpu3>; 147 }; 148 }; 149 }; 150 151 cpu0: cpu@0 { 152 device_type = "cpu"; 153 compatible = "arm,cortex-a53"; 154 reg = <0x000>; 155 enable-method = "psci"; 156 cpu-idle-states = <&CPU_SLEEP_0>; 157 #cooling-cells = <2>; 158 dynamic-power-coefficient = <263>; 159 clocks = <&infracfg CLK_INFRA_CA53SEL>, 160 <&apmixedsys CLK_APMIXED_MAINPLL>; 161 clock-names = "cpu", "intermediate"; 162 operating-points-v2 = <&cluster0_opp>; 163 capacity-dmips-mhz = <740>; 164 }; 165 166 cpu1: cpu@1 { 167 device_type = "cpu"; 168 compatible = "arm,cortex-a53"; 169 reg = <0x001>; 170 enable-method = "psci"; 171 cpu-idle-states = <&CPU_SLEEP_0>; 172 #cooling-cells = <2>; 173 dynamic-power-coefficient = <263>; 174 clocks = <&infracfg CLK_INFRA_CA53SEL>, 175 <&apmixedsys CLK_APMIXED_MAINPLL>; 176 clock-names = "cpu", "intermediate"; 177 operating-points-v2 = <&cluster0_opp>; 178 capacity-dmips-mhz = <740>; 179 }; 180 181 cpu2: cpu@100 { 182 device_type = "cpu"; 183 compatible = "arm,cortex-a72"; 184 reg = <0x100>; 185 enable-method = "psci"; 186 cpu-idle-states = <&CPU_SLEEP_0>; 187 #cooling-cells = <2>; 188 dynamic-power-coefficient = <530>; 189 clocks = <&infracfg CLK_INFRA_CA72SEL>, 190 <&apmixedsys CLK_APMIXED_MAINPLL>; 191 clock-names = "cpu", "intermediate"; 192 operating-points-v2 = <&cluster1_opp>; 193 capacity-dmips-mhz = <1024>; 194 }; 195 196 cpu3: cpu@101 { 197 device_type = "cpu"; 198 compatible = "arm,cortex-a72"; 199 reg = <0x101>; 200 enable-method = "psci"; 201 cpu-idle-states = <&CPU_SLEEP_0>; 202 #cooling-cells = <2>; 203 dynamic-power-coefficient = <530>; 204 clocks = <&infracfg CLK_INFRA_CA72SEL>, 205 <&apmixedsys CLK_APMIXED_MAINPLL>; 206 clock-names = "cpu", "intermediate"; 207 operating-points-v2 = <&cluster1_opp>; 208 capacity-dmips-mhz = <1024>; 209 }; 210 211 idle-states { 212 entry-method = "psci"; 213 214 CPU_SLEEP_0: cpu-sleep-0 { 215 compatible = "arm,idle-state"; 216 local-timer-stop; 217 entry-latency-us = <639>; 218 exit-latency-us = <680>; 219 min-residency-us = <1088>; 220 arm,psci-suspend-param = <0x0010000>; 221 }; 222 }; 223 }; 224 225 pmu_a53 { 226 compatible = "arm,cortex-a53-pmu"; 227 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, 228 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>; 229 interrupt-affinity = <&cpu0>, <&cpu1>; 230 }; 231 232 pmu_a72 { 233 compatible = "arm,cortex-a72-pmu"; 234 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>, 235 <GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>; 236 interrupt-affinity = <&cpu2>, <&cpu3>; 237 }; 238 239 psci { 240 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 241 method = "smc"; 242 cpu_suspend = <0x84000001>; 243 cpu_off = <0x84000002>; 244 cpu_on = <0x84000003>; 245 }; 246 247 clk26m: oscillator0 { 248 compatible = "fixed-clock"; 249 #clock-cells = <0>; 250 clock-frequency = <26000000>; 251 clock-output-names = "clk26m"; 252 }; 253 254 clk32k: oscillator1 { 255 compatible = "fixed-clock"; 256 #clock-cells = <0>; 257 clock-frequency = <32000>; 258 clock-output-names = "clk32k"; 259 }; 260 261 cpum_ck: oscillator2 { 262 compatible = "fixed-clock"; 263 #clock-cells = <0>; 264 clock-frequency = <0>; 265 clock-output-names = "cpum_ck"; 266 }; 267 268 thermal-zones { 269 cpu_thermal: cpu-thermal { 270 polling-delay-passive = <1000>; /* milliseconds */ 271 polling-delay = <1000>; /* milliseconds */ 272 273 thermal-sensors = <&thermal>; 274 sustainable-power = <1500>; /* milliwatts */ 275 276 trips { 277 threshold: trip-point0 { 278 temperature = <68000>; 279 hysteresis = <2000>; 280 type = "passive"; 281 }; 282 283 target: trip-point1 { 284 temperature = <85000>; 285 hysteresis = <2000>; 286 type = "passive"; 287 }; 288 289 cpu_crit: cpu_crit0 { 290 temperature = <115000>; 291 hysteresis = <2000>; 292 type = "critical"; 293 }; 294 }; 295 296 cooling-maps { 297 map0 { 298 trip = <&target>; 299 cooling-device = <&cpu0 THERMAL_NO_LIMIT 300 THERMAL_NO_LIMIT>, 301 <&cpu1 THERMAL_NO_LIMIT 302 THERMAL_NO_LIMIT>; 303 contribution = <3072>; 304 }; 305 map1 { 306 trip = <&target>; 307 cooling-device = <&cpu2 THERMAL_NO_LIMIT 308 THERMAL_NO_LIMIT>, 309 <&cpu3 THERMAL_NO_LIMIT 310 THERMAL_NO_LIMIT>; 311 contribution = <1024>; 312 }; 313 }; 314 }; 315 }; 316 317 reserved-memory { 318 #address-cells = <2>; 319 #size-cells = <2>; 320 ranges; 321 vpu_dma_reserved: vpu_dma_mem_region@b7000000 { 322 compatible = "shared-dma-pool"; 323 reg = <0 0xb7000000 0 0x500000>; 324 alignment = <0x1000>; 325 no-map; 326 }; 327 }; 328 329 timer { 330 compatible = "arm,armv8-timer"; 331 interrupt-parent = <&gic>; 332 interrupts = <GIC_PPI 13 333 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 334 <GIC_PPI 14 335 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 336 <GIC_PPI 11 337 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 338 <GIC_PPI 10 339 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 340 arm,no-tick-in-suspend; 341 }; 342 343 soc { 344 #address-cells = <2>; 345 #size-cells = <2>; 346 compatible = "simple-bus"; 347 ranges; 348 349 topckgen: clock-controller@10000000 { 350 compatible = "mediatek,mt8173-topckgen"; 351 reg = <0 0x10000000 0 0x1000>; 352 #clock-cells = <1>; 353 }; 354 355 infracfg: power-controller@10001000 { 356 compatible = "mediatek,mt8173-infracfg", "syscon"; 357 reg = <0 0x10001000 0 0x1000>; 358 #clock-cells = <1>; 359 #reset-cells = <1>; 360 }; 361 362 pericfg: power-controller@10003000 { 363 compatible = "mediatek,mt8173-pericfg", "syscon"; 364 reg = <0 0x10003000 0 0x1000>; 365 #clock-cells = <1>; 366 #reset-cells = <1>; 367 }; 368 369 syscfg_pctl_a: syscfg_pctl_a@10005000 { 370 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 371 reg = <0 0x10005000 0 0x1000>; 372 }; 373 374 pio: pinctrl@1000b000 { 375 compatible = "mediatek,mt8173-pinctrl"; 376 reg = <0 0x1000b000 0 0x1000>; 377 mediatek,pctl-regmap = <&syscfg_pctl_a>; 378 pins-are-numbered; 379 gpio-controller; 380 #gpio-cells = <2>; 381 interrupt-controller; 382 #interrupt-cells = <2>; 383 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 386 387 hdmi_pin: xxx { 388 389 /*hdmi htplg pin*/ 390 pins1 { 391 pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>; 392 input-enable; 393 bias-pull-down; 394 }; 395 }; 396 397 i2c0_pins_a: i2c0 { 398 pins1 { 399 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 400 <MT8173_PIN_46_SCL0__FUNC_SCL0>; 401 bias-disable; 402 }; 403 }; 404 405 i2c1_pins_a: i2c1 { 406 pins1 { 407 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 408 <MT8173_PIN_126_SCL1__FUNC_SCL1>; 409 bias-disable; 410 }; 411 }; 412 413 i2c2_pins_a: i2c2 { 414 pins1 { 415 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 416 <MT8173_PIN_44_SCL2__FUNC_SCL2>; 417 bias-disable; 418 }; 419 }; 420 421 i2c3_pins_a: i2c3 { 422 pins1 { 423 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 424 <MT8173_PIN_107_SCL3__FUNC_SCL3>; 425 bias-disable; 426 }; 427 }; 428 429 i2c4_pins_a: i2c4 { 430 pins1 { 431 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 432 <MT8173_PIN_134_SCL4__FUNC_SCL4>; 433 bias-disable; 434 }; 435 }; 436 437 i2c6_pins_a: i2c6 { 438 pins1 { 439 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 440 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 441 bias-disable; 442 }; 443 }; 444 }; 445 446 scpsys: syscon@10006000 { 447 compatible = "syscon", "simple-mfd"; 448 reg = <0 0x10006000 0 0x1000>; 449 #power-domain-cells = <1>; 450 451 /* System Power Manager */ 452 spm: power-controller { 453 compatible = "mediatek,mt8173-power-controller"; 454 #address-cells = <1>; 455 #size-cells = <0>; 456 #power-domain-cells = <1>; 457 458 /* power domains of the SoC */ 459 power-domain@MT8173_POWER_DOMAIN_VDEC { 460 reg = <MT8173_POWER_DOMAIN_VDEC>; 461 clocks = <&topckgen CLK_TOP_MM_SEL>; 462 clock-names = "mm"; 463 #power-domain-cells = <0>; 464 }; 465 power-domain@MT8173_POWER_DOMAIN_VENC { 466 reg = <MT8173_POWER_DOMAIN_VENC>; 467 clocks = <&topckgen CLK_TOP_MM_SEL>, 468 <&topckgen CLK_TOP_VENC_SEL>; 469 clock-names = "mm", "venc"; 470 #power-domain-cells = <0>; 471 }; 472 power-domain@MT8173_POWER_DOMAIN_ISP { 473 reg = <MT8173_POWER_DOMAIN_ISP>; 474 clocks = <&topckgen CLK_TOP_MM_SEL>; 475 clock-names = "mm"; 476 #power-domain-cells = <0>; 477 }; 478 power-domain@MT8173_POWER_DOMAIN_MM { 479 reg = <MT8173_POWER_DOMAIN_MM>; 480 clocks = <&topckgen CLK_TOP_MM_SEL>; 481 clock-names = "mm"; 482 #power-domain-cells = <0>; 483 mediatek,infracfg = <&infracfg>; 484 }; 485 power-domain@MT8173_POWER_DOMAIN_VENC_LT { 486 reg = <MT8173_POWER_DOMAIN_VENC_LT>; 487 clocks = <&topckgen CLK_TOP_MM_SEL>, 488 <&topckgen CLK_TOP_VENC_LT_SEL>; 489 clock-names = "mm", "venclt"; 490 #power-domain-cells = <0>; 491 }; 492 power-domain@MT8173_POWER_DOMAIN_AUDIO { 493 reg = <MT8173_POWER_DOMAIN_AUDIO>; 494 #power-domain-cells = <0>; 495 }; 496 power-domain@MT8173_POWER_DOMAIN_USB { 497 reg = <MT8173_POWER_DOMAIN_USB>; 498 #power-domain-cells = <0>; 499 }; 500 mfg_async: power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC { 501 reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>; 502 clocks = <&clk26m>; 503 clock-names = "mfg"; 504 #address-cells = <1>; 505 #size-cells = <0>; 506 #power-domain-cells = <1>; 507 508 power-domain@MT8173_POWER_DOMAIN_MFG_2D { 509 reg = <MT8173_POWER_DOMAIN_MFG_2D>; 510 #address-cells = <1>; 511 #size-cells = <0>; 512 #power-domain-cells = <1>; 513 514 power-domain@MT8173_POWER_DOMAIN_MFG { 515 reg = <MT8173_POWER_DOMAIN_MFG>; 516 #power-domain-cells = <0>; 517 mediatek,infracfg = <&infracfg>; 518 }; 519 }; 520 }; 521 }; 522 }; 523 524 watchdog: watchdog@10007000 { 525 compatible = "mediatek,mt8173-wdt", 526 "mediatek,mt6589-wdt"; 527 reg = <0 0x10007000 0 0x100>; 528 }; 529 530 timer: timer@10008000 { 531 compatible = "mediatek,mt8173-timer", 532 "mediatek,mt6577-timer"; 533 reg = <0 0x10008000 0 0x1000>; 534 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 535 clocks = <&infracfg CLK_INFRA_CLK_13M>, 536 <&topckgen CLK_TOP_RTC_SEL>; 537 }; 538 539 pwrap: pwrap@1000d000 { 540 compatible = "mediatek,mt8173-pwrap"; 541 reg = <0 0x1000d000 0 0x1000>; 542 reg-names = "pwrap"; 543 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 544 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 545 reset-names = "pwrap"; 546 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 547 clock-names = "spi", "wrap"; 548 }; 549 550 cec: cec@10013000 { 551 compatible = "mediatek,mt8173-cec"; 552 reg = <0 0x10013000 0 0xbc>; 553 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; 554 clocks = <&infracfg CLK_INFRA_CEC>; 555 status = "disabled"; 556 }; 557 558 vpu: vpu@10020000 { 559 compatible = "mediatek,mt8173-vpu"; 560 reg = <0 0x10020000 0 0x30000>, 561 <0 0x10050000 0 0x100>; 562 reg-names = "tcm", "cfg_reg"; 563 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 564 clocks = <&topckgen CLK_TOP_SCP_SEL>; 565 clock-names = "main"; 566 memory-region = <&vpu_dma_reserved>; 567 }; 568 569 sysirq: intpol-controller@10200620 { 570 compatible = "mediatek,mt8173-sysirq", 571 "mediatek,mt6577-sysirq"; 572 interrupt-controller; 573 #interrupt-cells = <3>; 574 interrupt-parent = <&gic>; 575 reg = <0 0x10200620 0 0x20>; 576 }; 577 578 iommu: iommu@10205000 { 579 compatible = "mediatek,mt8173-m4u"; 580 reg = <0 0x10205000 0 0x1000>; 581 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 582 clocks = <&infracfg CLK_INFRA_M4U>; 583 clock-names = "bclk"; 584 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, 585 <&larb3>, <&larb4>, <&larb5>; 586 #iommu-cells = <1>; 587 }; 588 589 efuse: efuse@10206000 { 590 compatible = "mediatek,mt8173-efuse"; 591 reg = <0 0x10206000 0 0x1000>; 592 #address-cells = <1>; 593 #size-cells = <1>; 594 thermal_calibration: calib@528 { 595 reg = <0x528 0xc>; 596 }; 597 }; 598 599 apmixedsys: clock-controller@10209000 { 600 compatible = "mediatek,mt8173-apmixedsys"; 601 reg = <0 0x10209000 0 0x1000>; 602 #clock-cells = <1>; 603 }; 604 605 hdmi_phy: hdmi-phy@10209100 { 606 compatible = "mediatek,mt8173-hdmi-phy"; 607 reg = <0 0x10209100 0 0x24>; 608 clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; 609 clock-names = "pll_ref"; 610 clock-output-names = "hdmitx_dig_cts"; 611 mediatek,ibias = <0xa>; 612 mediatek,ibias_up = <0x1c>; 613 #clock-cells = <0>; 614 #phy-cells = <0>; 615 status = "disabled"; 616 }; 617 618 gce: mailbox@10212000 { 619 compatible = "mediatek,mt8173-gce"; 620 reg = <0 0x10212000 0 0x1000>; 621 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 622 clocks = <&infracfg CLK_INFRA_GCE>; 623 clock-names = "gce"; 624 #mbox-cells = <2>; 625 }; 626 627 mipi_tx0: dsi-phy@10215000 { 628 compatible = "mediatek,mt8173-mipi-tx"; 629 reg = <0 0x10215000 0 0x1000>; 630 clocks = <&clk26m>; 631 clock-output-names = "mipi_tx0_pll"; 632 #clock-cells = <0>; 633 #phy-cells = <0>; 634 status = "disabled"; 635 }; 636 637 mipi_tx1: dsi-phy@10216000 { 638 compatible = "mediatek,mt8173-mipi-tx"; 639 reg = <0 0x10216000 0 0x1000>; 640 clocks = <&clk26m>; 641 clock-output-names = "mipi_tx1_pll"; 642 #clock-cells = <0>; 643 #phy-cells = <0>; 644 status = "disabled"; 645 }; 646 647 gic: interrupt-controller@10221000 { 648 compatible = "arm,gic-400"; 649 #interrupt-cells = <3>; 650 interrupt-parent = <&gic>; 651 interrupt-controller; 652 reg = <0 0x10221000 0 0x1000>, 653 <0 0x10222000 0 0x2000>, 654 <0 0x10224000 0 0x2000>, 655 <0 0x10226000 0 0x2000>; 656 interrupts = <GIC_PPI 9 657 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 658 }; 659 660 auxadc: auxadc@11001000 { 661 compatible = "mediatek,mt8173-auxadc"; 662 reg = <0 0x11001000 0 0x1000>; 663 clocks = <&pericfg CLK_PERI_AUXADC>; 664 clock-names = "main"; 665 #io-channel-cells = <1>; 666 }; 667 668 uart0: serial@11002000 { 669 compatible = "mediatek,mt8173-uart", 670 "mediatek,mt6577-uart"; 671 reg = <0 0x11002000 0 0x400>; 672 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 673 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 674 clock-names = "baud", "bus"; 675 status = "disabled"; 676 }; 677 678 uart1: serial@11003000 { 679 compatible = "mediatek,mt8173-uart", 680 "mediatek,mt6577-uart"; 681 reg = <0 0x11003000 0 0x400>; 682 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 683 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 684 clock-names = "baud", "bus"; 685 status = "disabled"; 686 }; 687 688 uart2: serial@11004000 { 689 compatible = "mediatek,mt8173-uart", 690 "mediatek,mt6577-uart"; 691 reg = <0 0x11004000 0 0x400>; 692 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 693 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 694 clock-names = "baud", "bus"; 695 status = "disabled"; 696 }; 697 698 uart3: serial@11005000 { 699 compatible = "mediatek,mt8173-uart", 700 "mediatek,mt6577-uart"; 701 reg = <0 0x11005000 0 0x400>; 702 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 703 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 704 clock-names = "baud", "bus"; 705 status = "disabled"; 706 }; 707 708 i2c0: i2c@11007000 { 709 compatible = "mediatek,mt8173-i2c"; 710 reg = <0 0x11007000 0 0x70>, 711 <0 0x11000100 0 0x80>; 712 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 713 clock-div = <16>; 714 clocks = <&pericfg CLK_PERI_I2C0>, 715 <&pericfg CLK_PERI_AP_DMA>; 716 clock-names = "main", "dma"; 717 pinctrl-names = "default"; 718 pinctrl-0 = <&i2c0_pins_a>; 719 #address-cells = <1>; 720 #size-cells = <0>; 721 status = "disabled"; 722 }; 723 724 i2c1: i2c@11008000 { 725 compatible = "mediatek,mt8173-i2c"; 726 reg = <0 0x11008000 0 0x70>, 727 <0 0x11000180 0 0x80>; 728 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 729 clock-div = <16>; 730 clocks = <&pericfg CLK_PERI_I2C1>, 731 <&pericfg CLK_PERI_AP_DMA>; 732 clock-names = "main", "dma"; 733 pinctrl-names = "default"; 734 pinctrl-0 = <&i2c1_pins_a>; 735 #address-cells = <1>; 736 #size-cells = <0>; 737 status = "disabled"; 738 }; 739 740 i2c2: i2c@11009000 { 741 compatible = "mediatek,mt8173-i2c"; 742 reg = <0 0x11009000 0 0x70>, 743 <0 0x11000200 0 0x80>; 744 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 745 clock-div = <16>; 746 clocks = <&pericfg CLK_PERI_I2C2>, 747 <&pericfg CLK_PERI_AP_DMA>; 748 clock-names = "main", "dma"; 749 pinctrl-names = "default"; 750 pinctrl-0 = <&i2c2_pins_a>; 751 #address-cells = <1>; 752 #size-cells = <0>; 753 status = "disabled"; 754 }; 755 756 spi: spi@1100a000 { 757 compatible = "mediatek,mt8173-spi"; 758 #address-cells = <1>; 759 #size-cells = <0>; 760 reg = <0 0x1100a000 0 0x1000>; 761 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 762 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 763 <&topckgen CLK_TOP_SPI_SEL>, 764 <&pericfg CLK_PERI_SPI0>; 765 clock-names = "parent-clk", "sel-clk", "spi-clk"; 766 status = "disabled"; 767 }; 768 769 thermal: thermal@1100b000 { 770 #thermal-sensor-cells = <0>; 771 compatible = "mediatek,mt8173-thermal"; 772 reg = <0 0x1100b000 0 0x1000>; 773 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 774 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 775 clock-names = "therm", "auxadc"; 776 resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 777 mediatek,auxadc = <&auxadc>; 778 mediatek,apmixedsys = <&apmixedsys>; 779 nvmem-cells = <&thermal_calibration>; 780 nvmem-cell-names = "calibration-data"; 781 }; 782 783 nor_flash: spi@1100d000 { 784 compatible = "mediatek,mt8173-nor"; 785 reg = <0 0x1100d000 0 0xe0>; 786 clocks = <&pericfg CLK_PERI_SPI>, 787 <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 788 clock-names = "spi", "sf"; 789 #address-cells = <1>; 790 #size-cells = <0>; 791 status = "disabled"; 792 }; 793 794 i2c3: i2c@11010000 { 795 compatible = "mediatek,mt8173-i2c"; 796 reg = <0 0x11010000 0 0x70>, 797 <0 0x11000280 0 0x80>; 798 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 799 clock-div = <16>; 800 clocks = <&pericfg CLK_PERI_I2C3>, 801 <&pericfg CLK_PERI_AP_DMA>; 802 clock-names = "main", "dma"; 803 pinctrl-names = "default"; 804 pinctrl-0 = <&i2c3_pins_a>; 805 #address-cells = <1>; 806 #size-cells = <0>; 807 status = "disabled"; 808 }; 809 810 i2c4: i2c@11011000 { 811 compatible = "mediatek,mt8173-i2c"; 812 reg = <0 0x11011000 0 0x70>, 813 <0 0x11000300 0 0x80>; 814 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 815 clock-div = <16>; 816 clocks = <&pericfg CLK_PERI_I2C4>, 817 <&pericfg CLK_PERI_AP_DMA>; 818 clock-names = "main", "dma"; 819 pinctrl-names = "default"; 820 pinctrl-0 = <&i2c4_pins_a>; 821 #address-cells = <1>; 822 #size-cells = <0>; 823 status = "disabled"; 824 }; 825 826 hdmiddc0: i2c@11012000 { 827 compatible = "mediatek,mt8173-hdmi-ddc"; 828 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 829 reg = <0 0x11012000 0 0x1C>; 830 clocks = <&pericfg CLK_PERI_I2C5>; 831 clock-names = "ddc-i2c"; 832 }; 833 834 i2c6: i2c@11013000 { 835 compatible = "mediatek,mt8173-i2c"; 836 reg = <0 0x11013000 0 0x70>, 837 <0 0x11000080 0 0x80>; 838 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 839 clock-div = <16>; 840 clocks = <&pericfg CLK_PERI_I2C6>, 841 <&pericfg CLK_PERI_AP_DMA>; 842 clock-names = "main", "dma"; 843 pinctrl-names = "default"; 844 pinctrl-0 = <&i2c6_pins_a>; 845 #address-cells = <1>; 846 #size-cells = <0>; 847 status = "disabled"; 848 }; 849 850 afe: audio-controller@11220000 { 851 compatible = "mediatek,mt8173-afe-pcm"; 852 reg = <0 0x11220000 0 0x1000>; 853 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 854 power-domains = <&spm MT8173_POWER_DOMAIN_AUDIO>; 855 clocks = <&infracfg CLK_INFRA_AUDIO>, 856 <&topckgen CLK_TOP_AUDIO_SEL>, 857 <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 858 <&topckgen CLK_TOP_APLL1_DIV0>, 859 <&topckgen CLK_TOP_APLL2_DIV0>, 860 <&topckgen CLK_TOP_I2S0_M_SEL>, 861 <&topckgen CLK_TOP_I2S1_M_SEL>, 862 <&topckgen CLK_TOP_I2S2_M_SEL>, 863 <&topckgen CLK_TOP_I2S3_M_SEL>, 864 <&topckgen CLK_TOP_I2S3_B_SEL>; 865 clock-names = "infra_sys_audio_clk", 866 "top_pdn_audio", 867 "top_pdn_aud_intbus", 868 "bck0", 869 "bck1", 870 "i2s0_m", 871 "i2s1_m", 872 "i2s2_m", 873 "i2s3_m", 874 "i2s3_b"; 875 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 876 <&topckgen CLK_TOP_AUD_2_SEL>; 877 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 878 <&topckgen CLK_TOP_APLL2>; 879 }; 880 881 mmc0: mmc@11230000 { 882 compatible = "mediatek,mt8173-mmc"; 883 reg = <0 0x11230000 0 0x1000>; 884 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 885 clocks = <&pericfg CLK_PERI_MSDC30_0>, 886 <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 887 clock-names = "source", "hclk"; 888 status = "disabled"; 889 }; 890 891 mmc1: mmc@11240000 { 892 compatible = "mediatek,mt8173-mmc"; 893 reg = <0 0x11240000 0 0x1000>; 894 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 895 clocks = <&pericfg CLK_PERI_MSDC30_1>, 896 <&topckgen CLK_TOP_AXI_SEL>; 897 clock-names = "source", "hclk"; 898 status = "disabled"; 899 }; 900 901 mmc2: mmc@11250000 { 902 compatible = "mediatek,mt8173-mmc"; 903 reg = <0 0x11250000 0 0x1000>; 904 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 905 clocks = <&pericfg CLK_PERI_MSDC30_2>, 906 <&topckgen CLK_TOP_AXI_SEL>; 907 clock-names = "source", "hclk"; 908 status = "disabled"; 909 }; 910 911 mmc3: mmc@11260000 { 912 compatible = "mediatek,mt8173-mmc"; 913 reg = <0 0x11260000 0 0x1000>; 914 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 915 clocks = <&pericfg CLK_PERI_MSDC30_3>, 916 <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 917 clock-names = "source", "hclk"; 918 status = "disabled"; 919 }; 920 921 ssusb: usb@11271000 { 922 compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3"; 923 reg = <0 0x11271000 0 0x3000>, 924 <0 0x11280700 0 0x0100>; 925 reg-names = "mac", "ippc"; 926 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>; 927 phys = <&u2port0 PHY_TYPE_USB2>, 928 <&u3port0 PHY_TYPE_USB3>, 929 <&u2port1 PHY_TYPE_USB2>; 930 power-domains = <&spm MT8173_POWER_DOMAIN_USB>; 931 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 932 clock-names = "sys_ck", "ref_ck"; 933 mediatek,syscon-wakeup = <&pericfg 0x400 1>; 934 #address-cells = <2>; 935 #size-cells = <2>; 936 ranges; 937 status = "disabled"; 938 939 usb_host: usb@11270000 { 940 compatible = "mediatek,mt8173-xhci", 941 "mediatek,mtk-xhci"; 942 reg = <0 0x11270000 0 0x1000>; 943 reg-names = "mac"; 944 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 945 power-domains = <&spm MT8173_POWER_DOMAIN_USB>; 946 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 947 clock-names = "sys_ck", "ref_ck"; 948 status = "disabled"; 949 }; 950 }; 951 952 u3phy: t-phy@11290000 { 953 compatible = "mediatek,mt8173-u3phy"; 954 reg = <0 0x11290000 0 0x800>; 955 #address-cells = <2>; 956 #size-cells = <2>; 957 ranges; 958 status = "okay"; 959 960 u2port0: usb-phy@11290800 { 961 reg = <0 0x11290800 0 0x100>; 962 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 963 clock-names = "ref"; 964 #phy-cells = <1>; 965 status = "okay"; 966 }; 967 968 u3port0: usb-phy@11290900 { 969 reg = <0 0x11290900 0 0x700>; 970 clocks = <&clk26m>; 971 clock-names = "ref"; 972 #phy-cells = <1>; 973 status = "okay"; 974 }; 975 976 u2port1: usb-phy@11291000 { 977 reg = <0 0x11291000 0 0x100>; 978 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 979 clock-names = "ref"; 980 #phy-cells = <1>; 981 status = "okay"; 982 }; 983 }; 984 985 mmsys: syscon@14000000 { 986 compatible = "mediatek,mt8173-mmsys", "syscon"; 987 reg = <0 0x14000000 0 0x1000>; 988 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 989 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; 990 assigned-clock-rates = <400000000>; 991 #clock-cells = <1>; 992 #reset-cells = <1>; 993 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 994 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 995 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 996 }; 997 998 mdp_rdma0: rdma@14001000 { 999 compatible = "mediatek,mt8173-mdp-rdma", 1000 "mediatek,mt8173-mdp"; 1001 reg = <0 0x14001000 0 0x1000>; 1002 clocks = <&mmsys CLK_MM_MDP_RDMA0>, 1003 <&mmsys CLK_MM_MUTEX_32K>; 1004 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1005 iommus = <&iommu M4U_PORT_MDP_RDMA0>; 1006 mediatek,vpu = <&vpu>; 1007 }; 1008 1009 mdp_rdma1: rdma@14002000 { 1010 compatible = "mediatek,mt8173-mdp-rdma"; 1011 reg = <0 0x14002000 0 0x1000>; 1012 clocks = <&mmsys CLK_MM_MDP_RDMA1>, 1013 <&mmsys CLK_MM_MUTEX_32K>; 1014 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1015 iommus = <&iommu M4U_PORT_MDP_RDMA1>; 1016 }; 1017 1018 mdp_rsz0: rsz@14003000 { 1019 compatible = "mediatek,mt8173-mdp-rsz"; 1020 reg = <0 0x14003000 0 0x1000>; 1021 clocks = <&mmsys CLK_MM_MDP_RSZ0>; 1022 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1023 }; 1024 1025 mdp_rsz1: rsz@14004000 { 1026 compatible = "mediatek,mt8173-mdp-rsz"; 1027 reg = <0 0x14004000 0 0x1000>; 1028 clocks = <&mmsys CLK_MM_MDP_RSZ1>; 1029 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1030 }; 1031 1032 mdp_rsz2: rsz@14005000 { 1033 compatible = "mediatek,mt8173-mdp-rsz"; 1034 reg = <0 0x14005000 0 0x1000>; 1035 clocks = <&mmsys CLK_MM_MDP_RSZ2>; 1036 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1037 }; 1038 1039 mdp_wdma0: wdma@14006000 { 1040 compatible = "mediatek,mt8173-mdp-wdma"; 1041 reg = <0 0x14006000 0 0x1000>; 1042 clocks = <&mmsys CLK_MM_MDP_WDMA>; 1043 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1044 iommus = <&iommu M4U_PORT_MDP_WDMA>; 1045 }; 1046 1047 mdp_wrot0: wrot@14007000 { 1048 compatible = "mediatek,mt8173-mdp-wrot"; 1049 reg = <0 0x14007000 0 0x1000>; 1050 clocks = <&mmsys CLK_MM_MDP_WROT0>; 1051 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1052 iommus = <&iommu M4U_PORT_MDP_WROT0>; 1053 }; 1054 1055 mdp_wrot1: wrot@14008000 { 1056 compatible = "mediatek,mt8173-mdp-wrot"; 1057 reg = <0 0x14008000 0 0x1000>; 1058 clocks = <&mmsys CLK_MM_MDP_WROT1>; 1059 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1060 iommus = <&iommu M4U_PORT_MDP_WROT1>; 1061 }; 1062 1063 ovl0: ovl@1400c000 { 1064 compatible = "mediatek,mt8173-disp-ovl"; 1065 reg = <0 0x1400c000 0 0x1000>; 1066 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 1067 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1068 clocks = <&mmsys CLK_MM_DISP_OVL0>; 1069 iommus = <&iommu M4U_PORT_DISP_OVL0>; 1070 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1071 }; 1072 1073 ovl1: ovl@1400d000 { 1074 compatible = "mediatek,mt8173-disp-ovl"; 1075 reg = <0 0x1400d000 0 0x1000>; 1076 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; 1077 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1078 clocks = <&mmsys CLK_MM_DISP_OVL1>; 1079 iommus = <&iommu M4U_PORT_DISP_OVL1>; 1080 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 1081 }; 1082 1083 rdma0: rdma@1400e000 { 1084 compatible = "mediatek,mt8173-disp-rdma"; 1085 reg = <0 0x1400e000 0 0x1000>; 1086 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 1087 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1088 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1089 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 1090 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1091 }; 1092 1093 rdma1: rdma@1400f000 { 1094 compatible = "mediatek,mt8173-disp-rdma"; 1095 reg = <0 0x1400f000 0 0x1000>; 1096 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; 1097 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1098 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 1099 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 1100 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; 1101 }; 1102 1103 rdma2: rdma@14010000 { 1104 compatible = "mediatek,mt8173-disp-rdma"; 1105 reg = <0 0x14010000 0 0x1000>; 1106 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; 1107 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1108 clocks = <&mmsys CLK_MM_DISP_RDMA2>; 1109 iommus = <&iommu M4U_PORT_DISP_RDMA2>; 1110 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; 1111 }; 1112 1113 wdma0: wdma@14011000 { 1114 compatible = "mediatek,mt8173-disp-wdma"; 1115 reg = <0 0x14011000 0 0x1000>; 1116 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 1117 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1118 clocks = <&mmsys CLK_MM_DISP_WDMA0>; 1119 iommus = <&iommu M4U_PORT_DISP_WDMA0>; 1120 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 1121 }; 1122 1123 wdma1: wdma@14012000 { 1124 compatible = "mediatek,mt8173-disp-wdma"; 1125 reg = <0 0x14012000 0 0x1000>; 1126 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; 1127 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1128 clocks = <&mmsys CLK_MM_DISP_WDMA1>; 1129 iommus = <&iommu M4U_PORT_DISP_WDMA1>; 1130 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; 1131 }; 1132 1133 color0: color@14013000 { 1134 compatible = "mediatek,mt8173-disp-color"; 1135 reg = <0 0x14013000 0 0x1000>; 1136 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; 1137 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1138 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1139 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>; 1140 }; 1141 1142 color1: color@14014000 { 1143 compatible = "mediatek,mt8173-disp-color"; 1144 reg = <0 0x14014000 0 0x1000>; 1145 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 1146 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1147 clocks = <&mmsys CLK_MM_DISP_COLOR1>; 1148 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; 1149 }; 1150 1151 aal@14015000 { 1152 compatible = "mediatek,mt8173-disp-aal"; 1153 reg = <0 0x14015000 0 0x1000>; 1154 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 1155 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1156 clocks = <&mmsys CLK_MM_DISP_AAL>; 1157 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; 1158 }; 1159 1160 gamma@14016000 { 1161 compatible = "mediatek,mt8173-disp-gamma"; 1162 reg = <0 0x14016000 0 0x1000>; 1163 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 1164 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1165 clocks = <&mmsys CLK_MM_DISP_GAMMA>; 1166 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; 1167 }; 1168 1169 merge@14017000 { 1170 compatible = "mediatek,mt8173-disp-merge"; 1171 reg = <0 0x14017000 0 0x1000>; 1172 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1173 clocks = <&mmsys CLK_MM_DISP_MERGE>; 1174 }; 1175 1176 split0: split@14018000 { 1177 compatible = "mediatek,mt8173-disp-split"; 1178 reg = <0 0x14018000 0 0x1000>; 1179 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1180 clocks = <&mmsys CLK_MM_DISP_SPLIT0>; 1181 }; 1182 1183 split1: split@14019000 { 1184 compatible = "mediatek,mt8173-disp-split"; 1185 reg = <0 0x14019000 0 0x1000>; 1186 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1187 clocks = <&mmsys CLK_MM_DISP_SPLIT1>; 1188 }; 1189 1190 ufoe@1401a000 { 1191 compatible = "mediatek,mt8173-disp-ufoe"; 1192 reg = <0 0x1401a000 0 0x1000>; 1193 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 1194 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1195 clocks = <&mmsys CLK_MM_DISP_UFOE>; 1196 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>; 1197 }; 1198 1199 dsi0: dsi@1401b000 { 1200 compatible = "mediatek,mt8173-dsi"; 1201 reg = <0 0x1401b000 0 0x1000>; 1202 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 1203 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1204 clocks = <&mmsys CLK_MM_DSI0_ENGINE>, 1205 <&mmsys CLK_MM_DSI0_DIGITAL>, 1206 <&mipi_tx0>; 1207 clock-names = "engine", "digital", "hs"; 1208 resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>; 1209 phys = <&mipi_tx0>; 1210 phy-names = "dphy"; 1211 status = "disabled"; 1212 }; 1213 1214 dsi1: dsi@1401c000 { 1215 compatible = "mediatek,mt8173-dsi"; 1216 reg = <0 0x1401c000 0 0x1000>; 1217 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 1218 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1219 clocks = <&mmsys CLK_MM_DSI1_ENGINE>, 1220 <&mmsys CLK_MM_DSI1_DIGITAL>, 1221 <&mipi_tx1>; 1222 clock-names = "engine", "digital", "hs"; 1223 phys = <&mipi_tx1>; 1224 phy-names = "dphy"; 1225 status = "disabled"; 1226 }; 1227 1228 dpi0: dpi@1401d000 { 1229 compatible = "mediatek,mt8173-dpi"; 1230 reg = <0 0x1401d000 0 0x1000>; 1231 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 1232 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1233 clocks = <&mmsys CLK_MM_DPI_PIXEL>, 1234 <&mmsys CLK_MM_DPI_ENGINE>, 1235 <&apmixedsys CLK_APMIXED_TVDPLL>; 1236 clock-names = "pixel", "engine", "pll"; 1237 status = "disabled"; 1238 1239 port { 1240 dpi0_out: endpoint { 1241 remote-endpoint = <&hdmi0_in>; 1242 }; 1243 }; 1244 }; 1245 1246 pwm0: pwm@1401e000 { 1247 compatible = "mediatek,mt8173-disp-pwm", 1248 "mediatek,mt6595-disp-pwm"; 1249 reg = <0 0x1401e000 0 0x1000>; 1250 #pwm-cells = <2>; 1251 clocks = <&mmsys CLK_MM_DISP_PWM026M>, 1252 <&mmsys CLK_MM_DISP_PWM0MM>; 1253 clock-names = "main", "mm"; 1254 status = "disabled"; 1255 }; 1256 1257 pwm1: pwm@1401f000 { 1258 compatible = "mediatek,mt8173-disp-pwm", 1259 "mediatek,mt6595-disp-pwm"; 1260 reg = <0 0x1401f000 0 0x1000>; 1261 #pwm-cells = <2>; 1262 clocks = <&mmsys CLK_MM_DISP_PWM126M>, 1263 <&mmsys CLK_MM_DISP_PWM1MM>; 1264 clock-names = "main", "mm"; 1265 status = "disabled"; 1266 }; 1267 1268 mutex: mutex@14020000 { 1269 compatible = "mediatek,mt8173-disp-mutex"; 1270 reg = <0 0x14020000 0 0x1000>; 1271 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 1272 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1273 clocks = <&mmsys CLK_MM_MUTEX_32K>; 1274 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0 0x1000>; 1275 mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>, 1276 <CMDQ_EVENT_MUTEX1_STREAM_EOF>; 1277 }; 1278 1279 larb0: larb@14021000 { 1280 compatible = "mediatek,mt8173-smi-larb"; 1281 reg = <0 0x14021000 0 0x1000>; 1282 mediatek,smi = <&smi_common>; 1283 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1284 clocks = <&mmsys CLK_MM_SMI_LARB0>, 1285 <&mmsys CLK_MM_SMI_LARB0>; 1286 clock-names = "apb", "smi"; 1287 }; 1288 1289 smi_common: smi@14022000 { 1290 compatible = "mediatek,mt8173-smi-common"; 1291 reg = <0 0x14022000 0 0x1000>; 1292 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1293 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1294 <&mmsys CLK_MM_SMI_COMMON>; 1295 clock-names = "apb", "smi"; 1296 }; 1297 1298 od@14023000 { 1299 compatible = "mediatek,mt8173-disp-od"; 1300 reg = <0 0x14023000 0 0x1000>; 1301 clocks = <&mmsys CLK_MM_DISP_OD>; 1302 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>; 1303 }; 1304 1305 hdmi0: hdmi@14025000 { 1306 compatible = "mediatek,mt8173-hdmi"; 1307 reg = <0 0x14025000 0 0x400>; 1308 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>; 1309 clocks = <&mmsys CLK_MM_HDMI_PIXEL>, 1310 <&mmsys CLK_MM_HDMI_PLLCK>, 1311 <&mmsys CLK_MM_HDMI_AUDIO>, 1312 <&mmsys CLK_MM_HDMI_SPDIF>; 1313 clock-names = "pixel", "pll", "bclk", "spdif"; 1314 pinctrl-names = "default"; 1315 pinctrl-0 = <&hdmi_pin>; 1316 phys = <&hdmi_phy>; 1317 phy-names = "hdmi"; 1318 mediatek,syscon-hdmi = <&mmsys 0x900>; 1319 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; 1320 assigned-clock-parents = <&hdmi_phy>; 1321 status = "disabled"; 1322 1323 ports { 1324 #address-cells = <1>; 1325 #size-cells = <0>; 1326 1327 port@0 { 1328 reg = <0>; 1329 1330 hdmi0_in: endpoint { 1331 remote-endpoint = <&dpi0_out>; 1332 }; 1333 }; 1334 }; 1335 }; 1336 1337 larb4: larb@14027000 { 1338 compatible = "mediatek,mt8173-smi-larb"; 1339 reg = <0 0x14027000 0 0x1000>; 1340 mediatek,smi = <&smi_common>; 1341 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1342 clocks = <&mmsys CLK_MM_SMI_LARB4>, 1343 <&mmsys CLK_MM_SMI_LARB4>; 1344 clock-names = "apb", "smi"; 1345 }; 1346 1347 imgsys: clock-controller@15000000 { 1348 compatible = "mediatek,mt8173-imgsys", "syscon"; 1349 reg = <0 0x15000000 0 0x1000>; 1350 #clock-cells = <1>; 1351 }; 1352 1353 larb2: larb@15001000 { 1354 compatible = "mediatek,mt8173-smi-larb"; 1355 reg = <0 0x15001000 0 0x1000>; 1356 mediatek,smi = <&smi_common>; 1357 power-domains = <&spm MT8173_POWER_DOMAIN_ISP>; 1358 clocks = <&imgsys CLK_IMG_LARB2_SMI>, 1359 <&imgsys CLK_IMG_LARB2_SMI>; 1360 clock-names = "apb", "smi"; 1361 }; 1362 1363 vdecsys: clock-controller@16000000 { 1364 compatible = "mediatek,mt8173-vdecsys", "syscon"; 1365 reg = <0 0x16000000 0 0x1000>; 1366 #clock-cells = <1>; 1367 }; 1368 1369 vcodec_dec: vcodec@16000000 { 1370 compatible = "mediatek,mt8173-vcodec-dec"; 1371 reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */ 1372 <0 0x16020000 0 0x1000>, /* VDEC_MISC */ 1373 <0 0x16021000 0 0x800>, /* VDEC_LD */ 1374 <0 0x16021800 0 0x800>, /* VDEC_TOP */ 1375 <0 0x16022000 0 0x1000>, /* VDEC_CM */ 1376 <0 0x16023000 0 0x1000>, /* VDEC_AD */ 1377 <0 0x16024000 0 0x1000>, /* VDEC_AV */ 1378 <0 0x16025000 0 0x1000>, /* VDEC_PP */ 1379 <0 0x16026800 0 0x800>, /* VDEC_HWD */ 1380 <0 0x16027000 0 0x800>, /* VDEC_HWQ */ 1381 <0 0x16027800 0 0x800>, /* VDEC_HWB */ 1382 <0 0x16028400 0 0x400>; /* VDEC_HWG */ 1383 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; 1384 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, 1385 <&iommu M4U_PORT_HW_VDEC_PP_EXT>, 1386 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, 1387 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, 1388 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, 1389 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, 1390 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, 1391 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; 1392 mediatek,vpu = <&vpu>; 1393 power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>; 1394 clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, 1395 <&topckgen CLK_TOP_UNIVPLL_D2>, 1396 <&topckgen CLK_TOP_CCI400_SEL>, 1397 <&topckgen CLK_TOP_VDEC_SEL>, 1398 <&topckgen CLK_TOP_VCODECPLL>, 1399 <&apmixedsys CLK_APMIXED_VENCPLL>, 1400 <&topckgen CLK_TOP_VENC_LT_SEL>, 1401 <&topckgen CLK_TOP_VCODECPLL_370P5>; 1402 clock-names = "vcodecpll", 1403 "univpll_d2", 1404 "clk_cci400_sel", 1405 "vdec_sel", 1406 "vdecpll", 1407 "vencpll", 1408 "venc_lt_sel", 1409 "vdec_bus_clk_src"; 1410 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>, 1411 <&topckgen CLK_TOP_CCI400_SEL>, 1412 <&topckgen CLK_TOP_VDEC_SEL>, 1413 <&apmixedsys CLK_APMIXED_VCODECPLL>, 1414 <&apmixedsys CLK_APMIXED_VENCPLL>; 1415 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>, 1416 <&topckgen CLK_TOP_UNIVPLL_D2>, 1417 <&topckgen CLK_TOP_VCODECPLL>; 1418 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>; 1419 }; 1420 1421 larb1: larb@16010000 { 1422 compatible = "mediatek,mt8173-smi-larb"; 1423 reg = <0 0x16010000 0 0x1000>; 1424 mediatek,smi = <&smi_common>; 1425 power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>; 1426 clocks = <&vdecsys CLK_VDEC_CKEN>, 1427 <&vdecsys CLK_VDEC_LARB_CKEN>; 1428 clock-names = "apb", "smi"; 1429 }; 1430 1431 vencsys: clock-controller@18000000 { 1432 compatible = "mediatek,mt8173-vencsys", "syscon"; 1433 reg = <0 0x18000000 0 0x1000>; 1434 #clock-cells = <1>; 1435 }; 1436 1437 larb3: larb@18001000 { 1438 compatible = "mediatek,mt8173-smi-larb"; 1439 reg = <0 0x18001000 0 0x1000>; 1440 mediatek,smi = <&smi_common>; 1441 power-domains = <&spm MT8173_POWER_DOMAIN_VENC>; 1442 clocks = <&vencsys CLK_VENC_CKE1>, 1443 <&vencsys CLK_VENC_CKE0>; 1444 clock-names = "apb", "smi"; 1445 }; 1446 1447 vcodec_enc_avc: vcodec@18002000 { 1448 compatible = "mediatek,mt8173-vcodec-enc"; 1449 reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */ 1450 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; 1451 iommus = <&iommu M4U_PORT_VENC_RCPU>, 1452 <&iommu M4U_PORT_VENC_REC>, 1453 <&iommu M4U_PORT_VENC_BSDMA>, 1454 <&iommu M4U_PORT_VENC_SV_COMV>, 1455 <&iommu M4U_PORT_VENC_RD_COMV>, 1456 <&iommu M4U_PORT_VENC_CUR_LUMA>, 1457 <&iommu M4U_PORT_VENC_CUR_CHROMA>, 1458 <&iommu M4U_PORT_VENC_REF_LUMA>, 1459 <&iommu M4U_PORT_VENC_REF_CHROMA>, 1460 <&iommu M4U_PORT_VENC_NBM_RDMA>, 1461 <&iommu M4U_PORT_VENC_NBM_WDMA>; 1462 mediatek,vpu = <&vpu>; 1463 clocks = <&topckgen CLK_TOP_VENC_SEL>; 1464 clock-names = "venc_sel"; 1465 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; 1466 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>; 1467 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 1468 }; 1469 1470 jpegdec: jpegdec@18004000 { 1471 compatible = "mediatek,mt8173-jpgdec"; 1472 reg = <0 0x18004000 0 0x1000>; 1473 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW>; 1474 clocks = <&vencsys CLK_VENC_CKE0>, 1475 <&vencsys CLK_VENC_CKE3>; 1476 clock-names = "jpgdec-smi", 1477 "jpgdec"; 1478 power-domains = <&spm MT8173_POWER_DOMAIN_VENC>; 1479 iommus = <&iommu M4U_PORT_JPGDEC_WDMA>, 1480 <&iommu M4U_PORT_JPGDEC_BSDMA>; 1481 }; 1482 1483 vencltsys: clock-controller@19000000 { 1484 compatible = "mediatek,mt8173-vencltsys", "syscon"; 1485 reg = <0 0x19000000 0 0x1000>; 1486 #clock-cells = <1>; 1487 }; 1488 1489 larb5: larb@19001000 { 1490 compatible = "mediatek,mt8173-smi-larb"; 1491 reg = <0 0x19001000 0 0x1000>; 1492 mediatek,smi = <&smi_common>; 1493 power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>; 1494 clocks = <&vencltsys CLK_VENCLT_CKE1>, 1495 <&vencltsys CLK_VENCLT_CKE0>; 1496 clock-names = "apb", "smi"; 1497 }; 1498 1499 vcodec_enc_vp8: vcodec@19002000 { 1500 compatible = "mediatek,mt8173-vcodec-enc-vp8"; 1501 reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ 1502 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; 1503 iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>, 1504 <&iommu M4U_PORT_VENC_REC_FRM_SET2>, 1505 <&iommu M4U_PORT_VENC_BSDMA_SET2>, 1506 <&iommu M4U_PORT_VENC_SV_COMA_SET2>, 1507 <&iommu M4U_PORT_VENC_RD_COMA_SET2>, 1508 <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, 1509 <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, 1510 <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, 1511 <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; 1512 mediatek,vpu = <&vpu>; 1513 clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; 1514 clock-names = "venc_lt_sel"; 1515 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; 1516 assigned-clock-parents = 1517 <&topckgen CLK_TOP_VCODECPLL_370P5>; 1518 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; 1519 }; 1520 }; 1521}; 1522