1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Eddie Huang <eddie.huang@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11 * GNU General Public License for more details.
12 */
13
14#include <dt-bindings/clock/mt8173-clk.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/interrupt-controller/arm-gic.h>
17#include <dt-bindings/phy/phy.h>
18#include <dt-bindings/power/mt8173-power.h>
19#include <dt-bindings/reset/mt8173-resets.h>
20#include "mt8173-pinfunc.h"
21
22/ {
23	compatible = "mediatek,mt8173";
24	interrupt-parent = <&sysirq>;
25	#address-cells = <2>;
26	#size-cells = <2>;
27
28	cpus {
29		#address-cells = <1>;
30		#size-cells = <0>;
31
32		cpu-map {
33			cluster0 {
34				core0 {
35					cpu = <&cpu0>;
36				};
37				core1 {
38					cpu = <&cpu1>;
39				};
40			};
41
42			cluster1 {
43				core0 {
44					cpu = <&cpu2>;
45				};
46				core1 {
47					cpu = <&cpu3>;
48				};
49			};
50		};
51
52		cpu0: cpu@0 {
53			device_type = "cpu";
54			compatible = "arm,cortex-a53";
55			reg = <0x000>;
56			enable-method = "psci";
57			cpu-idle-states = <&CPU_SLEEP_0>;
58		};
59
60		cpu1: cpu@1 {
61			device_type = "cpu";
62			compatible = "arm,cortex-a53";
63			reg = <0x001>;
64			enable-method = "psci";
65			cpu-idle-states = <&CPU_SLEEP_0>;
66		};
67
68		cpu2: cpu@100 {
69			device_type = "cpu";
70			compatible = "arm,cortex-a57";
71			reg = <0x100>;
72			enable-method = "psci";
73			cpu-idle-states = <&CPU_SLEEP_0>;
74		};
75
76		cpu3: cpu@101 {
77			device_type = "cpu";
78			compatible = "arm,cortex-a57";
79			reg = <0x101>;
80			enable-method = "psci";
81			cpu-idle-states = <&CPU_SLEEP_0>;
82		};
83
84		idle-states {
85			entry-method = "psci";
86
87			CPU_SLEEP_0: cpu-sleep-0 {
88				compatible = "arm,idle-state";
89				local-timer-stop;
90				entry-latency-us = <639>;
91				exit-latency-us = <680>;
92				min-residency-us = <1088>;
93				arm,psci-suspend-param = <0x0010000>;
94			};
95		};
96	};
97
98	psci {
99		compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
100		method = "smc";
101		cpu_suspend   = <0x84000001>;
102		cpu_off	      = <0x84000002>;
103		cpu_on	      = <0x84000003>;
104	};
105
106	clk26m: oscillator@0 {
107		compatible = "fixed-clock";
108		#clock-cells = <0>;
109		clock-frequency = <26000000>;
110		clock-output-names = "clk26m";
111	};
112
113	clk32k: oscillator@1 {
114		compatible = "fixed-clock";
115		#clock-cells = <0>;
116		clock-frequency = <32000>;
117		clock-output-names = "clk32k";
118	};
119
120	cpum_ck: oscillator@2 {
121		compatible = "fixed-clock";
122		#clock-cells = <0>;
123		clock-frequency = <0>;
124		clock-output-names = "cpum_ck";
125	};
126
127	timer {
128		compatible = "arm,armv8-timer";
129		interrupt-parent = <&gic>;
130		interrupts = <GIC_PPI 13
131			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
132			     <GIC_PPI 14
133			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
134			     <GIC_PPI 11
135			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
136			     <GIC_PPI 10
137			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
138	};
139
140	soc {
141		#address-cells = <2>;
142		#size-cells = <2>;
143		compatible = "simple-bus";
144		ranges;
145
146		topckgen: clock-controller@10000000 {
147			compatible = "mediatek,mt8173-topckgen";
148			reg = <0 0x10000000 0 0x1000>;
149			#clock-cells = <1>;
150		};
151
152		infracfg: power-controller@10001000 {
153			compatible = "mediatek,mt8173-infracfg", "syscon";
154			reg = <0 0x10001000 0 0x1000>;
155			#clock-cells = <1>;
156			#reset-cells = <1>;
157		};
158
159		pericfg: power-controller@10003000 {
160			compatible = "mediatek,mt8173-pericfg", "syscon";
161			reg = <0 0x10003000 0 0x1000>;
162			#clock-cells = <1>;
163			#reset-cells = <1>;
164		};
165
166		syscfg_pctl_a: syscfg_pctl_a@10005000 {
167			compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
168			reg = <0 0x10005000 0 0x1000>;
169		};
170
171		pio: pinctrl@0x10005000 {
172			compatible = "mediatek,mt8173-pinctrl";
173			reg = <0 0x1000b000 0 0x1000>;
174			mediatek,pctl-regmap = <&syscfg_pctl_a>;
175			pins-are-numbered;
176			gpio-controller;
177			#gpio-cells = <2>;
178			interrupt-controller;
179			#interrupt-cells = <2>;
180			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
181				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
182				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
183
184			i2c0_pins_a: i2c0 {
185				pins1 {
186					pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
187						 <MT8173_PIN_46_SCL0__FUNC_SCL0>;
188					bias-disable;
189				};
190			};
191
192			i2c1_pins_a: i2c1 {
193				pins1 {
194					pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
195						 <MT8173_PIN_126_SCL1__FUNC_SCL1>;
196					bias-disable;
197				};
198			};
199
200			i2c2_pins_a: i2c2 {
201				pins1 {
202					pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
203						 <MT8173_PIN_44_SCL2__FUNC_SCL2>;
204					bias-disable;
205				};
206			};
207
208			i2c3_pins_a: i2c3 {
209				pins1 {
210					pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
211						 <MT8173_PIN_107_SCL3__FUNC_SCL3>;
212					bias-disable;
213				};
214			};
215
216			i2c4_pins_a: i2c4 {
217				pins1 {
218					pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
219						 <MT8173_PIN_134_SCL4__FUNC_SCL4>;
220					bias-disable;
221				};
222			};
223
224			i2c6_pins_a: i2c6 {
225				pins1 {
226					pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
227						 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
228					bias-disable;
229				};
230			};
231		};
232
233		scpsys: scpsys@10006000 {
234			compatible = "mediatek,mt8173-scpsys";
235			#power-domain-cells = <1>;
236			reg = <0 0x10006000 0 0x1000>;
237			clocks = <&clk26m>,
238				 <&topckgen CLK_TOP_MM_SEL>,
239				 <&topckgen CLK_TOP_VENC_SEL>,
240				 <&topckgen CLK_TOP_VENC_LT_SEL>;
241			clock-names = "mfg", "mm", "venc", "venc_lt";
242			infracfg = <&infracfg>;
243		};
244
245		watchdog: watchdog@10007000 {
246			compatible = "mediatek,mt8173-wdt",
247				     "mediatek,mt6589-wdt";
248			reg = <0 0x10007000 0 0x100>;
249		};
250
251		timer: timer@10008000 {
252			compatible = "mediatek,mt8173-timer",
253				     "mediatek,mt6577-timer";
254			reg = <0 0x10008000 0 0x1000>;
255			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
256			clocks = <&infracfg CLK_INFRA_CLK_13M>,
257				 <&topckgen CLK_TOP_RTC_SEL>;
258		};
259
260		pwrap: pwrap@1000d000 {
261			compatible = "mediatek,mt8173-pwrap";
262			reg = <0 0x1000d000 0 0x1000>;
263			reg-names = "pwrap";
264			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
265			resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
266			reset-names = "pwrap";
267			clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
268			clock-names = "spi", "wrap";
269		};
270
271		sysirq: intpol-controller@10200620 {
272			compatible = "mediatek,mt8173-sysirq",
273				     "mediatek,mt6577-sysirq";
274			interrupt-controller;
275			#interrupt-cells = <3>;
276			interrupt-parent = <&gic>;
277			reg = <0 0x10200620 0 0x20>;
278		};
279
280		apmixedsys: clock-controller@10209000 {
281			compatible = "mediatek,mt8173-apmixedsys";
282			reg = <0 0x10209000 0 0x1000>;
283			#clock-cells = <1>;
284		};
285
286		gic: interrupt-controller@10220000 {
287			compatible = "arm,gic-400";
288			#interrupt-cells = <3>;
289			interrupt-parent = <&gic>;
290			interrupt-controller;
291			reg = <0 0x10221000 0 0x1000>,
292			      <0 0x10222000 0 0x2000>,
293			      <0 0x10224000 0 0x2000>,
294			      <0 0x10226000 0 0x2000>;
295			interrupts = <GIC_PPI 9
296				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
297		};
298
299		uart0: serial@11002000 {
300			compatible = "mediatek,mt8173-uart",
301				     "mediatek,mt6577-uart";
302			reg = <0 0x11002000 0 0x400>;
303			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
304			clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
305			clock-names = "baud", "bus";
306			status = "disabled";
307		};
308
309		uart1: serial@11003000 {
310			compatible = "mediatek,mt8173-uart",
311				     "mediatek,mt6577-uart";
312			reg = <0 0x11003000 0 0x400>;
313			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
314			clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
315			clock-names = "baud", "bus";
316			status = "disabled";
317		};
318
319		uart2: serial@11004000 {
320			compatible = "mediatek,mt8173-uart",
321				     "mediatek,mt6577-uart";
322			reg = <0 0x11004000 0 0x400>;
323			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
324			clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
325			clock-names = "baud", "bus";
326			status = "disabled";
327		};
328
329		uart3: serial@11005000 {
330			compatible = "mediatek,mt8173-uart",
331				     "mediatek,mt6577-uart";
332			reg = <0 0x11005000 0 0x400>;
333			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
334			clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
335			clock-names = "baud", "bus";
336			status = "disabled";
337		};
338
339		i2c0: i2c@11007000 {
340			compatible = "mediatek,mt8173-i2c";
341			reg = <0 0x11007000 0 0x70>,
342			      <0 0x11000100 0 0x80>;
343			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
344			clock-div = <16>;
345			clocks = <&pericfg CLK_PERI_I2C0>,
346				 <&pericfg CLK_PERI_AP_DMA>;
347			clock-names = "main", "dma";
348			pinctrl-names = "default";
349			pinctrl-0 = <&i2c0_pins_a>;
350			#address-cells = <1>;
351			#size-cells = <0>;
352			status = "disabled";
353		};
354
355		i2c1: i2c@11008000 {
356			compatible = "mediatek,mt8173-i2c";
357			reg = <0 0x11008000 0 0x70>,
358			      <0 0x11000180 0 0x80>;
359			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
360			clock-div = <16>;
361			clocks = <&pericfg CLK_PERI_I2C1>,
362				 <&pericfg CLK_PERI_AP_DMA>;
363			clock-names = "main", "dma";
364			pinctrl-names = "default";
365			pinctrl-0 = <&i2c1_pins_a>;
366			#address-cells = <1>;
367			#size-cells = <0>;
368			status = "disabled";
369		};
370
371		i2c2: i2c@11009000 {
372			compatible = "mediatek,mt8173-i2c";
373			reg = <0 0x11009000 0 0x70>,
374			      <0 0x11000200 0 0x80>;
375			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
376			clock-div = <16>;
377			clocks = <&pericfg CLK_PERI_I2C2>,
378				 <&pericfg CLK_PERI_AP_DMA>;
379			clock-names = "main", "dma";
380			pinctrl-names = "default";
381			pinctrl-0 = <&i2c2_pins_a>;
382			#address-cells = <1>;
383			#size-cells = <0>;
384			status = "disabled";
385		};
386
387		spi: spi@1100a000 {
388			compatible = "mediatek,mt8173-spi";
389			#address-cells = <1>;
390			#size-cells = <0>;
391			reg = <0 0x1100a000 0 0x1000>;
392			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
393			clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
394				 <&topckgen CLK_TOP_SPI_SEL>,
395				 <&pericfg CLK_PERI_SPI0>;
396			clock-names = "parent-clk", "sel-clk", "spi-clk";
397			status = "disabled";
398		};
399
400		nor_flash: spi@1100d000 {
401			compatible = "mediatek,mt8173-nor";
402			reg = <0 0x1100d000 0 0xe0>;
403			clocks = <&pericfg CLK_PERI_SPI>,
404				 <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
405			clock-names = "spi", "sf";
406			#address-cells = <1>;
407			#size-cells = <0>;
408			status = "disabled";
409		};
410
411		i2c3: i2c@11010000 {
412			compatible = "mediatek,mt8173-i2c";
413			reg = <0 0x11010000 0 0x70>,
414			      <0 0x11000280 0 0x80>;
415			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
416			clock-div = <16>;
417			clocks = <&pericfg CLK_PERI_I2C3>,
418				 <&pericfg CLK_PERI_AP_DMA>;
419			clock-names = "main", "dma";
420			pinctrl-names = "default";
421			pinctrl-0 = <&i2c3_pins_a>;
422			#address-cells = <1>;
423			#size-cells = <0>;
424			status = "disabled";
425		};
426
427		i2c4: i2c@11011000 {
428			compatible = "mediatek,mt8173-i2c";
429			reg = <0 0x11011000 0 0x70>,
430			      <0 0x11000300 0 0x80>;
431			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
432			clock-div = <16>;
433			clocks = <&pericfg CLK_PERI_I2C4>,
434				 <&pericfg CLK_PERI_AP_DMA>;
435			clock-names = "main", "dma";
436			pinctrl-names = "default";
437			pinctrl-0 = <&i2c4_pins_a>;
438			#address-cells = <1>;
439			#size-cells = <0>;
440			status = "disabled";
441		};
442
443		i2c6: i2c@11013000 {
444			compatible = "mediatek,mt8173-i2c";
445			reg = <0 0x11013000 0 0x70>,
446			      <0 0x11000080 0 0x80>;
447			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
448			clock-div = <16>;
449			clocks = <&pericfg CLK_PERI_I2C6>,
450				 <&pericfg CLK_PERI_AP_DMA>;
451			clock-names = "main", "dma";
452			pinctrl-names = "default";
453			pinctrl-0 = <&i2c6_pins_a>;
454			#address-cells = <1>;
455			#size-cells = <0>;
456			status = "disabled";
457		};
458
459		afe: audio-controller@11220000  {
460			compatible = "mediatek,mt8173-afe-pcm";
461			reg = <0 0x11220000 0 0x1000>;
462			interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
463			power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
464			clocks = <&infracfg CLK_INFRA_AUDIO>,
465				 <&topckgen CLK_TOP_AUDIO_SEL>,
466				 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
467				 <&topckgen CLK_TOP_APLL1_DIV0>,
468				 <&topckgen CLK_TOP_APLL2_DIV0>,
469				 <&topckgen CLK_TOP_I2S0_M_SEL>,
470				 <&topckgen CLK_TOP_I2S1_M_SEL>,
471				 <&topckgen CLK_TOP_I2S2_M_SEL>,
472				 <&topckgen CLK_TOP_I2S3_M_SEL>,
473				 <&topckgen CLK_TOP_I2S3_B_SEL>;
474			clock-names = "infra_sys_audio_clk",
475				      "top_pdn_audio",
476				      "top_pdn_aud_intbus",
477				      "bck0",
478				      "bck1",
479				      "i2s0_m",
480				      "i2s1_m",
481				      "i2s2_m",
482				      "i2s3_m",
483				      "i2s3_b";
484			assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
485					  <&topckgen CLK_TOP_AUD_2_SEL>;
486			assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
487						 <&topckgen CLK_TOP_APLL2>;
488		};
489
490		mmc0: mmc@11230000 {
491			compatible = "mediatek,mt8173-mmc",
492				     "mediatek,mt8135-mmc";
493			reg = <0 0x11230000 0 0x1000>;
494			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
495			clocks = <&pericfg CLK_PERI_MSDC30_0>,
496				 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
497			clock-names = "source", "hclk";
498			status = "disabled";
499		};
500
501		mmc1: mmc@11240000 {
502			compatible = "mediatek,mt8173-mmc",
503				     "mediatek,mt8135-mmc";
504			reg = <0 0x11240000 0 0x1000>;
505			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
506			clocks = <&pericfg CLK_PERI_MSDC30_1>,
507				 <&topckgen CLK_TOP_AXI_SEL>;
508			clock-names = "source", "hclk";
509			status = "disabled";
510		};
511
512		mmc2: mmc@11250000 {
513			compatible = "mediatek,mt8173-mmc",
514				     "mediatek,mt8135-mmc";
515			reg = <0 0x11250000 0 0x1000>;
516			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
517			clocks = <&pericfg CLK_PERI_MSDC30_2>,
518				 <&topckgen CLK_TOP_AXI_SEL>;
519			clock-names = "source", "hclk";
520			status = "disabled";
521		};
522
523		mmc3: mmc@11260000 {
524			compatible = "mediatek,mt8173-mmc",
525				     "mediatek,mt8135-mmc";
526			reg = <0 0x11260000 0 0x1000>;
527			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
528			clocks = <&pericfg CLK_PERI_MSDC30_3>,
529				 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
530			clock-names = "source", "hclk";
531			status = "disabled";
532		};
533
534		usb30: usb@11270000 {
535			compatible = "mediatek,mt8173-xhci";
536			reg = <0 0x11270000 0 0x1000>,
537			      <0 0x11280700 0 0x0100>;
538			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
539			power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
540			clocks = <&topckgen CLK_TOP_USB30_SEL>,
541				 <&pericfg CLK_PERI_USB0>,
542				 <&pericfg CLK_PERI_USB1>;
543			clock-names = "sys_ck",
544				      "wakeup_deb_p0",
545				      "wakeup_deb_p1";
546			phys = <&phy_port0 PHY_TYPE_USB3>,
547			       <&phy_port1 PHY_TYPE_USB2>;
548			mediatek,syscon-wakeup = <&pericfg>;
549			status = "okay";
550		};
551
552		u3phy: usb-phy@11290000 {
553			compatible = "mediatek,mt8173-u3phy";
554			reg = <0 0x11290000 0 0x800>;
555			clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
556			clock-names = "u3phya_ref";
557			#address-cells = <2>;
558			#size-cells = <2>;
559			ranges;
560			status = "okay";
561
562			phy_port0: port@11290800 {
563				reg = <0 0x11290800 0 0x800>;
564				#phy-cells = <1>;
565				status = "okay";
566			};
567
568			phy_port1: port@11291000 {
569				reg = <0 0x11291000 0 0x800>;
570				#phy-cells = <1>;
571				status = "okay";
572			};
573		};
574
575		mmsys: clock-controller@14000000 {
576			compatible = "mediatek,mt8173-mmsys", "syscon";
577			reg = <0 0x14000000 0 0x1000>;
578			#clock-cells = <1>;
579		};
580
581		pwm0: pwm@1401e000 {
582			compatible = "mediatek,mt8173-disp-pwm",
583				     "mediatek,mt6595-disp-pwm";
584			reg = <0 0x1401e000 0 0x1000>;
585			#pwm-cells = <2>;
586			clocks = <&mmsys CLK_MM_DISP_PWM026M>,
587				 <&mmsys CLK_MM_DISP_PWM0MM>;
588			clock-names = "main", "mm";
589			status = "disabled";
590		};
591
592		pwm1: pwm@1401f000 {
593			compatible = "mediatek,mt8173-disp-pwm",
594				     "mediatek,mt6595-disp-pwm";
595			reg = <0 0x1401f000 0 0x1000>;
596			#pwm-cells = <2>;
597			clocks = <&mmsys CLK_MM_DISP_PWM126M>,
598				 <&mmsys CLK_MM_DISP_PWM1MM>;
599			clock-names = "main", "mm";
600			status = "disabled";
601		};
602
603		imgsys: clock-controller@15000000 {
604			compatible = "mediatek,mt8173-imgsys", "syscon";
605			reg = <0 0x15000000 0 0x1000>;
606			#clock-cells = <1>;
607		};
608
609		vdecsys: clock-controller@16000000 {
610			compatible = "mediatek,mt8173-vdecsys", "syscon";
611			reg = <0 0x16000000 0 0x1000>;
612			#clock-cells = <1>;
613		};
614
615		vencsys: clock-controller@18000000 {
616			compatible = "mediatek,mt8173-vencsys", "syscon";
617			reg = <0 0x18000000 0 0x1000>;
618			#clock-cells = <1>;
619		};
620
621		vencltsys: clock-controller@19000000 {
622			compatible = "mediatek,mt8173-vencltsys", "syscon";
623			reg = <0 0x19000000 0 0x1000>;
624			#clock-cells = <1>;
625		};
626	};
627};
628
629