1/* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Eddie Huang <eddie.huang@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/clock/mt8173-clk.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/memory/mt8173-larb-port.h> 18#include <dt-bindings/phy/phy.h> 19#include <dt-bindings/power/mt8173-power.h> 20#include <dt-bindings/reset/mt8173-resets.h> 21#include "mt8173-pinfunc.h" 22 23/ { 24 compatible = "mediatek,mt8173"; 25 interrupt-parent = <&sysirq>; 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 aliases { 30 ovl0 = &ovl0; 31 ovl1 = &ovl1; 32 rdma0 = &rdma0; 33 rdma1 = &rdma1; 34 rdma2 = &rdma2; 35 wdma0 = &wdma0; 36 wdma1 = &wdma1; 37 color0 = &color0; 38 color1 = &color1; 39 split0 = &split0; 40 split1 = &split1; 41 dpi0 = &dpi0; 42 dsi0 = &dsi0; 43 dsi1 = &dsi1; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 cpu-map { 51 cluster0 { 52 core0 { 53 cpu = <&cpu0>; 54 }; 55 core1 { 56 cpu = <&cpu1>; 57 }; 58 }; 59 60 cluster1 { 61 core0 { 62 cpu = <&cpu2>; 63 }; 64 core1 { 65 cpu = <&cpu3>; 66 }; 67 }; 68 }; 69 70 cpu0: cpu@0 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53"; 73 reg = <0x000>; 74 enable-method = "psci"; 75 cpu-idle-states = <&CPU_SLEEP_0>; 76 }; 77 78 cpu1: cpu@1 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a53"; 81 reg = <0x001>; 82 enable-method = "psci"; 83 cpu-idle-states = <&CPU_SLEEP_0>; 84 }; 85 86 cpu2: cpu@100 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a57"; 89 reg = <0x100>; 90 enable-method = "psci"; 91 cpu-idle-states = <&CPU_SLEEP_0>; 92 }; 93 94 cpu3: cpu@101 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a57"; 97 reg = <0x101>; 98 enable-method = "psci"; 99 cpu-idle-states = <&CPU_SLEEP_0>; 100 }; 101 102 idle-states { 103 entry-method = "psci"; 104 105 CPU_SLEEP_0: cpu-sleep-0 { 106 compatible = "arm,idle-state"; 107 local-timer-stop; 108 entry-latency-us = <639>; 109 exit-latency-us = <680>; 110 min-residency-us = <1088>; 111 arm,psci-suspend-param = <0x0010000>; 112 }; 113 }; 114 }; 115 116 psci { 117 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 118 method = "smc"; 119 cpu_suspend = <0x84000001>; 120 cpu_off = <0x84000002>; 121 cpu_on = <0x84000003>; 122 }; 123 124 clk26m: oscillator@0 { 125 compatible = "fixed-clock"; 126 #clock-cells = <0>; 127 clock-frequency = <26000000>; 128 clock-output-names = "clk26m"; 129 }; 130 131 clk32k: oscillator@1 { 132 compatible = "fixed-clock"; 133 #clock-cells = <0>; 134 clock-frequency = <32000>; 135 clock-output-names = "clk32k"; 136 }; 137 138 cpum_ck: oscillator@2 { 139 compatible = "fixed-clock"; 140 #clock-cells = <0>; 141 clock-frequency = <0>; 142 clock-output-names = "cpum_ck"; 143 }; 144 145 thermal-zones { 146 cpu_thermal: cpu_thermal { 147 polling-delay-passive = <1000>; /* milliseconds */ 148 polling-delay = <1000>; /* milliseconds */ 149 150 thermal-sensors = <&thermal>; 151 sustainable-power = <1500>; /* milliwatts */ 152 153 trips { 154 threshold: trip-point@0 { 155 temperature = <68000>; 156 hysteresis = <2000>; 157 type = "passive"; 158 }; 159 160 target: trip-point@1 { 161 temperature = <85000>; 162 hysteresis = <2000>; 163 type = "passive"; 164 }; 165 166 cpu_crit: cpu_crit@0 { 167 temperature = <115000>; 168 hysteresis = <2000>; 169 type = "critical"; 170 }; 171 }; 172 173 cooling-maps { 174 map@0 { 175 trip = <&target>; 176 cooling-device = <&cpu0 0 0>; 177 contribution = <1024>; 178 }; 179 map@1 { 180 trip = <&target>; 181 cooling-device = <&cpu2 0 0>; 182 contribution = <2048>; 183 }; 184 }; 185 }; 186 }; 187 188 timer { 189 compatible = "arm,armv8-timer"; 190 interrupt-parent = <&gic>; 191 interrupts = <GIC_PPI 13 192 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 193 <GIC_PPI 14 194 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 195 <GIC_PPI 11 196 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 197 <GIC_PPI 10 198 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 199 }; 200 201 soc { 202 #address-cells = <2>; 203 #size-cells = <2>; 204 compatible = "simple-bus"; 205 ranges; 206 207 topckgen: clock-controller@10000000 { 208 compatible = "mediatek,mt8173-topckgen"; 209 reg = <0 0x10000000 0 0x1000>; 210 #clock-cells = <1>; 211 }; 212 213 infracfg: power-controller@10001000 { 214 compatible = "mediatek,mt8173-infracfg", "syscon"; 215 reg = <0 0x10001000 0 0x1000>; 216 #clock-cells = <1>; 217 #reset-cells = <1>; 218 }; 219 220 pericfg: power-controller@10003000 { 221 compatible = "mediatek,mt8173-pericfg", "syscon"; 222 reg = <0 0x10003000 0 0x1000>; 223 #clock-cells = <1>; 224 #reset-cells = <1>; 225 }; 226 227 syscfg_pctl_a: syscfg_pctl_a@10005000 { 228 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 229 reg = <0 0x10005000 0 0x1000>; 230 }; 231 232 pio: pinctrl@0x10005000 { 233 compatible = "mediatek,mt8173-pinctrl"; 234 reg = <0 0x1000b000 0 0x1000>; 235 mediatek,pctl-regmap = <&syscfg_pctl_a>; 236 pins-are-numbered; 237 gpio-controller; 238 #gpio-cells = <2>; 239 interrupt-controller; 240 #interrupt-cells = <2>; 241 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 242 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 244 245 i2c0_pins_a: i2c0 { 246 pins1 { 247 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 248 <MT8173_PIN_46_SCL0__FUNC_SCL0>; 249 bias-disable; 250 }; 251 }; 252 253 i2c1_pins_a: i2c1 { 254 pins1 { 255 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 256 <MT8173_PIN_126_SCL1__FUNC_SCL1>; 257 bias-disable; 258 }; 259 }; 260 261 i2c2_pins_a: i2c2 { 262 pins1 { 263 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 264 <MT8173_PIN_44_SCL2__FUNC_SCL2>; 265 bias-disable; 266 }; 267 }; 268 269 i2c3_pins_a: i2c3 { 270 pins1 { 271 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 272 <MT8173_PIN_107_SCL3__FUNC_SCL3>; 273 bias-disable; 274 }; 275 }; 276 277 i2c4_pins_a: i2c4 { 278 pins1 { 279 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 280 <MT8173_PIN_134_SCL4__FUNC_SCL4>; 281 bias-disable; 282 }; 283 }; 284 285 i2c6_pins_a: i2c6 { 286 pins1 { 287 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 288 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 289 bias-disable; 290 }; 291 }; 292 }; 293 294 scpsys: scpsys@10006000 { 295 compatible = "mediatek,mt8173-scpsys"; 296 #power-domain-cells = <1>; 297 reg = <0 0x10006000 0 0x1000>; 298 clocks = <&clk26m>, 299 <&topckgen CLK_TOP_MM_SEL>, 300 <&topckgen CLK_TOP_VENC_SEL>, 301 <&topckgen CLK_TOP_VENC_LT_SEL>; 302 clock-names = "mfg", "mm", "venc", "venc_lt"; 303 infracfg = <&infracfg>; 304 }; 305 306 watchdog: watchdog@10007000 { 307 compatible = "mediatek,mt8173-wdt", 308 "mediatek,mt6589-wdt"; 309 reg = <0 0x10007000 0 0x100>; 310 }; 311 312 timer: timer@10008000 { 313 compatible = "mediatek,mt8173-timer", 314 "mediatek,mt6577-timer"; 315 reg = <0 0x10008000 0 0x1000>; 316 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 317 clocks = <&infracfg CLK_INFRA_CLK_13M>, 318 <&topckgen CLK_TOP_RTC_SEL>; 319 }; 320 321 pwrap: pwrap@1000d000 { 322 compatible = "mediatek,mt8173-pwrap"; 323 reg = <0 0x1000d000 0 0x1000>; 324 reg-names = "pwrap"; 325 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 326 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 327 reset-names = "pwrap"; 328 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 329 clock-names = "spi", "wrap"; 330 }; 331 332 sysirq: intpol-controller@10200620 { 333 compatible = "mediatek,mt8173-sysirq", 334 "mediatek,mt6577-sysirq"; 335 interrupt-controller; 336 #interrupt-cells = <3>; 337 interrupt-parent = <&gic>; 338 reg = <0 0x10200620 0 0x20>; 339 }; 340 341 iommu: iommu@10205000 { 342 compatible = "mediatek,mt8173-m4u"; 343 reg = <0 0x10205000 0 0x1000>; 344 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 345 clocks = <&infracfg CLK_INFRA_M4U>; 346 clock-names = "bclk"; 347 mediatek,larbs = <&larb0 &larb1 &larb2 348 &larb3 &larb4 &larb5>; 349 #iommu-cells = <1>; 350 }; 351 352 efuse: efuse@10206000 { 353 compatible = "mediatek,mt8173-efuse"; 354 reg = <0 0x10206000 0 0x1000>; 355 }; 356 357 apmixedsys: clock-controller@10209000 { 358 compatible = "mediatek,mt8173-apmixedsys"; 359 reg = <0 0x10209000 0 0x1000>; 360 #clock-cells = <1>; 361 }; 362 363 mipi_tx0: mipi-dphy@10215000 { 364 compatible = "mediatek,mt8173-mipi-tx"; 365 reg = <0 0x10215000 0 0x1000>; 366 clocks = <&clk26m>; 367 clock-output-names = "mipi_tx0_pll"; 368 #clock-cells = <0>; 369 #phy-cells = <0>; 370 status = "disabled"; 371 }; 372 373 mipi_tx1: mipi-dphy@10216000 { 374 compatible = "mediatek,mt8173-mipi-tx"; 375 reg = <0 0x10216000 0 0x1000>; 376 clocks = <&clk26m>; 377 clock-output-names = "mipi_tx1_pll"; 378 #clock-cells = <0>; 379 #phy-cells = <0>; 380 status = "disabled"; 381 }; 382 383 gic: interrupt-controller@10220000 { 384 compatible = "arm,gic-400"; 385 #interrupt-cells = <3>; 386 interrupt-parent = <&gic>; 387 interrupt-controller; 388 reg = <0 0x10221000 0 0x1000>, 389 <0 0x10222000 0 0x2000>, 390 <0 0x10224000 0 0x2000>, 391 <0 0x10226000 0 0x2000>; 392 interrupts = <GIC_PPI 9 393 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 394 }; 395 396 auxadc: auxadc@11001000 { 397 compatible = "mediatek,mt8173-auxadc"; 398 reg = <0 0x11001000 0 0x1000>; 399 }; 400 401 uart0: serial@11002000 { 402 compatible = "mediatek,mt8173-uart", 403 "mediatek,mt6577-uart"; 404 reg = <0 0x11002000 0 0x400>; 405 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 406 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 407 clock-names = "baud", "bus"; 408 status = "disabled"; 409 }; 410 411 uart1: serial@11003000 { 412 compatible = "mediatek,mt8173-uart", 413 "mediatek,mt6577-uart"; 414 reg = <0 0x11003000 0 0x400>; 415 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 416 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 417 clock-names = "baud", "bus"; 418 status = "disabled"; 419 }; 420 421 uart2: serial@11004000 { 422 compatible = "mediatek,mt8173-uart", 423 "mediatek,mt6577-uart"; 424 reg = <0 0x11004000 0 0x400>; 425 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 426 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 427 clock-names = "baud", "bus"; 428 status = "disabled"; 429 }; 430 431 uart3: serial@11005000 { 432 compatible = "mediatek,mt8173-uart", 433 "mediatek,mt6577-uart"; 434 reg = <0 0x11005000 0 0x400>; 435 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 436 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 437 clock-names = "baud", "bus"; 438 status = "disabled"; 439 }; 440 441 i2c0: i2c@11007000 { 442 compatible = "mediatek,mt8173-i2c"; 443 reg = <0 0x11007000 0 0x70>, 444 <0 0x11000100 0 0x80>; 445 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 446 clock-div = <16>; 447 clocks = <&pericfg CLK_PERI_I2C0>, 448 <&pericfg CLK_PERI_AP_DMA>; 449 clock-names = "main", "dma"; 450 pinctrl-names = "default"; 451 pinctrl-0 = <&i2c0_pins_a>; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 status = "disabled"; 455 }; 456 457 i2c1: i2c@11008000 { 458 compatible = "mediatek,mt8173-i2c"; 459 reg = <0 0x11008000 0 0x70>, 460 <0 0x11000180 0 0x80>; 461 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 462 clock-div = <16>; 463 clocks = <&pericfg CLK_PERI_I2C1>, 464 <&pericfg CLK_PERI_AP_DMA>; 465 clock-names = "main", "dma"; 466 pinctrl-names = "default"; 467 pinctrl-0 = <&i2c1_pins_a>; 468 #address-cells = <1>; 469 #size-cells = <0>; 470 status = "disabled"; 471 }; 472 473 i2c2: i2c@11009000 { 474 compatible = "mediatek,mt8173-i2c"; 475 reg = <0 0x11009000 0 0x70>, 476 <0 0x11000200 0 0x80>; 477 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 478 clock-div = <16>; 479 clocks = <&pericfg CLK_PERI_I2C2>, 480 <&pericfg CLK_PERI_AP_DMA>; 481 clock-names = "main", "dma"; 482 pinctrl-names = "default"; 483 pinctrl-0 = <&i2c2_pins_a>; 484 #address-cells = <1>; 485 #size-cells = <0>; 486 status = "disabled"; 487 }; 488 489 spi: spi@1100a000 { 490 compatible = "mediatek,mt8173-spi"; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 reg = <0 0x1100a000 0 0x1000>; 494 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 495 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 496 <&topckgen CLK_TOP_SPI_SEL>, 497 <&pericfg CLK_PERI_SPI0>; 498 clock-names = "parent-clk", "sel-clk", "spi-clk"; 499 status = "disabled"; 500 }; 501 502 thermal: thermal@1100b000 { 503 #thermal-sensor-cells = <0>; 504 compatible = "mediatek,mt8173-thermal"; 505 reg = <0 0x1100b000 0 0x1000>; 506 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 507 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 508 clock-names = "therm", "auxadc"; 509 resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 510 mediatek,auxadc = <&auxadc>; 511 mediatek,apmixedsys = <&apmixedsys>; 512 }; 513 514 nor_flash: spi@1100d000 { 515 compatible = "mediatek,mt8173-nor"; 516 reg = <0 0x1100d000 0 0xe0>; 517 clocks = <&pericfg CLK_PERI_SPI>, 518 <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 519 clock-names = "spi", "sf"; 520 #address-cells = <1>; 521 #size-cells = <0>; 522 status = "disabled"; 523 }; 524 525 i2c3: i2c@11010000 { 526 compatible = "mediatek,mt8173-i2c"; 527 reg = <0 0x11010000 0 0x70>, 528 <0 0x11000280 0 0x80>; 529 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 530 clock-div = <16>; 531 clocks = <&pericfg CLK_PERI_I2C3>, 532 <&pericfg CLK_PERI_AP_DMA>; 533 clock-names = "main", "dma"; 534 pinctrl-names = "default"; 535 pinctrl-0 = <&i2c3_pins_a>; 536 #address-cells = <1>; 537 #size-cells = <0>; 538 status = "disabled"; 539 }; 540 541 i2c4: i2c@11011000 { 542 compatible = "mediatek,mt8173-i2c"; 543 reg = <0 0x11011000 0 0x70>, 544 <0 0x11000300 0 0x80>; 545 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 546 clock-div = <16>; 547 clocks = <&pericfg CLK_PERI_I2C4>, 548 <&pericfg CLK_PERI_AP_DMA>; 549 clock-names = "main", "dma"; 550 pinctrl-names = "default"; 551 pinctrl-0 = <&i2c4_pins_a>; 552 #address-cells = <1>; 553 #size-cells = <0>; 554 status = "disabled"; 555 }; 556 557 i2c6: i2c@11013000 { 558 compatible = "mediatek,mt8173-i2c"; 559 reg = <0 0x11013000 0 0x70>, 560 <0 0x11000080 0 0x80>; 561 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 562 clock-div = <16>; 563 clocks = <&pericfg CLK_PERI_I2C6>, 564 <&pericfg CLK_PERI_AP_DMA>; 565 clock-names = "main", "dma"; 566 pinctrl-names = "default"; 567 pinctrl-0 = <&i2c6_pins_a>; 568 #address-cells = <1>; 569 #size-cells = <0>; 570 status = "disabled"; 571 }; 572 573 afe: audio-controller@11220000 { 574 compatible = "mediatek,mt8173-afe-pcm"; 575 reg = <0 0x11220000 0 0x1000>; 576 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 577 power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; 578 clocks = <&infracfg CLK_INFRA_AUDIO>, 579 <&topckgen CLK_TOP_AUDIO_SEL>, 580 <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 581 <&topckgen CLK_TOP_APLL1_DIV0>, 582 <&topckgen CLK_TOP_APLL2_DIV0>, 583 <&topckgen CLK_TOP_I2S0_M_SEL>, 584 <&topckgen CLK_TOP_I2S1_M_SEL>, 585 <&topckgen CLK_TOP_I2S2_M_SEL>, 586 <&topckgen CLK_TOP_I2S3_M_SEL>, 587 <&topckgen CLK_TOP_I2S3_B_SEL>; 588 clock-names = "infra_sys_audio_clk", 589 "top_pdn_audio", 590 "top_pdn_aud_intbus", 591 "bck0", 592 "bck1", 593 "i2s0_m", 594 "i2s1_m", 595 "i2s2_m", 596 "i2s3_m", 597 "i2s3_b"; 598 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 599 <&topckgen CLK_TOP_AUD_2_SEL>; 600 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 601 <&topckgen CLK_TOP_APLL2>; 602 }; 603 604 mmc0: mmc@11230000 { 605 compatible = "mediatek,mt8173-mmc", 606 "mediatek,mt8135-mmc"; 607 reg = <0 0x11230000 0 0x1000>; 608 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 609 clocks = <&pericfg CLK_PERI_MSDC30_0>, 610 <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 611 clock-names = "source", "hclk"; 612 status = "disabled"; 613 }; 614 615 mmc1: mmc@11240000 { 616 compatible = "mediatek,mt8173-mmc", 617 "mediatek,mt8135-mmc"; 618 reg = <0 0x11240000 0 0x1000>; 619 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 620 clocks = <&pericfg CLK_PERI_MSDC30_1>, 621 <&topckgen CLK_TOP_AXI_SEL>; 622 clock-names = "source", "hclk"; 623 status = "disabled"; 624 }; 625 626 mmc2: mmc@11250000 { 627 compatible = "mediatek,mt8173-mmc", 628 "mediatek,mt8135-mmc"; 629 reg = <0 0x11250000 0 0x1000>; 630 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 631 clocks = <&pericfg CLK_PERI_MSDC30_2>, 632 <&topckgen CLK_TOP_AXI_SEL>; 633 clock-names = "source", "hclk"; 634 status = "disabled"; 635 }; 636 637 mmc3: mmc@11260000 { 638 compatible = "mediatek,mt8173-mmc", 639 "mediatek,mt8135-mmc"; 640 reg = <0 0x11260000 0 0x1000>; 641 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 642 clocks = <&pericfg CLK_PERI_MSDC30_3>, 643 <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 644 clock-names = "source", "hclk"; 645 status = "disabled"; 646 }; 647 648 usb30: usb@11270000 { 649 compatible = "mediatek,mt8173-xhci"; 650 reg = <0 0x11270000 0 0x1000>, 651 <0 0x11280700 0 0x0100>; 652 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 653 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 654 clocks = <&topckgen CLK_TOP_USB30_SEL>, 655 <&pericfg CLK_PERI_USB0>, 656 <&pericfg CLK_PERI_USB1>; 657 clock-names = "sys_ck", 658 "wakeup_deb_p0", 659 "wakeup_deb_p1"; 660 phys = <&phy_port0 PHY_TYPE_USB3>, 661 <&phy_port1 PHY_TYPE_USB2>; 662 mediatek,syscon-wakeup = <&pericfg>; 663 status = "okay"; 664 }; 665 666 u3phy: usb-phy@11290000 { 667 compatible = "mediatek,mt8173-u3phy"; 668 reg = <0 0x11290000 0 0x800>; 669 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 670 clock-names = "u3phya_ref"; 671 #address-cells = <2>; 672 #size-cells = <2>; 673 ranges; 674 status = "okay"; 675 676 phy_port0: port@11290800 { 677 reg = <0 0x11290800 0 0x800>; 678 #phy-cells = <1>; 679 status = "okay"; 680 }; 681 682 phy_port1: port@11291000 { 683 reg = <0 0x11291000 0 0x800>; 684 #phy-cells = <1>; 685 status = "okay"; 686 }; 687 }; 688 689 mmsys: clock-controller@14000000 { 690 compatible = "mediatek,mt8173-mmsys", "syscon"; 691 reg = <0 0x14000000 0 0x1000>; 692 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 693 #clock-cells = <1>; 694 }; 695 696 ovl0: ovl@1400c000 { 697 compatible = "mediatek,mt8173-disp-ovl"; 698 reg = <0 0x1400c000 0 0x1000>; 699 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 700 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 701 clocks = <&mmsys CLK_MM_DISP_OVL0>; 702 iommus = <&iommu M4U_PORT_DISP_OVL0>; 703 mediatek,larb = <&larb0>; 704 }; 705 706 ovl1: ovl@1400d000 { 707 compatible = "mediatek,mt8173-disp-ovl"; 708 reg = <0 0x1400d000 0 0x1000>; 709 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; 710 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 711 clocks = <&mmsys CLK_MM_DISP_OVL1>; 712 iommus = <&iommu M4U_PORT_DISP_OVL1>; 713 mediatek,larb = <&larb4>; 714 }; 715 716 rdma0: rdma@1400e000 { 717 compatible = "mediatek,mt8173-disp-rdma"; 718 reg = <0 0x1400e000 0 0x1000>; 719 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 720 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 721 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 722 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 723 mediatek,larb = <&larb0>; 724 }; 725 726 rdma1: rdma@1400f000 { 727 compatible = "mediatek,mt8173-disp-rdma"; 728 reg = <0 0x1400f000 0 0x1000>; 729 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; 730 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 731 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 732 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 733 mediatek,larb = <&larb4>; 734 }; 735 736 rdma2: rdma@14010000 { 737 compatible = "mediatek,mt8173-disp-rdma"; 738 reg = <0 0x14010000 0 0x1000>; 739 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; 740 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 741 clocks = <&mmsys CLK_MM_DISP_RDMA2>; 742 iommus = <&iommu M4U_PORT_DISP_RDMA2>; 743 mediatek,larb = <&larb4>; 744 }; 745 746 wdma0: wdma@14011000 { 747 compatible = "mediatek,mt8173-disp-wdma"; 748 reg = <0 0x14011000 0 0x1000>; 749 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 750 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 751 clocks = <&mmsys CLK_MM_DISP_WDMA0>; 752 iommus = <&iommu M4U_PORT_DISP_WDMA0>; 753 mediatek,larb = <&larb0>; 754 }; 755 756 wdma1: wdma@14012000 { 757 compatible = "mediatek,mt8173-disp-wdma"; 758 reg = <0 0x14012000 0 0x1000>; 759 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; 760 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 761 clocks = <&mmsys CLK_MM_DISP_WDMA1>; 762 iommus = <&iommu M4U_PORT_DISP_WDMA1>; 763 mediatek,larb = <&larb4>; 764 }; 765 766 color0: color@14013000 { 767 compatible = "mediatek,mt8173-disp-color"; 768 reg = <0 0x14013000 0 0x1000>; 769 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; 770 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 771 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 772 }; 773 774 color1: color@14014000 { 775 compatible = "mediatek,mt8173-disp-color"; 776 reg = <0 0x14014000 0 0x1000>; 777 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 778 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 779 clocks = <&mmsys CLK_MM_DISP_COLOR1>; 780 }; 781 782 aal@14015000 { 783 compatible = "mediatek,mt8173-disp-aal"; 784 reg = <0 0x14015000 0 0x1000>; 785 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 786 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 787 clocks = <&mmsys CLK_MM_DISP_AAL>; 788 }; 789 790 gamma@14016000 { 791 compatible = "mediatek,mt8173-disp-gamma"; 792 reg = <0 0x14016000 0 0x1000>; 793 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 794 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 795 clocks = <&mmsys CLK_MM_DISP_GAMMA>; 796 }; 797 798 merge@14017000 { 799 compatible = "mediatek,mt8173-disp-merge"; 800 reg = <0 0x14017000 0 0x1000>; 801 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 802 clocks = <&mmsys CLK_MM_DISP_MERGE>; 803 }; 804 805 split0: split@14018000 { 806 compatible = "mediatek,mt8173-disp-split"; 807 reg = <0 0x14018000 0 0x1000>; 808 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 809 clocks = <&mmsys CLK_MM_DISP_SPLIT0>; 810 }; 811 812 split1: split@14019000 { 813 compatible = "mediatek,mt8173-disp-split"; 814 reg = <0 0x14019000 0 0x1000>; 815 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 816 clocks = <&mmsys CLK_MM_DISP_SPLIT1>; 817 }; 818 819 ufoe@1401a000 { 820 compatible = "mediatek,mt8173-disp-ufoe"; 821 reg = <0 0x1401a000 0 0x1000>; 822 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 823 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 824 clocks = <&mmsys CLK_MM_DISP_UFOE>; 825 }; 826 827 dsi0: dsi@1401b000 { 828 compatible = "mediatek,mt8173-dsi"; 829 reg = <0 0x1401b000 0 0x1000>; 830 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 831 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 832 clocks = <&mmsys CLK_MM_DSI0_ENGINE>, 833 <&mmsys CLK_MM_DSI0_DIGITAL>, 834 <&mipi_tx0>; 835 clock-names = "engine", "digital", "hs"; 836 phys = <&mipi_tx0>; 837 phy-names = "dphy"; 838 status = "disabled"; 839 }; 840 841 dsi1: dsi@1401c000 { 842 compatible = "mediatek,mt8173-dsi"; 843 reg = <0 0x1401c000 0 0x1000>; 844 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 845 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 846 clocks = <&mmsys CLK_MM_DSI1_ENGINE>, 847 <&mmsys CLK_MM_DSI1_DIGITAL>, 848 <&mipi_tx1>; 849 clock-names = "engine", "digital", "hs"; 850 phy = <&mipi_tx1>; 851 phy-names = "dphy"; 852 status = "disabled"; 853 }; 854 855 dpi0: dpi@1401d000 { 856 compatible = "mediatek,mt8173-dpi"; 857 reg = <0 0x1401d000 0 0x1000>; 858 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 859 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 860 clocks = <&mmsys CLK_MM_DPI_PIXEL>, 861 <&mmsys CLK_MM_DPI_ENGINE>, 862 <&apmixedsys CLK_APMIXED_TVDPLL>; 863 clock-names = "pixel", "engine", "pll"; 864 status = "disabled"; 865 }; 866 867 pwm0: pwm@1401e000 { 868 compatible = "mediatek,mt8173-disp-pwm", 869 "mediatek,mt6595-disp-pwm"; 870 reg = <0 0x1401e000 0 0x1000>; 871 #pwm-cells = <2>; 872 clocks = <&mmsys CLK_MM_DISP_PWM026M>, 873 <&mmsys CLK_MM_DISP_PWM0MM>; 874 clock-names = "main", "mm"; 875 status = "disabled"; 876 }; 877 878 pwm1: pwm@1401f000 { 879 compatible = "mediatek,mt8173-disp-pwm", 880 "mediatek,mt6595-disp-pwm"; 881 reg = <0 0x1401f000 0 0x1000>; 882 #pwm-cells = <2>; 883 clocks = <&mmsys CLK_MM_DISP_PWM126M>, 884 <&mmsys CLK_MM_DISP_PWM1MM>; 885 clock-names = "main", "mm"; 886 status = "disabled"; 887 }; 888 889 mutex: mutex@14020000 { 890 compatible = "mediatek,mt8173-disp-mutex"; 891 reg = <0 0x14020000 0 0x1000>; 892 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 893 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 894 clocks = <&mmsys CLK_MM_MUTEX_32K>; 895 }; 896 897 larb0: larb@14021000 { 898 compatible = "mediatek,mt8173-smi-larb"; 899 reg = <0 0x14021000 0 0x1000>; 900 mediatek,smi = <&smi_common>; 901 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 902 clocks = <&mmsys CLK_MM_SMI_LARB0>, 903 <&mmsys CLK_MM_SMI_LARB0>; 904 clock-names = "apb", "smi"; 905 }; 906 907 smi_common: smi@14022000 { 908 compatible = "mediatek,mt8173-smi-common"; 909 reg = <0 0x14022000 0 0x1000>; 910 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 911 clocks = <&mmsys CLK_MM_SMI_COMMON>, 912 <&mmsys CLK_MM_SMI_COMMON>; 913 clock-names = "apb", "smi"; 914 }; 915 916 od@14023000 { 917 compatible = "mediatek,mt8173-disp-od"; 918 reg = <0 0x14023000 0 0x1000>; 919 clocks = <&mmsys CLK_MM_DISP_OD>; 920 }; 921 922 larb4: larb@14027000 { 923 compatible = "mediatek,mt8173-smi-larb"; 924 reg = <0 0x14027000 0 0x1000>; 925 mediatek,smi = <&smi_common>; 926 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 927 clocks = <&mmsys CLK_MM_SMI_LARB4>, 928 <&mmsys CLK_MM_SMI_LARB4>; 929 clock-names = "apb", "smi"; 930 }; 931 932 imgsys: clock-controller@15000000 { 933 compatible = "mediatek,mt8173-imgsys", "syscon"; 934 reg = <0 0x15000000 0 0x1000>; 935 #clock-cells = <1>; 936 }; 937 938 larb2: larb@15001000 { 939 compatible = "mediatek,mt8173-smi-larb"; 940 reg = <0 0x15001000 0 0x1000>; 941 mediatek,smi = <&smi_common>; 942 power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>; 943 clocks = <&imgsys CLK_IMG_LARB2_SMI>, 944 <&imgsys CLK_IMG_LARB2_SMI>; 945 clock-names = "apb", "smi"; 946 }; 947 948 vdecsys: clock-controller@16000000 { 949 compatible = "mediatek,mt8173-vdecsys", "syscon"; 950 reg = <0 0x16000000 0 0x1000>; 951 #clock-cells = <1>; 952 }; 953 954 larb1: larb@16010000 { 955 compatible = "mediatek,mt8173-smi-larb"; 956 reg = <0 0x16010000 0 0x1000>; 957 mediatek,smi = <&smi_common>; 958 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 959 clocks = <&vdecsys CLK_VDEC_CKEN>, 960 <&vdecsys CLK_VDEC_LARB_CKEN>; 961 clock-names = "apb", "smi"; 962 }; 963 964 vencsys: clock-controller@18000000 { 965 compatible = "mediatek,mt8173-vencsys", "syscon"; 966 reg = <0 0x18000000 0 0x1000>; 967 #clock-cells = <1>; 968 }; 969 970 larb3: larb@18001000 { 971 compatible = "mediatek,mt8173-smi-larb"; 972 reg = <0 0x18001000 0 0x1000>; 973 mediatek,smi = <&smi_common>; 974 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 975 clocks = <&vencsys CLK_VENC_CKE1>, 976 <&vencsys CLK_VENC_CKE0>; 977 clock-names = "apb", "smi"; 978 }; 979 980 vencltsys: clock-controller@19000000 { 981 compatible = "mediatek,mt8173-vencltsys", "syscon"; 982 reg = <0 0x19000000 0 0x1000>; 983 #clock-cells = <1>; 984 }; 985 986 larb5: larb@19001000 { 987 compatible = "mediatek,mt8173-smi-larb"; 988 reg = <0 0x19001000 0 0x1000>; 989 mediatek,smi = <&smi_common>; 990 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; 991 clocks = <&vencltsys CLK_VENCLT_CKE1>, 992 <&vencltsys CLK_VENCLT_CKE0>; 993 clock-names = "apb", "smi"; 994 }; 995 }; 996}; 997 998