1/* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Eddie Huang <eddie.huang@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/clock/mt8173-clk.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/memory/mt8173-larb-port.h> 18#include <dt-bindings/phy/phy.h> 19#include <dt-bindings/power/mt8173-power.h> 20#include <dt-bindings/reset/mt8173-resets.h> 21#include <dt-bindings/gce/mt8173-gce.h> 22#include <dt-bindings/thermal/thermal.h> 23#include "mt8173-pinfunc.h" 24 25/ { 26 compatible = "mediatek,mt8173"; 27 interrupt-parent = <&sysirq>; 28 #address-cells = <2>; 29 #size-cells = <2>; 30 31 aliases { 32 ovl0 = &ovl0; 33 ovl1 = &ovl1; 34 rdma0 = &rdma0; 35 rdma1 = &rdma1; 36 rdma2 = &rdma2; 37 wdma0 = &wdma0; 38 wdma1 = &wdma1; 39 color0 = &color0; 40 color1 = &color1; 41 split0 = &split0; 42 split1 = &split1; 43 dpi0 = &dpi0; 44 dsi0 = &dsi0; 45 dsi1 = &dsi1; 46 mdp-rdma0 = &mdp_rdma0; 47 mdp-rdma1 = &mdp_rdma1; 48 mdp-rsz0 = &mdp_rsz0; 49 mdp-rsz1 = &mdp_rsz1; 50 mdp-rsz2 = &mdp_rsz2; 51 mdp-wdma0 = &mdp_wdma0; 52 mdp-wrot0 = &mdp_wrot0; 53 mdp-wrot1 = &mdp_wrot1; 54 serial0 = &uart0; 55 serial1 = &uart1; 56 serial2 = &uart2; 57 serial3 = &uart3; 58 }; 59 60 cluster0_opp: opp-table-0 { 61 compatible = "operating-points-v2"; 62 opp-shared; 63 opp-507000000 { 64 opp-hz = /bits/ 64 <507000000>; 65 opp-microvolt = <859000>; 66 }; 67 opp-702000000 { 68 opp-hz = /bits/ 64 <702000000>; 69 opp-microvolt = <908000>; 70 }; 71 opp-1001000000 { 72 opp-hz = /bits/ 64 <1001000000>; 73 opp-microvolt = <983000>; 74 }; 75 opp-1105000000 { 76 opp-hz = /bits/ 64 <1105000000>; 77 opp-microvolt = <1009000>; 78 }; 79 opp-1209000000 { 80 opp-hz = /bits/ 64 <1209000000>; 81 opp-microvolt = <1034000>; 82 }; 83 opp-1300000000 { 84 opp-hz = /bits/ 64 <1300000000>; 85 opp-microvolt = <1057000>; 86 }; 87 opp-1508000000 { 88 opp-hz = /bits/ 64 <1508000000>; 89 opp-microvolt = <1109000>; 90 }; 91 opp-1703000000 { 92 opp-hz = /bits/ 64 <1703000000>; 93 opp-microvolt = <1125000>; 94 }; 95 }; 96 97 cluster1_opp: opp-table-1 { 98 compatible = "operating-points-v2"; 99 opp-shared; 100 opp-507000000 { 101 opp-hz = /bits/ 64 <507000000>; 102 opp-microvolt = <828000>; 103 }; 104 opp-702000000 { 105 opp-hz = /bits/ 64 <702000000>; 106 opp-microvolt = <867000>; 107 }; 108 opp-1001000000 { 109 opp-hz = /bits/ 64 <1001000000>; 110 opp-microvolt = <927000>; 111 }; 112 opp-1209000000 { 113 opp-hz = /bits/ 64 <1209000000>; 114 opp-microvolt = <968000>; 115 }; 116 opp-1404000000 { 117 opp-hz = /bits/ 64 <1404000000>; 118 opp-microvolt = <1007000>; 119 }; 120 opp-1612000000 { 121 opp-hz = /bits/ 64 <1612000000>; 122 opp-microvolt = <1049000>; 123 }; 124 opp-1807000000 { 125 opp-hz = /bits/ 64 <1807000000>; 126 opp-microvolt = <1089000>; 127 }; 128 opp-2106000000 { 129 opp-hz = /bits/ 64 <2106000000>; 130 opp-microvolt = <1125000>; 131 }; 132 }; 133 134 cpus { 135 #address-cells = <1>; 136 #size-cells = <0>; 137 138 cpu-map { 139 cluster0 { 140 core0 { 141 cpu = <&cpu0>; 142 }; 143 core1 { 144 cpu = <&cpu1>; 145 }; 146 }; 147 148 cluster1 { 149 core0 { 150 cpu = <&cpu2>; 151 }; 152 core1 { 153 cpu = <&cpu3>; 154 }; 155 }; 156 }; 157 158 cpu0: cpu@0 { 159 device_type = "cpu"; 160 compatible = "arm,cortex-a53"; 161 reg = <0x000>; 162 enable-method = "psci"; 163 cpu-idle-states = <&CPU_SLEEP_0>; 164 #cooling-cells = <2>; 165 dynamic-power-coefficient = <263>; 166 clocks = <&infracfg CLK_INFRA_CA53SEL>, 167 <&apmixedsys CLK_APMIXED_MAINPLL>; 168 clock-names = "cpu", "intermediate"; 169 operating-points-v2 = <&cluster0_opp>; 170 capacity-dmips-mhz = <740>; 171 }; 172 173 cpu1: cpu@1 { 174 device_type = "cpu"; 175 compatible = "arm,cortex-a53"; 176 reg = <0x001>; 177 enable-method = "psci"; 178 cpu-idle-states = <&CPU_SLEEP_0>; 179 #cooling-cells = <2>; 180 dynamic-power-coefficient = <263>; 181 clocks = <&infracfg CLK_INFRA_CA53SEL>, 182 <&apmixedsys CLK_APMIXED_MAINPLL>; 183 clock-names = "cpu", "intermediate"; 184 operating-points-v2 = <&cluster0_opp>; 185 capacity-dmips-mhz = <740>; 186 }; 187 188 cpu2: cpu@100 { 189 device_type = "cpu"; 190 compatible = "arm,cortex-a72"; 191 reg = <0x100>; 192 enable-method = "psci"; 193 cpu-idle-states = <&CPU_SLEEP_0>; 194 #cooling-cells = <2>; 195 dynamic-power-coefficient = <530>; 196 clocks = <&infracfg CLK_INFRA_CA72SEL>, 197 <&apmixedsys CLK_APMIXED_MAINPLL>; 198 clock-names = "cpu", "intermediate"; 199 operating-points-v2 = <&cluster1_opp>; 200 capacity-dmips-mhz = <1024>; 201 }; 202 203 cpu3: cpu@101 { 204 device_type = "cpu"; 205 compatible = "arm,cortex-a72"; 206 reg = <0x101>; 207 enable-method = "psci"; 208 cpu-idle-states = <&CPU_SLEEP_0>; 209 #cooling-cells = <2>; 210 dynamic-power-coefficient = <530>; 211 clocks = <&infracfg CLK_INFRA_CA72SEL>, 212 <&apmixedsys CLK_APMIXED_MAINPLL>; 213 clock-names = "cpu", "intermediate"; 214 operating-points-v2 = <&cluster1_opp>; 215 capacity-dmips-mhz = <1024>; 216 }; 217 218 idle-states { 219 entry-method = "psci"; 220 221 CPU_SLEEP_0: cpu-sleep-0 { 222 compatible = "arm,idle-state"; 223 local-timer-stop; 224 entry-latency-us = <639>; 225 exit-latency-us = <680>; 226 min-residency-us = <1088>; 227 arm,psci-suspend-param = <0x0010000>; 228 }; 229 }; 230 }; 231 232 pmu_a53 { 233 compatible = "arm,cortex-a53-pmu"; 234 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, 235 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>; 236 interrupt-affinity = <&cpu0>, <&cpu1>; 237 }; 238 239 pmu_a72 { 240 compatible = "arm,cortex-a72-pmu"; 241 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>, 242 <GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>; 243 interrupt-affinity = <&cpu2>, <&cpu3>; 244 }; 245 246 psci { 247 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 248 method = "smc"; 249 cpu_suspend = <0x84000001>; 250 cpu_off = <0x84000002>; 251 cpu_on = <0x84000003>; 252 }; 253 254 clk26m: oscillator0 { 255 compatible = "fixed-clock"; 256 #clock-cells = <0>; 257 clock-frequency = <26000000>; 258 clock-output-names = "clk26m"; 259 }; 260 261 clk32k: oscillator1 { 262 compatible = "fixed-clock"; 263 #clock-cells = <0>; 264 clock-frequency = <32000>; 265 clock-output-names = "clk32k"; 266 }; 267 268 cpum_ck: oscillator2 { 269 compatible = "fixed-clock"; 270 #clock-cells = <0>; 271 clock-frequency = <0>; 272 clock-output-names = "cpum_ck"; 273 }; 274 275 thermal-zones { 276 cpu_thermal: cpu-thermal { 277 polling-delay-passive = <1000>; /* milliseconds */ 278 polling-delay = <1000>; /* milliseconds */ 279 280 thermal-sensors = <&thermal>; 281 sustainable-power = <1500>; /* milliwatts */ 282 283 trips { 284 threshold: trip-point0 { 285 temperature = <68000>; 286 hysteresis = <2000>; 287 type = "passive"; 288 }; 289 290 target: trip-point1 { 291 temperature = <85000>; 292 hysteresis = <2000>; 293 type = "passive"; 294 }; 295 296 cpu_crit: cpu_crit0 { 297 temperature = <115000>; 298 hysteresis = <2000>; 299 type = "critical"; 300 }; 301 }; 302 303 cooling-maps { 304 map0 { 305 trip = <&target>; 306 cooling-device = <&cpu0 THERMAL_NO_LIMIT 307 THERMAL_NO_LIMIT>, 308 <&cpu1 THERMAL_NO_LIMIT 309 THERMAL_NO_LIMIT>; 310 contribution = <3072>; 311 }; 312 map1 { 313 trip = <&target>; 314 cooling-device = <&cpu2 THERMAL_NO_LIMIT 315 THERMAL_NO_LIMIT>, 316 <&cpu3 THERMAL_NO_LIMIT 317 THERMAL_NO_LIMIT>; 318 contribution = <1024>; 319 }; 320 }; 321 }; 322 }; 323 324 reserved-memory { 325 #address-cells = <2>; 326 #size-cells = <2>; 327 ranges; 328 vpu_dma_reserved: vpu_dma_mem_region@b7000000 { 329 compatible = "shared-dma-pool"; 330 reg = <0 0xb7000000 0 0x500000>; 331 alignment = <0x1000>; 332 no-map; 333 }; 334 }; 335 336 timer { 337 compatible = "arm,armv8-timer"; 338 interrupt-parent = <&gic>; 339 interrupts = <GIC_PPI 13 340 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 341 <GIC_PPI 14 342 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 343 <GIC_PPI 11 344 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 345 <GIC_PPI 10 346 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 347 arm,no-tick-in-suspend; 348 }; 349 350 soc { 351 #address-cells = <2>; 352 #size-cells = <2>; 353 compatible = "simple-bus"; 354 ranges; 355 356 topckgen: clock-controller@10000000 { 357 compatible = "mediatek,mt8173-topckgen"; 358 reg = <0 0x10000000 0 0x1000>; 359 #clock-cells = <1>; 360 }; 361 362 infracfg: power-controller@10001000 { 363 compatible = "mediatek,mt8173-infracfg", "syscon"; 364 reg = <0 0x10001000 0 0x1000>; 365 #clock-cells = <1>; 366 #reset-cells = <1>; 367 }; 368 369 pericfg: power-controller@10003000 { 370 compatible = "mediatek,mt8173-pericfg", "syscon"; 371 reg = <0 0x10003000 0 0x1000>; 372 #clock-cells = <1>; 373 #reset-cells = <1>; 374 }; 375 376 syscfg_pctl_a: syscfg_pctl_a@10005000 { 377 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 378 reg = <0 0x10005000 0 0x1000>; 379 }; 380 381 pio: pinctrl@1000b000 { 382 compatible = "mediatek,mt8173-pinctrl"; 383 reg = <0 0x1000b000 0 0x1000>; 384 mediatek,pctl-regmap = <&syscfg_pctl_a>; 385 pins-are-numbered; 386 gpio-controller; 387 #gpio-cells = <2>; 388 interrupt-controller; 389 #interrupt-cells = <2>; 390 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 391 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 392 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 393 394 hdmi_pin: xxx { 395 396 /*hdmi htplg pin*/ 397 pins1 { 398 pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>; 399 input-enable; 400 bias-pull-down; 401 }; 402 }; 403 404 i2c0_pins_a: i2c0 { 405 pins1 { 406 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 407 <MT8173_PIN_46_SCL0__FUNC_SCL0>; 408 bias-disable; 409 }; 410 }; 411 412 i2c1_pins_a: i2c1 { 413 pins1 { 414 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 415 <MT8173_PIN_126_SCL1__FUNC_SCL1>; 416 bias-disable; 417 }; 418 }; 419 420 i2c2_pins_a: i2c2 { 421 pins1 { 422 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 423 <MT8173_PIN_44_SCL2__FUNC_SCL2>; 424 bias-disable; 425 }; 426 }; 427 428 i2c3_pins_a: i2c3 { 429 pins1 { 430 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 431 <MT8173_PIN_107_SCL3__FUNC_SCL3>; 432 bias-disable; 433 }; 434 }; 435 436 i2c4_pins_a: i2c4 { 437 pins1 { 438 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 439 <MT8173_PIN_134_SCL4__FUNC_SCL4>; 440 bias-disable; 441 }; 442 }; 443 444 i2c6_pins_a: i2c6 { 445 pins1 { 446 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 447 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 448 bias-disable; 449 }; 450 }; 451 }; 452 453 scpsys: syscon@10006000 { 454 compatible = "syscon", "simple-mfd"; 455 reg = <0 0x10006000 0 0x1000>; 456 #power-domain-cells = <1>; 457 458 /* System Power Manager */ 459 spm: power-controller { 460 compatible = "mediatek,mt8173-power-controller"; 461 #address-cells = <1>; 462 #size-cells = <0>; 463 #power-domain-cells = <1>; 464 465 /* power domains of the SoC */ 466 power-domain@MT8173_POWER_DOMAIN_VDEC { 467 reg = <MT8173_POWER_DOMAIN_VDEC>; 468 clocks = <&topckgen CLK_TOP_MM_SEL>; 469 clock-names = "mm"; 470 #power-domain-cells = <0>; 471 }; 472 power-domain@MT8173_POWER_DOMAIN_VENC { 473 reg = <MT8173_POWER_DOMAIN_VENC>; 474 clocks = <&topckgen CLK_TOP_MM_SEL>, 475 <&topckgen CLK_TOP_VENC_SEL>; 476 clock-names = "mm", "venc"; 477 #power-domain-cells = <0>; 478 }; 479 power-domain@MT8173_POWER_DOMAIN_ISP { 480 reg = <MT8173_POWER_DOMAIN_ISP>; 481 clocks = <&topckgen CLK_TOP_MM_SEL>; 482 clock-names = "mm"; 483 #power-domain-cells = <0>; 484 }; 485 power-domain@MT8173_POWER_DOMAIN_MM { 486 reg = <MT8173_POWER_DOMAIN_MM>; 487 clocks = <&topckgen CLK_TOP_MM_SEL>; 488 clock-names = "mm"; 489 #power-domain-cells = <0>; 490 mediatek,infracfg = <&infracfg>; 491 }; 492 power-domain@MT8173_POWER_DOMAIN_VENC_LT { 493 reg = <MT8173_POWER_DOMAIN_VENC_LT>; 494 clocks = <&topckgen CLK_TOP_MM_SEL>, 495 <&topckgen CLK_TOP_VENC_LT_SEL>; 496 clock-names = "mm", "venclt"; 497 #power-domain-cells = <0>; 498 }; 499 power-domain@MT8173_POWER_DOMAIN_AUDIO { 500 reg = <MT8173_POWER_DOMAIN_AUDIO>; 501 #power-domain-cells = <0>; 502 }; 503 power-domain@MT8173_POWER_DOMAIN_USB { 504 reg = <MT8173_POWER_DOMAIN_USB>; 505 #power-domain-cells = <0>; 506 }; 507 mfg_async: power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC { 508 reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>; 509 clocks = <&clk26m>; 510 clock-names = "mfg"; 511 #address-cells = <1>; 512 #size-cells = <0>; 513 #power-domain-cells = <1>; 514 515 power-domain@MT8173_POWER_DOMAIN_MFG_2D { 516 reg = <MT8173_POWER_DOMAIN_MFG_2D>; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 #power-domain-cells = <1>; 520 521 power-domain@MT8173_POWER_DOMAIN_MFG { 522 reg = <MT8173_POWER_DOMAIN_MFG>; 523 #power-domain-cells = <0>; 524 mediatek,infracfg = <&infracfg>; 525 }; 526 }; 527 }; 528 }; 529 }; 530 531 watchdog: watchdog@10007000 { 532 compatible = "mediatek,mt8173-wdt", 533 "mediatek,mt6589-wdt"; 534 reg = <0 0x10007000 0 0x100>; 535 }; 536 537 timer: timer@10008000 { 538 compatible = "mediatek,mt8173-timer", 539 "mediatek,mt6577-timer"; 540 reg = <0 0x10008000 0 0x1000>; 541 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 542 clocks = <&infracfg CLK_INFRA_CLK_13M>, 543 <&topckgen CLK_TOP_RTC_SEL>; 544 }; 545 546 pwrap: pwrap@1000d000 { 547 compatible = "mediatek,mt8173-pwrap"; 548 reg = <0 0x1000d000 0 0x1000>; 549 reg-names = "pwrap"; 550 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 551 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 552 reset-names = "pwrap"; 553 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 554 clock-names = "spi", "wrap"; 555 }; 556 557 cec: cec@10013000 { 558 compatible = "mediatek,mt8173-cec"; 559 reg = <0 0x10013000 0 0xbc>; 560 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; 561 clocks = <&infracfg CLK_INFRA_CEC>; 562 status = "disabled"; 563 }; 564 565 vpu: vpu@10020000 { 566 compatible = "mediatek,mt8173-vpu"; 567 reg = <0 0x10020000 0 0x30000>, 568 <0 0x10050000 0 0x100>; 569 reg-names = "tcm", "cfg_reg"; 570 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 571 clocks = <&topckgen CLK_TOP_SCP_SEL>; 572 clock-names = "main"; 573 memory-region = <&vpu_dma_reserved>; 574 }; 575 576 sysirq: intpol-controller@10200620 { 577 compatible = "mediatek,mt8173-sysirq", 578 "mediatek,mt6577-sysirq"; 579 interrupt-controller; 580 #interrupt-cells = <3>; 581 interrupt-parent = <&gic>; 582 reg = <0 0x10200620 0 0x20>; 583 }; 584 585 iommu: iommu@10205000 { 586 compatible = "mediatek,mt8173-m4u"; 587 reg = <0 0x10205000 0 0x1000>; 588 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 589 clocks = <&infracfg CLK_INFRA_M4U>; 590 clock-names = "bclk"; 591 mediatek,infracfg = <&infracfg>; 592 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, 593 <&larb3>, <&larb4>, <&larb5>; 594 #iommu-cells = <1>; 595 }; 596 597 efuse: efuse@10206000 { 598 compatible = "mediatek,mt8173-efuse"; 599 reg = <0 0x10206000 0 0x1000>; 600 #address-cells = <1>; 601 #size-cells = <1>; 602 thermal_calibration: calib@528 { 603 reg = <0x528 0xc>; 604 }; 605 }; 606 607 apmixedsys: clock-controller@10209000 { 608 compatible = "mediatek,mt8173-apmixedsys"; 609 reg = <0 0x10209000 0 0x1000>; 610 #clock-cells = <1>; 611 }; 612 613 hdmi_phy: hdmi-phy@10209100 { 614 compatible = "mediatek,mt8173-hdmi-phy"; 615 reg = <0 0x10209100 0 0x24>; 616 clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; 617 clock-names = "pll_ref"; 618 clock-output-names = "hdmitx_dig_cts"; 619 mediatek,ibias = <0xa>; 620 mediatek,ibias_up = <0x1c>; 621 #clock-cells = <0>; 622 #phy-cells = <0>; 623 status = "disabled"; 624 }; 625 626 gce: mailbox@10212000 { 627 compatible = "mediatek,mt8173-gce"; 628 reg = <0 0x10212000 0 0x1000>; 629 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 630 clocks = <&infracfg CLK_INFRA_GCE>; 631 clock-names = "gce"; 632 #mbox-cells = <2>; 633 }; 634 635 mipi_tx0: dsi-phy@10215000 { 636 compatible = "mediatek,mt8173-mipi-tx"; 637 reg = <0 0x10215000 0 0x1000>; 638 clocks = <&clk26m>; 639 clock-output-names = "mipi_tx0_pll"; 640 #clock-cells = <0>; 641 #phy-cells = <0>; 642 status = "disabled"; 643 }; 644 645 mipi_tx1: dsi-phy@10216000 { 646 compatible = "mediatek,mt8173-mipi-tx"; 647 reg = <0 0x10216000 0 0x1000>; 648 clocks = <&clk26m>; 649 clock-output-names = "mipi_tx1_pll"; 650 #clock-cells = <0>; 651 #phy-cells = <0>; 652 status = "disabled"; 653 }; 654 655 gic: interrupt-controller@10221000 { 656 compatible = "arm,gic-400"; 657 #interrupt-cells = <3>; 658 interrupt-parent = <&gic>; 659 interrupt-controller; 660 reg = <0 0x10221000 0 0x1000>, 661 <0 0x10222000 0 0x2000>, 662 <0 0x10224000 0 0x2000>, 663 <0 0x10226000 0 0x2000>; 664 interrupts = <GIC_PPI 9 665 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 666 }; 667 668 auxadc: auxadc@11001000 { 669 compatible = "mediatek,mt8173-auxadc"; 670 reg = <0 0x11001000 0 0x1000>; 671 clocks = <&pericfg CLK_PERI_AUXADC>; 672 clock-names = "main"; 673 #io-channel-cells = <1>; 674 }; 675 676 uart0: serial@11002000 { 677 compatible = "mediatek,mt8173-uart", 678 "mediatek,mt6577-uart"; 679 reg = <0 0x11002000 0 0x400>; 680 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 681 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 682 clock-names = "baud", "bus"; 683 status = "disabled"; 684 }; 685 686 uart1: serial@11003000 { 687 compatible = "mediatek,mt8173-uart", 688 "mediatek,mt6577-uart"; 689 reg = <0 0x11003000 0 0x400>; 690 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 691 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 692 clock-names = "baud", "bus"; 693 status = "disabled"; 694 }; 695 696 uart2: serial@11004000 { 697 compatible = "mediatek,mt8173-uart", 698 "mediatek,mt6577-uart"; 699 reg = <0 0x11004000 0 0x400>; 700 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 701 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 702 clock-names = "baud", "bus"; 703 status = "disabled"; 704 }; 705 706 uart3: serial@11005000 { 707 compatible = "mediatek,mt8173-uart", 708 "mediatek,mt6577-uart"; 709 reg = <0 0x11005000 0 0x400>; 710 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 711 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 712 clock-names = "baud", "bus"; 713 status = "disabled"; 714 }; 715 716 i2c0: i2c@11007000 { 717 compatible = "mediatek,mt8173-i2c"; 718 reg = <0 0x11007000 0 0x70>, 719 <0 0x11000100 0 0x80>; 720 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 721 clock-div = <16>; 722 clocks = <&pericfg CLK_PERI_I2C0>, 723 <&pericfg CLK_PERI_AP_DMA>; 724 clock-names = "main", "dma"; 725 pinctrl-names = "default"; 726 pinctrl-0 = <&i2c0_pins_a>; 727 #address-cells = <1>; 728 #size-cells = <0>; 729 status = "disabled"; 730 }; 731 732 i2c1: i2c@11008000 { 733 compatible = "mediatek,mt8173-i2c"; 734 reg = <0 0x11008000 0 0x70>, 735 <0 0x11000180 0 0x80>; 736 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 737 clock-div = <16>; 738 clocks = <&pericfg CLK_PERI_I2C1>, 739 <&pericfg CLK_PERI_AP_DMA>; 740 clock-names = "main", "dma"; 741 pinctrl-names = "default"; 742 pinctrl-0 = <&i2c1_pins_a>; 743 #address-cells = <1>; 744 #size-cells = <0>; 745 status = "disabled"; 746 }; 747 748 i2c2: i2c@11009000 { 749 compatible = "mediatek,mt8173-i2c"; 750 reg = <0 0x11009000 0 0x70>, 751 <0 0x11000200 0 0x80>; 752 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 753 clock-div = <16>; 754 clocks = <&pericfg CLK_PERI_I2C2>, 755 <&pericfg CLK_PERI_AP_DMA>; 756 clock-names = "main", "dma"; 757 pinctrl-names = "default"; 758 pinctrl-0 = <&i2c2_pins_a>; 759 #address-cells = <1>; 760 #size-cells = <0>; 761 status = "disabled"; 762 }; 763 764 spi: spi@1100a000 { 765 compatible = "mediatek,mt8173-spi"; 766 #address-cells = <1>; 767 #size-cells = <0>; 768 reg = <0 0x1100a000 0 0x1000>; 769 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 770 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 771 <&topckgen CLK_TOP_SPI_SEL>, 772 <&pericfg CLK_PERI_SPI0>; 773 clock-names = "parent-clk", "sel-clk", "spi-clk"; 774 status = "disabled"; 775 }; 776 777 thermal: thermal@1100b000 { 778 #thermal-sensor-cells = <0>; 779 compatible = "mediatek,mt8173-thermal"; 780 reg = <0 0x1100b000 0 0x1000>; 781 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 782 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 783 clock-names = "therm", "auxadc"; 784 resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 785 mediatek,auxadc = <&auxadc>; 786 mediatek,apmixedsys = <&apmixedsys>; 787 nvmem-cells = <&thermal_calibration>; 788 nvmem-cell-names = "calibration-data"; 789 }; 790 791 nor_flash: spi@1100d000 { 792 compatible = "mediatek,mt8173-nor"; 793 reg = <0 0x1100d000 0 0xe0>; 794 clocks = <&pericfg CLK_PERI_SPI>, 795 <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 796 clock-names = "spi", "sf"; 797 #address-cells = <1>; 798 #size-cells = <0>; 799 status = "disabled"; 800 }; 801 802 i2c3: i2c@11010000 { 803 compatible = "mediatek,mt8173-i2c"; 804 reg = <0 0x11010000 0 0x70>, 805 <0 0x11000280 0 0x80>; 806 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 807 clock-div = <16>; 808 clocks = <&pericfg CLK_PERI_I2C3>, 809 <&pericfg CLK_PERI_AP_DMA>; 810 clock-names = "main", "dma"; 811 pinctrl-names = "default"; 812 pinctrl-0 = <&i2c3_pins_a>; 813 #address-cells = <1>; 814 #size-cells = <0>; 815 status = "disabled"; 816 }; 817 818 i2c4: i2c@11011000 { 819 compatible = "mediatek,mt8173-i2c"; 820 reg = <0 0x11011000 0 0x70>, 821 <0 0x11000300 0 0x80>; 822 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 823 clock-div = <16>; 824 clocks = <&pericfg CLK_PERI_I2C4>, 825 <&pericfg CLK_PERI_AP_DMA>; 826 clock-names = "main", "dma"; 827 pinctrl-names = "default"; 828 pinctrl-0 = <&i2c4_pins_a>; 829 #address-cells = <1>; 830 #size-cells = <0>; 831 status = "disabled"; 832 }; 833 834 hdmiddc0: i2c@11012000 { 835 compatible = "mediatek,mt8173-hdmi-ddc"; 836 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 837 reg = <0 0x11012000 0 0x1C>; 838 clocks = <&pericfg CLK_PERI_I2C5>; 839 clock-names = "ddc-i2c"; 840 }; 841 842 i2c6: i2c@11013000 { 843 compatible = "mediatek,mt8173-i2c"; 844 reg = <0 0x11013000 0 0x70>, 845 <0 0x11000080 0 0x80>; 846 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 847 clock-div = <16>; 848 clocks = <&pericfg CLK_PERI_I2C6>, 849 <&pericfg CLK_PERI_AP_DMA>; 850 clock-names = "main", "dma"; 851 pinctrl-names = "default"; 852 pinctrl-0 = <&i2c6_pins_a>; 853 #address-cells = <1>; 854 #size-cells = <0>; 855 status = "disabled"; 856 }; 857 858 afe: audio-controller@11220000 { 859 compatible = "mediatek,mt8173-afe-pcm"; 860 reg = <0 0x11220000 0 0x1000>; 861 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 862 power-domains = <&spm MT8173_POWER_DOMAIN_AUDIO>; 863 clocks = <&infracfg CLK_INFRA_AUDIO>, 864 <&topckgen CLK_TOP_AUDIO_SEL>, 865 <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 866 <&topckgen CLK_TOP_APLL1_DIV0>, 867 <&topckgen CLK_TOP_APLL2_DIV0>, 868 <&topckgen CLK_TOP_I2S0_M_SEL>, 869 <&topckgen CLK_TOP_I2S1_M_SEL>, 870 <&topckgen CLK_TOP_I2S2_M_SEL>, 871 <&topckgen CLK_TOP_I2S3_M_SEL>, 872 <&topckgen CLK_TOP_I2S3_B_SEL>; 873 clock-names = "infra_sys_audio_clk", 874 "top_pdn_audio", 875 "top_pdn_aud_intbus", 876 "bck0", 877 "bck1", 878 "i2s0_m", 879 "i2s1_m", 880 "i2s2_m", 881 "i2s3_m", 882 "i2s3_b"; 883 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 884 <&topckgen CLK_TOP_AUD_2_SEL>; 885 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 886 <&topckgen CLK_TOP_APLL2>; 887 }; 888 889 mmc0: mmc@11230000 { 890 compatible = "mediatek,mt8173-mmc"; 891 reg = <0 0x11230000 0 0x1000>; 892 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 893 clocks = <&pericfg CLK_PERI_MSDC30_0>, 894 <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 895 clock-names = "source", "hclk"; 896 status = "disabled"; 897 }; 898 899 mmc1: mmc@11240000 { 900 compatible = "mediatek,mt8173-mmc"; 901 reg = <0 0x11240000 0 0x1000>; 902 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 903 clocks = <&pericfg CLK_PERI_MSDC30_1>, 904 <&topckgen CLK_TOP_AXI_SEL>; 905 clock-names = "source", "hclk"; 906 status = "disabled"; 907 }; 908 909 mmc2: mmc@11250000 { 910 compatible = "mediatek,mt8173-mmc"; 911 reg = <0 0x11250000 0 0x1000>; 912 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 913 clocks = <&pericfg CLK_PERI_MSDC30_2>, 914 <&topckgen CLK_TOP_AXI_SEL>; 915 clock-names = "source", "hclk"; 916 status = "disabled"; 917 }; 918 919 mmc3: mmc@11260000 { 920 compatible = "mediatek,mt8173-mmc"; 921 reg = <0 0x11260000 0 0x1000>; 922 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 923 clocks = <&pericfg CLK_PERI_MSDC30_3>, 924 <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 925 clock-names = "source", "hclk"; 926 status = "disabled"; 927 }; 928 929 ssusb: usb@11271000 { 930 compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3"; 931 reg = <0 0x11271000 0 0x3000>, 932 <0 0x11280700 0 0x0100>; 933 reg-names = "mac", "ippc"; 934 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>; 935 phys = <&u2port0 PHY_TYPE_USB2>, 936 <&u3port0 PHY_TYPE_USB3>, 937 <&u2port1 PHY_TYPE_USB2>; 938 power-domains = <&spm MT8173_POWER_DOMAIN_USB>; 939 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 940 clock-names = "sys_ck", "ref_ck"; 941 mediatek,syscon-wakeup = <&pericfg 0x400 1>; 942 #address-cells = <2>; 943 #size-cells = <2>; 944 ranges; 945 status = "disabled"; 946 947 usb_host: usb@11270000 { 948 compatible = "mediatek,mt8173-xhci", 949 "mediatek,mtk-xhci"; 950 reg = <0 0x11270000 0 0x1000>; 951 reg-names = "mac"; 952 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 953 power-domains = <&spm MT8173_POWER_DOMAIN_USB>; 954 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 955 clock-names = "sys_ck", "ref_ck"; 956 status = "disabled"; 957 }; 958 }; 959 960 u3phy: t-phy@11290000 { 961 compatible = "mediatek,mt8173-u3phy"; 962 reg = <0 0x11290000 0 0x800>; 963 #address-cells = <2>; 964 #size-cells = <2>; 965 ranges; 966 status = "okay"; 967 968 u2port0: usb-phy@11290800 { 969 reg = <0 0x11290800 0 0x100>; 970 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 971 clock-names = "ref"; 972 #phy-cells = <1>; 973 status = "okay"; 974 }; 975 976 u3port0: usb-phy@11290900 { 977 reg = <0 0x11290900 0 0x700>; 978 clocks = <&clk26m>; 979 clock-names = "ref"; 980 #phy-cells = <1>; 981 status = "okay"; 982 }; 983 984 u2port1: usb-phy@11291000 { 985 reg = <0 0x11291000 0 0x100>; 986 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 987 clock-names = "ref"; 988 #phy-cells = <1>; 989 status = "okay"; 990 }; 991 }; 992 993 mmsys: syscon@14000000 { 994 compatible = "mediatek,mt8173-mmsys", "syscon"; 995 reg = <0 0x14000000 0 0x1000>; 996 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 997 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; 998 assigned-clock-rates = <400000000>; 999 #clock-cells = <1>; 1000 #reset-cells = <1>; 1001 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 1002 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 1003 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 1004 }; 1005 1006 mdp_rdma0: rdma@14001000 { 1007 compatible = "mediatek,mt8173-mdp-rdma", 1008 "mediatek,mt8173-mdp"; 1009 reg = <0 0x14001000 0 0x1000>; 1010 clocks = <&mmsys CLK_MM_MDP_RDMA0>, 1011 <&mmsys CLK_MM_MUTEX_32K>; 1012 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1013 iommus = <&iommu M4U_PORT_MDP_RDMA0>; 1014 mediatek,vpu = <&vpu>; 1015 }; 1016 1017 mdp_rdma1: rdma@14002000 { 1018 compatible = "mediatek,mt8173-mdp-rdma"; 1019 reg = <0 0x14002000 0 0x1000>; 1020 clocks = <&mmsys CLK_MM_MDP_RDMA1>, 1021 <&mmsys CLK_MM_MUTEX_32K>; 1022 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1023 iommus = <&iommu M4U_PORT_MDP_RDMA1>; 1024 }; 1025 1026 mdp_rsz0: rsz@14003000 { 1027 compatible = "mediatek,mt8173-mdp-rsz"; 1028 reg = <0 0x14003000 0 0x1000>; 1029 clocks = <&mmsys CLK_MM_MDP_RSZ0>; 1030 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1031 }; 1032 1033 mdp_rsz1: rsz@14004000 { 1034 compatible = "mediatek,mt8173-mdp-rsz"; 1035 reg = <0 0x14004000 0 0x1000>; 1036 clocks = <&mmsys CLK_MM_MDP_RSZ1>; 1037 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1038 }; 1039 1040 mdp_rsz2: rsz@14005000 { 1041 compatible = "mediatek,mt8173-mdp-rsz"; 1042 reg = <0 0x14005000 0 0x1000>; 1043 clocks = <&mmsys CLK_MM_MDP_RSZ2>; 1044 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1045 }; 1046 1047 mdp_wdma0: wdma@14006000 { 1048 compatible = "mediatek,mt8173-mdp-wdma"; 1049 reg = <0 0x14006000 0 0x1000>; 1050 clocks = <&mmsys CLK_MM_MDP_WDMA>; 1051 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1052 iommus = <&iommu M4U_PORT_MDP_WDMA>; 1053 }; 1054 1055 mdp_wrot0: wrot@14007000 { 1056 compatible = "mediatek,mt8173-mdp-wrot"; 1057 reg = <0 0x14007000 0 0x1000>; 1058 clocks = <&mmsys CLK_MM_MDP_WROT0>; 1059 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1060 iommus = <&iommu M4U_PORT_MDP_WROT0>; 1061 }; 1062 1063 mdp_wrot1: wrot@14008000 { 1064 compatible = "mediatek,mt8173-mdp-wrot"; 1065 reg = <0 0x14008000 0 0x1000>; 1066 clocks = <&mmsys CLK_MM_MDP_WROT1>; 1067 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1068 iommus = <&iommu M4U_PORT_MDP_WROT1>; 1069 }; 1070 1071 ovl0: ovl@1400c000 { 1072 compatible = "mediatek,mt8173-disp-ovl"; 1073 reg = <0 0x1400c000 0 0x1000>; 1074 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 1075 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1076 clocks = <&mmsys CLK_MM_DISP_OVL0>; 1077 iommus = <&iommu M4U_PORT_DISP_OVL0>; 1078 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1079 }; 1080 1081 ovl1: ovl@1400d000 { 1082 compatible = "mediatek,mt8173-disp-ovl"; 1083 reg = <0 0x1400d000 0 0x1000>; 1084 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; 1085 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1086 clocks = <&mmsys CLK_MM_DISP_OVL1>; 1087 iommus = <&iommu M4U_PORT_DISP_OVL1>; 1088 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 1089 }; 1090 1091 rdma0: rdma@1400e000 { 1092 compatible = "mediatek,mt8173-disp-rdma"; 1093 reg = <0 0x1400e000 0 0x1000>; 1094 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 1095 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1096 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1097 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 1098 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1099 }; 1100 1101 rdma1: rdma@1400f000 { 1102 compatible = "mediatek,mt8173-disp-rdma"; 1103 reg = <0 0x1400f000 0 0x1000>; 1104 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; 1105 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1106 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 1107 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 1108 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; 1109 }; 1110 1111 rdma2: rdma@14010000 { 1112 compatible = "mediatek,mt8173-disp-rdma"; 1113 reg = <0 0x14010000 0 0x1000>; 1114 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; 1115 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1116 clocks = <&mmsys CLK_MM_DISP_RDMA2>; 1117 iommus = <&iommu M4U_PORT_DISP_RDMA2>; 1118 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; 1119 }; 1120 1121 wdma0: wdma@14011000 { 1122 compatible = "mediatek,mt8173-disp-wdma"; 1123 reg = <0 0x14011000 0 0x1000>; 1124 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 1125 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1126 clocks = <&mmsys CLK_MM_DISP_WDMA0>; 1127 iommus = <&iommu M4U_PORT_DISP_WDMA0>; 1128 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 1129 }; 1130 1131 wdma1: wdma@14012000 { 1132 compatible = "mediatek,mt8173-disp-wdma"; 1133 reg = <0 0x14012000 0 0x1000>; 1134 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; 1135 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1136 clocks = <&mmsys CLK_MM_DISP_WDMA1>; 1137 iommus = <&iommu M4U_PORT_DISP_WDMA1>; 1138 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; 1139 }; 1140 1141 color0: color@14013000 { 1142 compatible = "mediatek,mt8173-disp-color"; 1143 reg = <0 0x14013000 0 0x1000>; 1144 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; 1145 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1146 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1147 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>; 1148 }; 1149 1150 color1: color@14014000 { 1151 compatible = "mediatek,mt8173-disp-color"; 1152 reg = <0 0x14014000 0 0x1000>; 1153 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 1154 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1155 clocks = <&mmsys CLK_MM_DISP_COLOR1>; 1156 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; 1157 }; 1158 1159 aal@14015000 { 1160 compatible = "mediatek,mt8173-disp-aal"; 1161 reg = <0 0x14015000 0 0x1000>; 1162 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 1163 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1164 clocks = <&mmsys CLK_MM_DISP_AAL>; 1165 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; 1166 }; 1167 1168 gamma@14016000 { 1169 compatible = "mediatek,mt8173-disp-gamma"; 1170 reg = <0 0x14016000 0 0x1000>; 1171 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 1172 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1173 clocks = <&mmsys CLK_MM_DISP_GAMMA>; 1174 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; 1175 }; 1176 1177 merge@14017000 { 1178 compatible = "mediatek,mt8173-disp-merge"; 1179 reg = <0 0x14017000 0 0x1000>; 1180 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1181 clocks = <&mmsys CLK_MM_DISP_MERGE>; 1182 }; 1183 1184 split0: split@14018000 { 1185 compatible = "mediatek,mt8173-disp-split"; 1186 reg = <0 0x14018000 0 0x1000>; 1187 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1188 clocks = <&mmsys CLK_MM_DISP_SPLIT0>; 1189 }; 1190 1191 split1: split@14019000 { 1192 compatible = "mediatek,mt8173-disp-split"; 1193 reg = <0 0x14019000 0 0x1000>; 1194 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1195 clocks = <&mmsys CLK_MM_DISP_SPLIT1>; 1196 }; 1197 1198 ufoe@1401a000 { 1199 compatible = "mediatek,mt8173-disp-ufoe"; 1200 reg = <0 0x1401a000 0 0x1000>; 1201 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 1202 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1203 clocks = <&mmsys CLK_MM_DISP_UFOE>; 1204 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>; 1205 }; 1206 1207 dsi0: dsi@1401b000 { 1208 compatible = "mediatek,mt8173-dsi"; 1209 reg = <0 0x1401b000 0 0x1000>; 1210 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 1211 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1212 clocks = <&mmsys CLK_MM_DSI0_ENGINE>, 1213 <&mmsys CLK_MM_DSI0_DIGITAL>, 1214 <&mipi_tx0>; 1215 clock-names = "engine", "digital", "hs"; 1216 resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>; 1217 phys = <&mipi_tx0>; 1218 phy-names = "dphy"; 1219 status = "disabled"; 1220 }; 1221 1222 dsi1: dsi@1401c000 { 1223 compatible = "mediatek,mt8173-dsi"; 1224 reg = <0 0x1401c000 0 0x1000>; 1225 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 1226 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1227 clocks = <&mmsys CLK_MM_DSI1_ENGINE>, 1228 <&mmsys CLK_MM_DSI1_DIGITAL>, 1229 <&mipi_tx1>; 1230 clock-names = "engine", "digital", "hs"; 1231 phys = <&mipi_tx1>; 1232 phy-names = "dphy"; 1233 status = "disabled"; 1234 }; 1235 1236 dpi0: dpi@1401d000 { 1237 compatible = "mediatek,mt8173-dpi"; 1238 reg = <0 0x1401d000 0 0x1000>; 1239 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 1240 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1241 clocks = <&mmsys CLK_MM_DPI_PIXEL>, 1242 <&mmsys CLK_MM_DPI_ENGINE>, 1243 <&apmixedsys CLK_APMIXED_TVDPLL>; 1244 clock-names = "pixel", "engine", "pll"; 1245 status = "disabled"; 1246 1247 port { 1248 dpi0_out: endpoint { 1249 remote-endpoint = <&hdmi0_in>; 1250 }; 1251 }; 1252 }; 1253 1254 pwm0: pwm@1401e000 { 1255 compatible = "mediatek,mt8173-disp-pwm", 1256 "mediatek,mt6595-disp-pwm"; 1257 reg = <0 0x1401e000 0 0x1000>; 1258 #pwm-cells = <2>; 1259 clocks = <&mmsys CLK_MM_DISP_PWM026M>, 1260 <&mmsys CLK_MM_DISP_PWM0MM>; 1261 clock-names = "main", "mm"; 1262 status = "disabled"; 1263 }; 1264 1265 pwm1: pwm@1401f000 { 1266 compatible = "mediatek,mt8173-disp-pwm", 1267 "mediatek,mt6595-disp-pwm"; 1268 reg = <0 0x1401f000 0 0x1000>; 1269 #pwm-cells = <2>; 1270 clocks = <&mmsys CLK_MM_DISP_PWM126M>, 1271 <&mmsys CLK_MM_DISP_PWM1MM>; 1272 clock-names = "main", "mm"; 1273 status = "disabled"; 1274 }; 1275 1276 mutex: mutex@14020000 { 1277 compatible = "mediatek,mt8173-disp-mutex"; 1278 reg = <0 0x14020000 0 0x1000>; 1279 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 1280 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1281 clocks = <&mmsys CLK_MM_MUTEX_32K>; 1282 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0 0x1000>; 1283 mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>, 1284 <CMDQ_EVENT_MUTEX1_STREAM_EOF>; 1285 }; 1286 1287 larb0: larb@14021000 { 1288 compatible = "mediatek,mt8173-smi-larb"; 1289 reg = <0 0x14021000 0 0x1000>; 1290 mediatek,smi = <&smi_common>; 1291 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1292 clocks = <&mmsys CLK_MM_SMI_LARB0>, 1293 <&mmsys CLK_MM_SMI_LARB0>; 1294 clock-names = "apb", "smi"; 1295 }; 1296 1297 smi_common: smi@14022000 { 1298 compatible = "mediatek,mt8173-smi-common"; 1299 reg = <0 0x14022000 0 0x1000>; 1300 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1301 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1302 <&mmsys CLK_MM_SMI_COMMON>; 1303 clock-names = "apb", "smi"; 1304 }; 1305 1306 od@14023000 { 1307 compatible = "mediatek,mt8173-disp-od"; 1308 reg = <0 0x14023000 0 0x1000>; 1309 clocks = <&mmsys CLK_MM_DISP_OD>; 1310 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>; 1311 }; 1312 1313 hdmi0: hdmi@14025000 { 1314 compatible = "mediatek,mt8173-hdmi"; 1315 reg = <0 0x14025000 0 0x400>; 1316 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>; 1317 clocks = <&mmsys CLK_MM_HDMI_PIXEL>, 1318 <&mmsys CLK_MM_HDMI_PLLCK>, 1319 <&mmsys CLK_MM_HDMI_AUDIO>, 1320 <&mmsys CLK_MM_HDMI_SPDIF>; 1321 clock-names = "pixel", "pll", "bclk", "spdif"; 1322 pinctrl-names = "default"; 1323 pinctrl-0 = <&hdmi_pin>; 1324 phys = <&hdmi_phy>; 1325 phy-names = "hdmi"; 1326 mediatek,syscon-hdmi = <&mmsys 0x900>; 1327 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; 1328 assigned-clock-parents = <&hdmi_phy>; 1329 status = "disabled"; 1330 1331 ports { 1332 #address-cells = <1>; 1333 #size-cells = <0>; 1334 1335 port@0 { 1336 reg = <0>; 1337 1338 hdmi0_in: endpoint { 1339 remote-endpoint = <&dpi0_out>; 1340 }; 1341 }; 1342 }; 1343 }; 1344 1345 larb4: larb@14027000 { 1346 compatible = "mediatek,mt8173-smi-larb"; 1347 reg = <0 0x14027000 0 0x1000>; 1348 mediatek,smi = <&smi_common>; 1349 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1350 clocks = <&mmsys CLK_MM_SMI_LARB4>, 1351 <&mmsys CLK_MM_SMI_LARB4>; 1352 clock-names = "apb", "smi"; 1353 }; 1354 1355 imgsys: clock-controller@15000000 { 1356 compatible = "mediatek,mt8173-imgsys", "syscon"; 1357 reg = <0 0x15000000 0 0x1000>; 1358 #clock-cells = <1>; 1359 }; 1360 1361 larb2: larb@15001000 { 1362 compatible = "mediatek,mt8173-smi-larb"; 1363 reg = <0 0x15001000 0 0x1000>; 1364 mediatek,smi = <&smi_common>; 1365 power-domains = <&spm MT8173_POWER_DOMAIN_ISP>; 1366 clocks = <&imgsys CLK_IMG_LARB2_SMI>, 1367 <&imgsys CLK_IMG_LARB2_SMI>; 1368 clock-names = "apb", "smi"; 1369 }; 1370 1371 vdecsys: clock-controller@16000000 { 1372 compatible = "mediatek,mt8173-vdecsys", "syscon"; 1373 reg = <0 0x16000000 0 0x1000>; 1374 #clock-cells = <1>; 1375 }; 1376 1377 vcodec_dec: vcodec@16000000 { 1378 compatible = "mediatek,mt8173-vcodec-dec"; 1379 reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */ 1380 <0 0x16020000 0 0x1000>, /* VDEC_MISC */ 1381 <0 0x16021000 0 0x800>, /* VDEC_LD */ 1382 <0 0x16021800 0 0x800>, /* VDEC_TOP */ 1383 <0 0x16022000 0 0x1000>, /* VDEC_CM */ 1384 <0 0x16023000 0 0x1000>, /* VDEC_AD */ 1385 <0 0x16024000 0 0x1000>, /* VDEC_AV */ 1386 <0 0x16025000 0 0x1000>, /* VDEC_PP */ 1387 <0 0x16026800 0 0x800>, /* VDEC_HWD */ 1388 <0 0x16027000 0 0x800>, /* VDEC_HWQ */ 1389 <0 0x16027800 0 0x800>, /* VDEC_HWB */ 1390 <0 0x16028400 0 0x400>; /* VDEC_HWG */ 1391 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; 1392 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, 1393 <&iommu M4U_PORT_HW_VDEC_PP_EXT>, 1394 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, 1395 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, 1396 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, 1397 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, 1398 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, 1399 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; 1400 mediatek,vpu = <&vpu>; 1401 power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>; 1402 clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, 1403 <&topckgen CLK_TOP_UNIVPLL_D2>, 1404 <&topckgen CLK_TOP_CCI400_SEL>, 1405 <&topckgen CLK_TOP_VDEC_SEL>, 1406 <&topckgen CLK_TOP_VCODECPLL>, 1407 <&apmixedsys CLK_APMIXED_VENCPLL>, 1408 <&topckgen CLK_TOP_VENC_LT_SEL>, 1409 <&topckgen CLK_TOP_VCODECPLL_370P5>; 1410 clock-names = "vcodecpll", 1411 "univpll_d2", 1412 "clk_cci400_sel", 1413 "vdec_sel", 1414 "vdecpll", 1415 "vencpll", 1416 "venc_lt_sel", 1417 "vdec_bus_clk_src"; 1418 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>, 1419 <&topckgen CLK_TOP_CCI400_SEL>, 1420 <&topckgen CLK_TOP_VDEC_SEL>, 1421 <&apmixedsys CLK_APMIXED_VCODECPLL>, 1422 <&apmixedsys CLK_APMIXED_VENCPLL>; 1423 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>, 1424 <&topckgen CLK_TOP_UNIVPLL_D2>, 1425 <&topckgen CLK_TOP_VCODECPLL>; 1426 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>; 1427 }; 1428 1429 larb1: larb@16010000 { 1430 compatible = "mediatek,mt8173-smi-larb"; 1431 reg = <0 0x16010000 0 0x1000>; 1432 mediatek,smi = <&smi_common>; 1433 power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>; 1434 clocks = <&vdecsys CLK_VDEC_CKEN>, 1435 <&vdecsys CLK_VDEC_LARB_CKEN>; 1436 clock-names = "apb", "smi"; 1437 }; 1438 1439 vencsys: clock-controller@18000000 { 1440 compatible = "mediatek,mt8173-vencsys", "syscon"; 1441 reg = <0 0x18000000 0 0x1000>; 1442 #clock-cells = <1>; 1443 }; 1444 1445 larb3: larb@18001000 { 1446 compatible = "mediatek,mt8173-smi-larb"; 1447 reg = <0 0x18001000 0 0x1000>; 1448 mediatek,smi = <&smi_common>; 1449 power-domains = <&spm MT8173_POWER_DOMAIN_VENC>; 1450 clocks = <&vencsys CLK_VENC_CKE1>, 1451 <&vencsys CLK_VENC_CKE0>; 1452 clock-names = "apb", "smi"; 1453 }; 1454 1455 vcodec_enc_avc: vcodec@18002000 { 1456 compatible = "mediatek,mt8173-vcodec-enc"; 1457 reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */ 1458 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; 1459 iommus = <&iommu M4U_PORT_VENC_RCPU>, 1460 <&iommu M4U_PORT_VENC_REC>, 1461 <&iommu M4U_PORT_VENC_BSDMA>, 1462 <&iommu M4U_PORT_VENC_SV_COMV>, 1463 <&iommu M4U_PORT_VENC_RD_COMV>, 1464 <&iommu M4U_PORT_VENC_CUR_LUMA>, 1465 <&iommu M4U_PORT_VENC_CUR_CHROMA>, 1466 <&iommu M4U_PORT_VENC_REF_LUMA>, 1467 <&iommu M4U_PORT_VENC_REF_CHROMA>, 1468 <&iommu M4U_PORT_VENC_NBM_RDMA>, 1469 <&iommu M4U_PORT_VENC_NBM_WDMA>; 1470 mediatek,vpu = <&vpu>; 1471 clocks = <&topckgen CLK_TOP_VENC_SEL>; 1472 clock-names = "venc_sel"; 1473 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; 1474 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>; 1475 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 1476 }; 1477 1478 jpegdec: jpegdec@18004000 { 1479 compatible = "mediatek,mt8173-jpgdec"; 1480 reg = <0 0x18004000 0 0x1000>; 1481 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW>; 1482 clocks = <&vencsys CLK_VENC_CKE0>, 1483 <&vencsys CLK_VENC_CKE3>; 1484 clock-names = "jpgdec-smi", 1485 "jpgdec"; 1486 power-domains = <&spm MT8173_POWER_DOMAIN_VENC>; 1487 iommus = <&iommu M4U_PORT_JPGDEC_WDMA>, 1488 <&iommu M4U_PORT_JPGDEC_BSDMA>; 1489 }; 1490 1491 vencltsys: clock-controller@19000000 { 1492 compatible = "mediatek,mt8173-vencltsys", "syscon"; 1493 reg = <0 0x19000000 0 0x1000>; 1494 #clock-cells = <1>; 1495 }; 1496 1497 larb5: larb@19001000 { 1498 compatible = "mediatek,mt8173-smi-larb"; 1499 reg = <0 0x19001000 0 0x1000>; 1500 mediatek,smi = <&smi_common>; 1501 power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>; 1502 clocks = <&vencltsys CLK_VENCLT_CKE1>, 1503 <&vencltsys CLK_VENCLT_CKE0>; 1504 clock-names = "apb", "smi"; 1505 }; 1506 1507 vcodec_enc_vp8: vcodec@19002000 { 1508 compatible = "mediatek,mt8173-vcodec-enc-vp8"; 1509 reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ 1510 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; 1511 iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>, 1512 <&iommu M4U_PORT_VENC_REC_FRM_SET2>, 1513 <&iommu M4U_PORT_VENC_BSDMA_SET2>, 1514 <&iommu M4U_PORT_VENC_SV_COMA_SET2>, 1515 <&iommu M4U_PORT_VENC_RD_COMA_SET2>, 1516 <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, 1517 <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, 1518 <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, 1519 <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; 1520 mediatek,vpu = <&vpu>; 1521 clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; 1522 clock-names = "venc_lt_sel"; 1523 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; 1524 assigned-clock-parents = 1525 <&topckgen CLK_TOP_VCODECPLL_370P5>; 1526 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; 1527 }; 1528 }; 1529}; 1530