1/* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Eddie Huang <eddie.huang@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/clock/mt8173-clk.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/memory/mt8173-larb-port.h> 18#include <dt-bindings/phy/phy.h> 19#include <dt-bindings/power/mt8173-power.h> 20#include <dt-bindings/reset/mt8173-resets.h> 21#include "mt8173-pinfunc.h" 22 23/ { 24 compatible = "mediatek,mt8173"; 25 interrupt-parent = <&sysirq>; 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu-map { 34 cluster0 { 35 core0 { 36 cpu = <&cpu0>; 37 }; 38 core1 { 39 cpu = <&cpu1>; 40 }; 41 }; 42 43 cluster1 { 44 core0 { 45 cpu = <&cpu2>; 46 }; 47 core1 { 48 cpu = <&cpu3>; 49 }; 50 }; 51 }; 52 53 cpu0: cpu@0 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a53"; 56 reg = <0x000>; 57 enable-method = "psci"; 58 cpu-idle-states = <&CPU_SLEEP_0>; 59 }; 60 61 cpu1: cpu@1 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a53"; 64 reg = <0x001>; 65 enable-method = "psci"; 66 cpu-idle-states = <&CPU_SLEEP_0>; 67 }; 68 69 cpu2: cpu@100 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a57"; 72 reg = <0x100>; 73 enable-method = "psci"; 74 cpu-idle-states = <&CPU_SLEEP_0>; 75 }; 76 77 cpu3: cpu@101 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a57"; 80 reg = <0x101>; 81 enable-method = "psci"; 82 cpu-idle-states = <&CPU_SLEEP_0>; 83 }; 84 85 idle-states { 86 entry-method = "psci"; 87 88 CPU_SLEEP_0: cpu-sleep-0 { 89 compatible = "arm,idle-state"; 90 local-timer-stop; 91 entry-latency-us = <639>; 92 exit-latency-us = <680>; 93 min-residency-us = <1088>; 94 arm,psci-suspend-param = <0x0010000>; 95 }; 96 }; 97 }; 98 99 psci { 100 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 101 method = "smc"; 102 cpu_suspend = <0x84000001>; 103 cpu_off = <0x84000002>; 104 cpu_on = <0x84000003>; 105 }; 106 107 clk26m: oscillator@0 { 108 compatible = "fixed-clock"; 109 #clock-cells = <0>; 110 clock-frequency = <26000000>; 111 clock-output-names = "clk26m"; 112 }; 113 114 clk32k: oscillator@1 { 115 compatible = "fixed-clock"; 116 #clock-cells = <0>; 117 clock-frequency = <32000>; 118 clock-output-names = "clk32k"; 119 }; 120 121 cpum_ck: oscillator@2 { 122 compatible = "fixed-clock"; 123 #clock-cells = <0>; 124 clock-frequency = <0>; 125 clock-output-names = "cpum_ck"; 126 }; 127 128 timer { 129 compatible = "arm,armv8-timer"; 130 interrupt-parent = <&gic>; 131 interrupts = <GIC_PPI 13 132 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 133 <GIC_PPI 14 134 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 135 <GIC_PPI 11 136 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 137 <GIC_PPI 10 138 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 139 }; 140 141 soc { 142 #address-cells = <2>; 143 #size-cells = <2>; 144 compatible = "simple-bus"; 145 ranges; 146 147 topckgen: clock-controller@10000000 { 148 compatible = "mediatek,mt8173-topckgen"; 149 reg = <0 0x10000000 0 0x1000>; 150 #clock-cells = <1>; 151 }; 152 153 infracfg: power-controller@10001000 { 154 compatible = "mediatek,mt8173-infracfg", "syscon"; 155 reg = <0 0x10001000 0 0x1000>; 156 #clock-cells = <1>; 157 #reset-cells = <1>; 158 }; 159 160 pericfg: power-controller@10003000 { 161 compatible = "mediatek,mt8173-pericfg", "syscon"; 162 reg = <0 0x10003000 0 0x1000>; 163 #clock-cells = <1>; 164 #reset-cells = <1>; 165 }; 166 167 syscfg_pctl_a: syscfg_pctl_a@10005000 { 168 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 169 reg = <0 0x10005000 0 0x1000>; 170 }; 171 172 pio: pinctrl@0x10005000 { 173 compatible = "mediatek,mt8173-pinctrl"; 174 reg = <0 0x1000b000 0 0x1000>; 175 mediatek,pctl-regmap = <&syscfg_pctl_a>; 176 pins-are-numbered; 177 gpio-controller; 178 #gpio-cells = <2>; 179 interrupt-controller; 180 #interrupt-cells = <2>; 181 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 184 185 i2c0_pins_a: i2c0 { 186 pins1 { 187 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 188 <MT8173_PIN_46_SCL0__FUNC_SCL0>; 189 bias-disable; 190 }; 191 }; 192 193 i2c1_pins_a: i2c1 { 194 pins1 { 195 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 196 <MT8173_PIN_126_SCL1__FUNC_SCL1>; 197 bias-disable; 198 }; 199 }; 200 201 i2c2_pins_a: i2c2 { 202 pins1 { 203 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 204 <MT8173_PIN_44_SCL2__FUNC_SCL2>; 205 bias-disable; 206 }; 207 }; 208 209 i2c3_pins_a: i2c3 { 210 pins1 { 211 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 212 <MT8173_PIN_107_SCL3__FUNC_SCL3>; 213 bias-disable; 214 }; 215 }; 216 217 i2c4_pins_a: i2c4 { 218 pins1 { 219 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 220 <MT8173_PIN_134_SCL4__FUNC_SCL4>; 221 bias-disable; 222 }; 223 }; 224 225 i2c6_pins_a: i2c6 { 226 pins1 { 227 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 228 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 229 bias-disable; 230 }; 231 }; 232 }; 233 234 scpsys: scpsys@10006000 { 235 compatible = "mediatek,mt8173-scpsys"; 236 #power-domain-cells = <1>; 237 reg = <0 0x10006000 0 0x1000>; 238 clocks = <&clk26m>, 239 <&topckgen CLK_TOP_MM_SEL>, 240 <&topckgen CLK_TOP_VENC_SEL>, 241 <&topckgen CLK_TOP_VENC_LT_SEL>; 242 clock-names = "mfg", "mm", "venc", "venc_lt"; 243 infracfg = <&infracfg>; 244 }; 245 246 watchdog: watchdog@10007000 { 247 compatible = "mediatek,mt8173-wdt", 248 "mediatek,mt6589-wdt"; 249 reg = <0 0x10007000 0 0x100>; 250 }; 251 252 timer: timer@10008000 { 253 compatible = "mediatek,mt8173-timer", 254 "mediatek,mt6577-timer"; 255 reg = <0 0x10008000 0 0x1000>; 256 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 257 clocks = <&infracfg CLK_INFRA_CLK_13M>, 258 <&topckgen CLK_TOP_RTC_SEL>; 259 }; 260 261 pwrap: pwrap@1000d000 { 262 compatible = "mediatek,mt8173-pwrap"; 263 reg = <0 0x1000d000 0 0x1000>; 264 reg-names = "pwrap"; 265 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 266 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 267 reset-names = "pwrap"; 268 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 269 clock-names = "spi", "wrap"; 270 }; 271 272 sysirq: intpol-controller@10200620 { 273 compatible = "mediatek,mt8173-sysirq", 274 "mediatek,mt6577-sysirq"; 275 interrupt-controller; 276 #interrupt-cells = <3>; 277 interrupt-parent = <&gic>; 278 reg = <0 0x10200620 0 0x20>; 279 }; 280 281 iommu: iommu@10205000 { 282 compatible = "mediatek,mt8173-m4u"; 283 reg = <0 0x10205000 0 0x1000>; 284 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 285 clocks = <&infracfg CLK_INFRA_M4U>; 286 clock-names = "bclk"; 287 mediatek,larbs = <&larb0 &larb1 &larb2 288 &larb3 &larb4 &larb5>; 289 #iommu-cells = <1>; 290 }; 291 292 efuse: efuse@10206000 { 293 compatible = "mediatek,mt8173-efuse"; 294 reg = <0 0x10206000 0 0x1000>; 295 }; 296 297 apmixedsys: clock-controller@10209000 { 298 compatible = "mediatek,mt8173-apmixedsys"; 299 reg = <0 0x10209000 0 0x1000>; 300 #clock-cells = <1>; 301 }; 302 303 gic: interrupt-controller@10220000 { 304 compatible = "arm,gic-400"; 305 #interrupt-cells = <3>; 306 interrupt-parent = <&gic>; 307 interrupt-controller; 308 reg = <0 0x10221000 0 0x1000>, 309 <0 0x10222000 0 0x2000>, 310 <0 0x10224000 0 0x2000>, 311 <0 0x10226000 0 0x2000>; 312 interrupts = <GIC_PPI 9 313 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 314 }; 315 316 auxadc: auxadc@11001000 { 317 compatible = "mediatek,mt8173-auxadc"; 318 reg = <0 0x11001000 0 0x1000>; 319 }; 320 321 uart0: serial@11002000 { 322 compatible = "mediatek,mt8173-uart", 323 "mediatek,mt6577-uart"; 324 reg = <0 0x11002000 0 0x400>; 325 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 326 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 327 clock-names = "baud", "bus"; 328 status = "disabled"; 329 }; 330 331 uart1: serial@11003000 { 332 compatible = "mediatek,mt8173-uart", 333 "mediatek,mt6577-uart"; 334 reg = <0 0x11003000 0 0x400>; 335 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 336 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 337 clock-names = "baud", "bus"; 338 status = "disabled"; 339 }; 340 341 uart2: serial@11004000 { 342 compatible = "mediatek,mt8173-uart", 343 "mediatek,mt6577-uart"; 344 reg = <0 0x11004000 0 0x400>; 345 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 346 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 347 clock-names = "baud", "bus"; 348 status = "disabled"; 349 }; 350 351 uart3: serial@11005000 { 352 compatible = "mediatek,mt8173-uart", 353 "mediatek,mt6577-uart"; 354 reg = <0 0x11005000 0 0x400>; 355 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 356 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 357 clock-names = "baud", "bus"; 358 status = "disabled"; 359 }; 360 361 i2c0: i2c@11007000 { 362 compatible = "mediatek,mt8173-i2c"; 363 reg = <0 0x11007000 0 0x70>, 364 <0 0x11000100 0 0x80>; 365 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 366 clock-div = <16>; 367 clocks = <&pericfg CLK_PERI_I2C0>, 368 <&pericfg CLK_PERI_AP_DMA>; 369 clock-names = "main", "dma"; 370 pinctrl-names = "default"; 371 pinctrl-0 = <&i2c0_pins_a>; 372 #address-cells = <1>; 373 #size-cells = <0>; 374 status = "disabled"; 375 }; 376 377 i2c1: i2c@11008000 { 378 compatible = "mediatek,mt8173-i2c"; 379 reg = <0 0x11008000 0 0x70>, 380 <0 0x11000180 0 0x80>; 381 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 382 clock-div = <16>; 383 clocks = <&pericfg CLK_PERI_I2C1>, 384 <&pericfg CLK_PERI_AP_DMA>; 385 clock-names = "main", "dma"; 386 pinctrl-names = "default"; 387 pinctrl-0 = <&i2c1_pins_a>; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 status = "disabled"; 391 }; 392 393 i2c2: i2c@11009000 { 394 compatible = "mediatek,mt8173-i2c"; 395 reg = <0 0x11009000 0 0x70>, 396 <0 0x11000200 0 0x80>; 397 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 398 clock-div = <16>; 399 clocks = <&pericfg CLK_PERI_I2C2>, 400 <&pericfg CLK_PERI_AP_DMA>; 401 clock-names = "main", "dma"; 402 pinctrl-names = "default"; 403 pinctrl-0 = <&i2c2_pins_a>; 404 #address-cells = <1>; 405 #size-cells = <0>; 406 status = "disabled"; 407 }; 408 409 spi: spi@1100a000 { 410 compatible = "mediatek,mt8173-spi"; 411 #address-cells = <1>; 412 #size-cells = <0>; 413 reg = <0 0x1100a000 0 0x1000>; 414 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 415 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 416 <&topckgen CLK_TOP_SPI_SEL>, 417 <&pericfg CLK_PERI_SPI0>; 418 clock-names = "parent-clk", "sel-clk", "spi-clk"; 419 status = "disabled"; 420 }; 421 422 thermal: thermal@1100b000 { 423 #thermal-sensor-cells = <0>; 424 compatible = "mediatek,mt8173-thermal"; 425 reg = <0 0x1100b000 0 0x1000>; 426 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 427 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 428 clock-names = "therm", "auxadc"; 429 resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 430 mediatek,auxadc = <&auxadc>; 431 mediatek,apmixedsys = <&apmixedsys>; 432 }; 433 434 nor_flash: spi@1100d000 { 435 compatible = "mediatek,mt8173-nor"; 436 reg = <0 0x1100d000 0 0xe0>; 437 clocks = <&pericfg CLK_PERI_SPI>, 438 <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 439 clock-names = "spi", "sf"; 440 #address-cells = <1>; 441 #size-cells = <0>; 442 status = "disabled"; 443 }; 444 445 i2c3: i2c@11010000 { 446 compatible = "mediatek,mt8173-i2c"; 447 reg = <0 0x11010000 0 0x70>, 448 <0 0x11000280 0 0x80>; 449 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 450 clock-div = <16>; 451 clocks = <&pericfg CLK_PERI_I2C3>, 452 <&pericfg CLK_PERI_AP_DMA>; 453 clock-names = "main", "dma"; 454 pinctrl-names = "default"; 455 pinctrl-0 = <&i2c3_pins_a>; 456 #address-cells = <1>; 457 #size-cells = <0>; 458 status = "disabled"; 459 }; 460 461 i2c4: i2c@11011000 { 462 compatible = "mediatek,mt8173-i2c"; 463 reg = <0 0x11011000 0 0x70>, 464 <0 0x11000300 0 0x80>; 465 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 466 clock-div = <16>; 467 clocks = <&pericfg CLK_PERI_I2C4>, 468 <&pericfg CLK_PERI_AP_DMA>; 469 clock-names = "main", "dma"; 470 pinctrl-names = "default"; 471 pinctrl-0 = <&i2c4_pins_a>; 472 #address-cells = <1>; 473 #size-cells = <0>; 474 status = "disabled"; 475 }; 476 477 i2c6: i2c@11013000 { 478 compatible = "mediatek,mt8173-i2c"; 479 reg = <0 0x11013000 0 0x70>, 480 <0 0x11000080 0 0x80>; 481 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 482 clock-div = <16>; 483 clocks = <&pericfg CLK_PERI_I2C6>, 484 <&pericfg CLK_PERI_AP_DMA>; 485 clock-names = "main", "dma"; 486 pinctrl-names = "default"; 487 pinctrl-0 = <&i2c6_pins_a>; 488 #address-cells = <1>; 489 #size-cells = <0>; 490 status = "disabled"; 491 }; 492 493 afe: audio-controller@11220000 { 494 compatible = "mediatek,mt8173-afe-pcm"; 495 reg = <0 0x11220000 0 0x1000>; 496 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 497 power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; 498 clocks = <&infracfg CLK_INFRA_AUDIO>, 499 <&topckgen CLK_TOP_AUDIO_SEL>, 500 <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 501 <&topckgen CLK_TOP_APLL1_DIV0>, 502 <&topckgen CLK_TOP_APLL2_DIV0>, 503 <&topckgen CLK_TOP_I2S0_M_SEL>, 504 <&topckgen CLK_TOP_I2S1_M_SEL>, 505 <&topckgen CLK_TOP_I2S2_M_SEL>, 506 <&topckgen CLK_TOP_I2S3_M_SEL>, 507 <&topckgen CLK_TOP_I2S3_B_SEL>; 508 clock-names = "infra_sys_audio_clk", 509 "top_pdn_audio", 510 "top_pdn_aud_intbus", 511 "bck0", 512 "bck1", 513 "i2s0_m", 514 "i2s1_m", 515 "i2s2_m", 516 "i2s3_m", 517 "i2s3_b"; 518 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 519 <&topckgen CLK_TOP_AUD_2_SEL>; 520 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 521 <&topckgen CLK_TOP_APLL2>; 522 }; 523 524 mmc0: mmc@11230000 { 525 compatible = "mediatek,mt8173-mmc", 526 "mediatek,mt8135-mmc"; 527 reg = <0 0x11230000 0 0x1000>; 528 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 529 clocks = <&pericfg CLK_PERI_MSDC30_0>, 530 <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 531 clock-names = "source", "hclk"; 532 status = "disabled"; 533 }; 534 535 mmc1: mmc@11240000 { 536 compatible = "mediatek,mt8173-mmc", 537 "mediatek,mt8135-mmc"; 538 reg = <0 0x11240000 0 0x1000>; 539 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 540 clocks = <&pericfg CLK_PERI_MSDC30_1>, 541 <&topckgen CLK_TOP_AXI_SEL>; 542 clock-names = "source", "hclk"; 543 status = "disabled"; 544 }; 545 546 mmc2: mmc@11250000 { 547 compatible = "mediatek,mt8173-mmc", 548 "mediatek,mt8135-mmc"; 549 reg = <0 0x11250000 0 0x1000>; 550 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 551 clocks = <&pericfg CLK_PERI_MSDC30_2>, 552 <&topckgen CLK_TOP_AXI_SEL>; 553 clock-names = "source", "hclk"; 554 status = "disabled"; 555 }; 556 557 mmc3: mmc@11260000 { 558 compatible = "mediatek,mt8173-mmc", 559 "mediatek,mt8135-mmc"; 560 reg = <0 0x11260000 0 0x1000>; 561 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 562 clocks = <&pericfg CLK_PERI_MSDC30_3>, 563 <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 564 clock-names = "source", "hclk"; 565 status = "disabled"; 566 }; 567 568 usb30: usb@11270000 { 569 compatible = "mediatek,mt8173-xhci"; 570 reg = <0 0x11270000 0 0x1000>, 571 <0 0x11280700 0 0x0100>; 572 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 573 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 574 clocks = <&topckgen CLK_TOP_USB30_SEL>, 575 <&pericfg CLK_PERI_USB0>, 576 <&pericfg CLK_PERI_USB1>; 577 clock-names = "sys_ck", 578 "wakeup_deb_p0", 579 "wakeup_deb_p1"; 580 phys = <&phy_port0 PHY_TYPE_USB3>, 581 <&phy_port1 PHY_TYPE_USB2>; 582 mediatek,syscon-wakeup = <&pericfg>; 583 status = "okay"; 584 }; 585 586 u3phy: usb-phy@11290000 { 587 compatible = "mediatek,mt8173-u3phy"; 588 reg = <0 0x11290000 0 0x800>; 589 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 590 clock-names = "u3phya_ref"; 591 #address-cells = <2>; 592 #size-cells = <2>; 593 ranges; 594 status = "okay"; 595 596 phy_port0: port@11290800 { 597 reg = <0 0x11290800 0 0x800>; 598 #phy-cells = <1>; 599 status = "okay"; 600 }; 601 602 phy_port1: port@11291000 { 603 reg = <0 0x11291000 0 0x800>; 604 #phy-cells = <1>; 605 status = "okay"; 606 }; 607 }; 608 609 mmsys: clock-controller@14000000 { 610 compatible = "mediatek,mt8173-mmsys", "syscon"; 611 reg = <0 0x14000000 0 0x1000>; 612 #clock-cells = <1>; 613 }; 614 615 pwm0: pwm@1401e000 { 616 compatible = "mediatek,mt8173-disp-pwm", 617 "mediatek,mt6595-disp-pwm"; 618 reg = <0 0x1401e000 0 0x1000>; 619 #pwm-cells = <2>; 620 clocks = <&mmsys CLK_MM_DISP_PWM026M>, 621 <&mmsys CLK_MM_DISP_PWM0MM>; 622 clock-names = "main", "mm"; 623 status = "disabled"; 624 }; 625 626 pwm1: pwm@1401f000 { 627 compatible = "mediatek,mt8173-disp-pwm", 628 "mediatek,mt6595-disp-pwm"; 629 reg = <0 0x1401f000 0 0x1000>; 630 #pwm-cells = <2>; 631 clocks = <&mmsys CLK_MM_DISP_PWM126M>, 632 <&mmsys CLK_MM_DISP_PWM1MM>; 633 clock-names = "main", "mm"; 634 status = "disabled"; 635 }; 636 637 larb0: larb@14021000 { 638 compatible = "mediatek,mt8173-smi-larb"; 639 reg = <0 0x14021000 0 0x1000>; 640 mediatek,smi = <&smi_common>; 641 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 642 clocks = <&mmsys CLK_MM_SMI_LARB0>, 643 <&mmsys CLK_MM_SMI_LARB0>; 644 clock-names = "apb", "smi"; 645 }; 646 647 smi_common: smi@14022000 { 648 compatible = "mediatek,mt8173-smi-common"; 649 reg = <0 0x14022000 0 0x1000>; 650 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 651 clocks = <&mmsys CLK_MM_SMI_COMMON>, 652 <&mmsys CLK_MM_SMI_COMMON>; 653 clock-names = "apb", "smi"; 654 }; 655 656 larb4: larb@14027000 { 657 compatible = "mediatek,mt8173-smi-larb"; 658 reg = <0 0x14027000 0 0x1000>; 659 mediatek,smi = <&smi_common>; 660 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 661 clocks = <&mmsys CLK_MM_SMI_LARB4>, 662 <&mmsys CLK_MM_SMI_LARB4>; 663 clock-names = "apb", "smi"; 664 }; 665 666 imgsys: clock-controller@15000000 { 667 compatible = "mediatek,mt8173-imgsys", "syscon"; 668 reg = <0 0x15000000 0 0x1000>; 669 #clock-cells = <1>; 670 }; 671 672 larb2: larb@15001000 { 673 compatible = "mediatek,mt8173-smi-larb"; 674 reg = <0 0x15001000 0 0x1000>; 675 mediatek,smi = <&smi_common>; 676 power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>; 677 clocks = <&imgsys CLK_IMG_LARB2_SMI>, 678 <&imgsys CLK_IMG_LARB2_SMI>; 679 clock-names = "apb", "smi"; 680 }; 681 682 vdecsys: clock-controller@16000000 { 683 compatible = "mediatek,mt8173-vdecsys", "syscon"; 684 reg = <0 0x16000000 0 0x1000>; 685 #clock-cells = <1>; 686 }; 687 688 larb1: larb@16010000 { 689 compatible = "mediatek,mt8173-smi-larb"; 690 reg = <0 0x16010000 0 0x1000>; 691 mediatek,smi = <&smi_common>; 692 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 693 clocks = <&vdecsys CLK_VDEC_CKEN>, 694 <&vdecsys CLK_VDEC_LARB_CKEN>; 695 clock-names = "apb", "smi"; 696 }; 697 698 vencsys: clock-controller@18000000 { 699 compatible = "mediatek,mt8173-vencsys", "syscon"; 700 reg = <0 0x18000000 0 0x1000>; 701 #clock-cells = <1>; 702 }; 703 704 larb3: larb@18001000 { 705 compatible = "mediatek,mt8173-smi-larb"; 706 reg = <0 0x18001000 0 0x1000>; 707 mediatek,smi = <&smi_common>; 708 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 709 clocks = <&vencsys CLK_VENC_CKE1>, 710 <&vencsys CLK_VENC_CKE0>; 711 clock-names = "apb", "smi"; 712 }; 713 714 vencltsys: clock-controller@19000000 { 715 compatible = "mediatek,mt8173-vencltsys", "syscon"; 716 reg = <0 0x19000000 0 0x1000>; 717 #clock-cells = <1>; 718 }; 719 720 larb5: larb@19001000 { 721 compatible = "mediatek,mt8173-smi-larb"; 722 reg = <0 0x19001000 0 0x1000>; 723 mediatek,smi = <&smi_common>; 724 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; 725 clocks = <&vencltsys CLK_VENCLT_CKE1>, 726 <&vencltsys CLK_VENCLT_CKE0>; 727 clock-names = "apb", "smi"; 728 }; 729 }; 730}; 731 732