1/* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Eddie Huang <eddie.huang@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/clock/mt8173-clk.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/phy/phy.h> 18#include <dt-bindings/power/mt8173-power.h> 19#include <dt-bindings/reset/mt8173-resets.h> 20#include "mt8173-pinfunc.h" 21 22/ { 23 compatible = "mediatek,mt8173"; 24 interrupt-parent = <&sysirq>; 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 cpu-map { 33 cluster0 { 34 core0 { 35 cpu = <&cpu0>; 36 }; 37 core1 { 38 cpu = <&cpu1>; 39 }; 40 }; 41 42 cluster1 { 43 core0 { 44 cpu = <&cpu2>; 45 }; 46 core1 { 47 cpu = <&cpu3>; 48 }; 49 }; 50 }; 51 52 cpu0: cpu@0 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a53"; 55 reg = <0x000>; 56 enable-method = "psci"; 57 cpu-idle-states = <&CPU_SLEEP_0>; 58 }; 59 60 cpu1: cpu@1 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53"; 63 reg = <0x001>; 64 enable-method = "psci"; 65 cpu-idle-states = <&CPU_SLEEP_0>; 66 }; 67 68 cpu2: cpu@100 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a57"; 71 reg = <0x100>; 72 enable-method = "psci"; 73 cpu-idle-states = <&CPU_SLEEP_0>; 74 }; 75 76 cpu3: cpu@101 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a57"; 79 reg = <0x101>; 80 enable-method = "psci"; 81 cpu-idle-states = <&CPU_SLEEP_0>; 82 }; 83 84 idle-states { 85 entry-method = "psci"; 86 87 CPU_SLEEP_0: cpu-sleep-0 { 88 compatible = "arm,idle-state"; 89 local-timer-stop; 90 entry-latency-us = <639>; 91 exit-latency-us = <680>; 92 min-residency-us = <1088>; 93 arm,psci-suspend-param = <0x0010000>; 94 }; 95 }; 96 }; 97 98 psci { 99 compatible = "arm,psci"; 100 method = "smc"; 101 cpu_suspend = <0x84000001>; 102 cpu_off = <0x84000002>; 103 cpu_on = <0x84000003>; 104 }; 105 106 clk26m: oscillator@0 { 107 compatible = "fixed-clock"; 108 #clock-cells = <0>; 109 clock-frequency = <26000000>; 110 clock-output-names = "clk26m"; 111 }; 112 113 clk32k: oscillator@1 { 114 compatible = "fixed-clock"; 115 #clock-cells = <0>; 116 clock-frequency = <32000>; 117 clock-output-names = "clk32k"; 118 }; 119 120 cpum_ck: oscillator@2 { 121 compatible = "fixed-clock"; 122 #clock-cells = <0>; 123 clock-frequency = <0>; 124 clock-output-names = "cpum_ck"; 125 }; 126 127 timer { 128 compatible = "arm,armv8-timer"; 129 interrupt-parent = <&gic>; 130 interrupts = <GIC_PPI 13 131 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 132 <GIC_PPI 14 133 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 134 <GIC_PPI 11 135 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 136 <GIC_PPI 10 137 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 138 }; 139 140 soc { 141 #address-cells = <2>; 142 #size-cells = <2>; 143 compatible = "simple-bus"; 144 ranges; 145 146 topckgen: clock-controller@10000000 { 147 compatible = "mediatek,mt8173-topckgen"; 148 reg = <0 0x10000000 0 0x1000>; 149 #clock-cells = <1>; 150 }; 151 152 infracfg: power-controller@10001000 { 153 compatible = "mediatek,mt8173-infracfg", "syscon"; 154 reg = <0 0x10001000 0 0x1000>; 155 #clock-cells = <1>; 156 #reset-cells = <1>; 157 }; 158 159 pericfg: power-controller@10003000 { 160 compatible = "mediatek,mt8173-pericfg", "syscon"; 161 reg = <0 0x10003000 0 0x1000>; 162 #clock-cells = <1>; 163 #reset-cells = <1>; 164 }; 165 166 syscfg_pctl_a: syscfg_pctl_a@10005000 { 167 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 168 reg = <0 0x10005000 0 0x1000>; 169 }; 170 171 pio: pinctrl@0x10005000 { 172 compatible = "mediatek,mt8173-pinctrl"; 173 reg = <0 0x1000b000 0 0x1000>; 174 mediatek,pctl-regmap = <&syscfg_pctl_a>; 175 pins-are-numbered; 176 gpio-controller; 177 #gpio-cells = <2>; 178 interrupt-controller; 179 #interrupt-cells = <2>; 180 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 183 184 i2c0_pins_a: i2c0 { 185 pins1 { 186 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 187 <MT8173_PIN_46_SCL0__FUNC_SCL0>; 188 bias-disable; 189 }; 190 }; 191 192 i2c1_pins_a: i2c1 { 193 pins1 { 194 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 195 <MT8173_PIN_126_SCL1__FUNC_SCL1>; 196 bias-disable; 197 }; 198 }; 199 200 i2c2_pins_a: i2c2 { 201 pins1 { 202 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 203 <MT8173_PIN_44_SCL2__FUNC_SCL2>; 204 bias-disable; 205 }; 206 }; 207 208 i2c3_pins_a: i2c3 { 209 pins1 { 210 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 211 <MT8173_PIN_107_SCL3__FUNC_SCL3>; 212 bias-disable; 213 }; 214 }; 215 216 i2c4_pins_a: i2c4 { 217 pins1 { 218 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 219 <MT8173_PIN_134_SCL4__FUNC_SCL4>; 220 bias-disable; 221 }; 222 }; 223 224 i2c6_pins_a: i2c6 { 225 pins1 { 226 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 227 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 228 bias-disable; 229 }; 230 }; 231 }; 232 233 scpsys: scpsys@10006000 { 234 compatible = "mediatek,mt8173-scpsys"; 235 #power-domain-cells = <1>; 236 reg = <0 0x10006000 0 0x1000>; 237 clocks = <&clk26m>, 238 <&topckgen CLK_TOP_MM_SEL>, 239 <&topckgen CLK_TOP_VENC_SEL>, 240 <&topckgen CLK_TOP_VENC_LT_SEL>; 241 clock-names = "mfg", "mm", "venc", "venc_lt"; 242 infracfg = <&infracfg>; 243 }; 244 245 watchdog: watchdog@10007000 { 246 compatible = "mediatek,mt8173-wdt", 247 "mediatek,mt6589-wdt"; 248 reg = <0 0x10007000 0 0x100>; 249 }; 250 251 pwrap: pwrap@1000d000 { 252 compatible = "mediatek,mt8173-pwrap"; 253 reg = <0 0x1000d000 0 0x1000>; 254 reg-names = "pwrap"; 255 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 256 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 257 reset-names = "pwrap"; 258 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 259 clock-names = "spi", "wrap"; 260 }; 261 262 sysirq: intpol-controller@10200620 { 263 compatible = "mediatek,mt8173-sysirq", 264 "mediatek,mt6577-sysirq"; 265 interrupt-controller; 266 #interrupt-cells = <3>; 267 interrupt-parent = <&gic>; 268 reg = <0 0x10200620 0 0x20>; 269 }; 270 271 apmixedsys: clock-controller@10209000 { 272 compatible = "mediatek,mt8173-apmixedsys"; 273 reg = <0 0x10209000 0 0x1000>; 274 #clock-cells = <1>; 275 }; 276 277 gic: interrupt-controller@10220000 { 278 compatible = "arm,gic-400"; 279 #interrupt-cells = <3>; 280 interrupt-parent = <&gic>; 281 interrupt-controller; 282 reg = <0 0x10221000 0 0x1000>, 283 <0 0x10222000 0 0x2000>, 284 <0 0x10224000 0 0x2000>, 285 <0 0x10226000 0 0x2000>; 286 interrupts = <GIC_PPI 9 287 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 288 }; 289 290 uart0: serial@11002000 { 291 compatible = "mediatek,mt8173-uart", 292 "mediatek,mt6577-uart"; 293 reg = <0 0x11002000 0 0x400>; 294 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 295 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 296 clock-names = "baud", "bus"; 297 status = "disabled"; 298 }; 299 300 uart1: serial@11003000 { 301 compatible = "mediatek,mt8173-uart", 302 "mediatek,mt6577-uart"; 303 reg = <0 0x11003000 0 0x400>; 304 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 305 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 306 clock-names = "baud", "bus"; 307 status = "disabled"; 308 }; 309 310 uart2: serial@11004000 { 311 compatible = "mediatek,mt8173-uart", 312 "mediatek,mt6577-uart"; 313 reg = <0 0x11004000 0 0x400>; 314 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 315 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 316 clock-names = "baud", "bus"; 317 status = "disabled"; 318 }; 319 320 uart3: serial@11005000 { 321 compatible = "mediatek,mt8173-uart", 322 "mediatek,mt6577-uart"; 323 reg = <0 0x11005000 0 0x400>; 324 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 325 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 326 clock-names = "baud", "bus"; 327 status = "disabled"; 328 }; 329 330 i2c0: i2c@11007000 { 331 compatible = "mediatek,mt8173-i2c"; 332 reg = <0 0x11007000 0 0x70>, 333 <0 0x11000100 0 0x80>; 334 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 335 clock-div = <16>; 336 clocks = <&pericfg CLK_PERI_I2C0>, 337 <&pericfg CLK_PERI_AP_DMA>; 338 clock-names = "main", "dma"; 339 pinctrl-names = "default"; 340 pinctrl-0 = <&i2c0_pins_a>; 341 #address-cells = <1>; 342 #size-cells = <0>; 343 status = "disabled"; 344 }; 345 346 i2c1: i2c@11008000 { 347 compatible = "mediatek,mt8173-i2c"; 348 reg = <0 0x11008000 0 0x70>, 349 <0 0x11000180 0 0x80>; 350 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 351 clock-div = <16>; 352 clocks = <&pericfg CLK_PERI_I2C1>, 353 <&pericfg CLK_PERI_AP_DMA>; 354 clock-names = "main", "dma"; 355 pinctrl-names = "default"; 356 pinctrl-0 = <&i2c1_pins_a>; 357 #address-cells = <1>; 358 #size-cells = <0>; 359 status = "disabled"; 360 }; 361 362 i2c2: i2c@11009000 { 363 compatible = "mediatek,mt8173-i2c"; 364 reg = <0 0x11009000 0 0x70>, 365 <0 0x11000200 0 0x80>; 366 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 367 clock-div = <16>; 368 clocks = <&pericfg CLK_PERI_I2C2>, 369 <&pericfg CLK_PERI_AP_DMA>; 370 clock-names = "main", "dma"; 371 pinctrl-names = "default"; 372 pinctrl-0 = <&i2c2_pins_a>; 373 #address-cells = <1>; 374 #size-cells = <0>; 375 status = "disabled"; 376 }; 377 378 spi: spi@1100a000 { 379 compatible = "mediatek,mt8173-spi"; 380 #address-cells = <1>; 381 #size-cells = <0>; 382 reg = <0 0x1100a000 0 0x1000>; 383 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 384 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 385 <&topckgen CLK_TOP_SPI_SEL>, 386 <&pericfg CLK_PERI_SPI0>; 387 clock-names = "parent-clk", "sel-clk", "spi-clk"; 388 status = "disabled"; 389 }; 390 391 i2c3: i2c@11010000 { 392 compatible = "mediatek,mt8173-i2c"; 393 reg = <0 0x11010000 0 0x70>, 394 <0 0x11000280 0 0x80>; 395 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 396 clock-div = <16>; 397 clocks = <&pericfg CLK_PERI_I2C3>, 398 <&pericfg CLK_PERI_AP_DMA>; 399 clock-names = "main", "dma"; 400 pinctrl-names = "default"; 401 pinctrl-0 = <&i2c3_pins_a>; 402 #address-cells = <1>; 403 #size-cells = <0>; 404 status = "disabled"; 405 }; 406 407 i2c4: i2c@11011000 { 408 compatible = "mediatek,mt8173-i2c"; 409 reg = <0 0x11011000 0 0x70>, 410 <0 0x11000300 0 0x80>; 411 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 412 clock-div = <16>; 413 clocks = <&pericfg CLK_PERI_I2C4>, 414 <&pericfg CLK_PERI_AP_DMA>; 415 clock-names = "main", "dma"; 416 pinctrl-names = "default"; 417 pinctrl-0 = <&i2c4_pins_a>; 418 #address-cells = <1>; 419 #size-cells = <0>; 420 status = "disabled"; 421 }; 422 423 i2c6: i2c@11013000 { 424 compatible = "mediatek,mt8173-i2c"; 425 reg = <0 0x11013000 0 0x70>, 426 <0 0x11000080 0 0x80>; 427 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 428 clock-div = <16>; 429 clocks = <&pericfg CLK_PERI_I2C6>, 430 <&pericfg CLK_PERI_AP_DMA>; 431 clock-names = "main", "dma"; 432 pinctrl-names = "default"; 433 pinctrl-0 = <&i2c6_pins_a>; 434 #address-cells = <1>; 435 #size-cells = <0>; 436 status = "disabled"; 437 }; 438 439 afe: audio-controller@11220000 { 440 compatible = "mediatek,mt8173-afe-pcm"; 441 reg = <0 0x11220000 0 0x1000>; 442 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 443 power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; 444 clocks = <&infracfg CLK_INFRA_AUDIO>, 445 <&topckgen CLK_TOP_AUDIO_SEL>, 446 <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 447 <&topckgen CLK_TOP_APLL1_DIV0>, 448 <&topckgen CLK_TOP_APLL2_DIV0>, 449 <&topckgen CLK_TOP_I2S0_M_SEL>, 450 <&topckgen CLK_TOP_I2S1_M_SEL>, 451 <&topckgen CLK_TOP_I2S2_M_SEL>, 452 <&topckgen CLK_TOP_I2S3_M_SEL>, 453 <&topckgen CLK_TOP_I2S3_B_SEL>; 454 clock-names = "infra_sys_audio_clk", 455 "top_pdn_audio", 456 "top_pdn_aud_intbus", 457 "bck0", 458 "bck1", 459 "i2s0_m", 460 "i2s1_m", 461 "i2s2_m", 462 "i2s3_m", 463 "i2s3_b"; 464 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 465 <&topckgen CLK_TOP_AUD_2_SEL>; 466 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 467 <&topckgen CLK_TOP_APLL2>; 468 }; 469 470 mmc0: mmc@11230000 { 471 compatible = "mediatek,mt8173-mmc", 472 "mediatek,mt8135-mmc"; 473 reg = <0 0x11230000 0 0x1000>; 474 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 475 clocks = <&pericfg CLK_PERI_MSDC30_0>, 476 <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 477 clock-names = "source", "hclk"; 478 status = "disabled"; 479 }; 480 481 mmc1: mmc@11240000 { 482 compatible = "mediatek,mt8173-mmc", 483 "mediatek,mt8135-mmc"; 484 reg = <0 0x11240000 0 0x1000>; 485 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 486 clocks = <&pericfg CLK_PERI_MSDC30_1>, 487 <&topckgen CLK_TOP_AXI_SEL>; 488 clock-names = "source", "hclk"; 489 status = "disabled"; 490 }; 491 492 mmc2: mmc@11250000 { 493 compatible = "mediatek,mt8173-mmc", 494 "mediatek,mt8135-mmc"; 495 reg = <0 0x11250000 0 0x1000>; 496 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 497 clocks = <&pericfg CLK_PERI_MSDC30_2>, 498 <&topckgen CLK_TOP_AXI_SEL>; 499 clock-names = "source", "hclk"; 500 status = "disabled"; 501 }; 502 503 mmc3: mmc@11260000 { 504 compatible = "mediatek,mt8173-mmc", 505 "mediatek,mt8135-mmc"; 506 reg = <0 0x11260000 0 0x1000>; 507 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 508 clocks = <&pericfg CLK_PERI_MSDC30_3>, 509 <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 510 clock-names = "source", "hclk"; 511 status = "disabled"; 512 }; 513 514 usb30: usb@11270000 { 515 compatible = "mediatek,mt8173-xhci"; 516 reg = <0 0x11270000 0 0x1000>, 517 <0 0x11280700 0 0x0100>; 518 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 519 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 520 clocks = <&topckgen CLK_TOP_USB30_SEL>, 521 <&pericfg CLK_PERI_USB0>, 522 <&pericfg CLK_PERI_USB1>; 523 clock-names = "sys_ck", 524 "wakeup_deb_p0", 525 "wakeup_deb_p1"; 526 phys = <&phy_port0 PHY_TYPE_USB3>, 527 <&phy_port1 PHY_TYPE_USB2>; 528 mediatek,syscon-wakeup = <&pericfg>; 529 status = "okay"; 530 }; 531 532 u3phy: usb-phy@11290000 { 533 compatible = "mediatek,mt8173-u3phy"; 534 reg = <0 0x11290000 0 0x800>; 535 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 536 clock-names = "u3phya_ref"; 537 #address-cells = <2>; 538 #size-cells = <2>; 539 ranges; 540 status = "okay"; 541 542 phy_port0: port@11290800 { 543 reg = <0 0x11290800 0 0x800>; 544 #phy-cells = <1>; 545 status = "okay"; 546 }; 547 548 phy_port1: port@11291000 { 549 reg = <0 0x11291000 0 0x800>; 550 #phy-cells = <1>; 551 status = "okay"; 552 }; 553 }; 554 555 mmsys: clock-controller@14000000 { 556 compatible = "mediatek,mt8173-mmsys", "syscon"; 557 reg = <0 0x14000000 0 0x1000>; 558 #clock-cells = <1>; 559 }; 560 561 imgsys: clock-controller@15000000 { 562 compatible = "mediatek,mt8173-imgsys", "syscon"; 563 reg = <0 0x15000000 0 0x1000>; 564 #clock-cells = <1>; 565 }; 566 567 vdecsys: clock-controller@16000000 { 568 compatible = "mediatek,mt8173-vdecsys", "syscon"; 569 reg = <0 0x16000000 0 0x1000>; 570 #clock-cells = <1>; 571 }; 572 573 vencsys: clock-controller@18000000 { 574 compatible = "mediatek,mt8173-vencsys", "syscon"; 575 reg = <0 0x18000000 0 0x1000>; 576 #clock-cells = <1>; 577 }; 578 579 vencltsys: clock-controller@19000000 { 580 compatible = "mediatek,mt8173-vencltsys", "syscon"; 581 reg = <0 0x19000000 0 0x1000>; 582 #clock-cells = <1>; 583 }; 584 }; 585}; 586 587