1/* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Eddie Huang <eddie.huang@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/clock/mt8173-clk.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/memory/mt8173-larb-port.h> 18#include <dt-bindings/phy/phy.h> 19#include <dt-bindings/power/mt8173-power.h> 20#include <dt-bindings/reset/mt8173-resets.h> 21#include <dt-bindings/gce/mt8173-gce.h> 22#include "mt8173-pinfunc.h" 23 24/ { 25 compatible = "mediatek,mt8173"; 26 interrupt-parent = <&sysirq>; 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 aliases { 31 ovl0 = &ovl0; 32 ovl1 = &ovl1; 33 rdma0 = &rdma0; 34 rdma1 = &rdma1; 35 rdma2 = &rdma2; 36 wdma0 = &wdma0; 37 wdma1 = &wdma1; 38 color0 = &color0; 39 color1 = &color1; 40 split0 = &split0; 41 split1 = &split1; 42 dpi0 = &dpi0; 43 dsi0 = &dsi0; 44 dsi1 = &dsi1; 45 mdp_rdma0 = &mdp_rdma0; 46 mdp_rdma1 = &mdp_rdma1; 47 mdp_rsz0 = &mdp_rsz0; 48 mdp_rsz1 = &mdp_rsz1; 49 mdp_rsz2 = &mdp_rsz2; 50 mdp_wdma0 = &mdp_wdma0; 51 mdp_wrot0 = &mdp_wrot0; 52 mdp_wrot1 = &mdp_wrot1; 53 serial0 = &uart0; 54 serial1 = &uart1; 55 serial2 = &uart2; 56 serial3 = &uart3; 57 }; 58 59 cluster0_opp: opp_table0 { 60 compatible = "operating-points-v2"; 61 opp-shared; 62 opp-507000000 { 63 opp-hz = /bits/ 64 <507000000>; 64 opp-microvolt = <859000>; 65 }; 66 opp-702000000 { 67 opp-hz = /bits/ 64 <702000000>; 68 opp-microvolt = <908000>; 69 }; 70 opp-1001000000 { 71 opp-hz = /bits/ 64 <1001000000>; 72 opp-microvolt = <983000>; 73 }; 74 opp-1105000000 { 75 opp-hz = /bits/ 64 <1105000000>; 76 opp-microvolt = <1009000>; 77 }; 78 opp-1209000000 { 79 opp-hz = /bits/ 64 <1209000000>; 80 opp-microvolt = <1034000>; 81 }; 82 opp-1300000000 { 83 opp-hz = /bits/ 64 <1300000000>; 84 opp-microvolt = <1057000>; 85 }; 86 opp-1508000000 { 87 opp-hz = /bits/ 64 <1508000000>; 88 opp-microvolt = <1109000>; 89 }; 90 opp-1703000000 { 91 opp-hz = /bits/ 64 <1703000000>; 92 opp-microvolt = <1125000>; 93 }; 94 }; 95 96 cluster1_opp: opp_table1 { 97 compatible = "operating-points-v2"; 98 opp-shared; 99 opp-507000000 { 100 opp-hz = /bits/ 64 <507000000>; 101 opp-microvolt = <828000>; 102 }; 103 opp-702000000 { 104 opp-hz = /bits/ 64 <702000000>; 105 opp-microvolt = <867000>; 106 }; 107 opp-1001000000 { 108 opp-hz = /bits/ 64 <1001000000>; 109 opp-microvolt = <927000>; 110 }; 111 opp-1209000000 { 112 opp-hz = /bits/ 64 <1209000000>; 113 opp-microvolt = <968000>; 114 }; 115 opp-1404000000 { 116 opp-hz = /bits/ 64 <1404000000>; 117 opp-microvolt = <1007000>; 118 }; 119 opp-1612000000 { 120 opp-hz = /bits/ 64 <1612000000>; 121 opp-microvolt = <1049000>; 122 }; 123 opp-1807000000 { 124 opp-hz = /bits/ 64 <1807000000>; 125 opp-microvolt = <1089000>; 126 }; 127 opp-2106000000 { 128 opp-hz = /bits/ 64 <2106000000>; 129 opp-microvolt = <1125000>; 130 }; 131 }; 132 133 cpus { 134 #address-cells = <1>; 135 #size-cells = <0>; 136 137 cpu-map { 138 cluster0 { 139 core0 { 140 cpu = <&cpu0>; 141 }; 142 core1 { 143 cpu = <&cpu1>; 144 }; 145 }; 146 147 cluster1 { 148 core0 { 149 cpu = <&cpu2>; 150 }; 151 core1 { 152 cpu = <&cpu3>; 153 }; 154 }; 155 }; 156 157 cpu0: cpu@0 { 158 device_type = "cpu"; 159 compatible = "arm,cortex-a53"; 160 reg = <0x000>; 161 enable-method = "psci"; 162 cpu-idle-states = <&CPU_SLEEP_0>; 163 #cooling-cells = <2>; 164 dynamic-power-coefficient = <263>; 165 clocks = <&infracfg CLK_INFRA_CA53SEL>, 166 <&apmixedsys CLK_APMIXED_MAINPLL>; 167 clock-names = "cpu", "intermediate"; 168 operating-points-v2 = <&cluster0_opp>; 169 }; 170 171 cpu1: cpu@1 { 172 device_type = "cpu"; 173 compatible = "arm,cortex-a53"; 174 reg = <0x001>; 175 enable-method = "psci"; 176 cpu-idle-states = <&CPU_SLEEP_0>; 177 #cooling-cells = <2>; 178 dynamic-power-coefficient = <263>; 179 clocks = <&infracfg CLK_INFRA_CA53SEL>, 180 <&apmixedsys CLK_APMIXED_MAINPLL>; 181 clock-names = "cpu", "intermediate"; 182 operating-points-v2 = <&cluster0_opp>; 183 }; 184 185 cpu2: cpu@100 { 186 device_type = "cpu"; 187 compatible = "arm,cortex-a72"; 188 reg = <0x100>; 189 enable-method = "psci"; 190 cpu-idle-states = <&CPU_SLEEP_0>; 191 #cooling-cells = <2>; 192 dynamic-power-coefficient = <530>; 193 clocks = <&infracfg CLK_INFRA_CA72SEL>, 194 <&apmixedsys CLK_APMIXED_MAINPLL>; 195 clock-names = "cpu", "intermediate"; 196 operating-points-v2 = <&cluster1_opp>; 197 }; 198 199 cpu3: cpu@101 { 200 device_type = "cpu"; 201 compatible = "arm,cortex-a72"; 202 reg = <0x101>; 203 enable-method = "psci"; 204 cpu-idle-states = <&CPU_SLEEP_0>; 205 #cooling-cells = <2>; 206 dynamic-power-coefficient = <530>; 207 clocks = <&infracfg CLK_INFRA_CA72SEL>, 208 <&apmixedsys CLK_APMIXED_MAINPLL>; 209 clock-names = "cpu", "intermediate"; 210 operating-points-v2 = <&cluster1_opp>; 211 }; 212 213 idle-states { 214 entry-method = "psci"; 215 216 CPU_SLEEP_0: cpu-sleep-0 { 217 compatible = "arm,idle-state"; 218 local-timer-stop; 219 entry-latency-us = <639>; 220 exit-latency-us = <680>; 221 min-residency-us = <1088>; 222 arm,psci-suspend-param = <0x0010000>; 223 }; 224 }; 225 }; 226 227 pmu_a53 { 228 compatible = "arm,cortex-a53-pmu"; 229 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, 230 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>; 231 interrupt-affinity = <&cpu0>, <&cpu1>; 232 }; 233 234 pmu_a72 { 235 compatible = "arm,cortex-a72-pmu"; 236 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>, 237 <GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>; 238 interrupt-affinity = <&cpu2>, <&cpu3>; 239 }; 240 241 psci { 242 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 243 method = "smc"; 244 cpu_suspend = <0x84000001>; 245 cpu_off = <0x84000002>; 246 cpu_on = <0x84000003>; 247 }; 248 249 clk26m: oscillator0 { 250 compatible = "fixed-clock"; 251 #clock-cells = <0>; 252 clock-frequency = <26000000>; 253 clock-output-names = "clk26m"; 254 }; 255 256 clk32k: oscillator1 { 257 compatible = "fixed-clock"; 258 #clock-cells = <0>; 259 clock-frequency = <32000>; 260 clock-output-names = "clk32k"; 261 }; 262 263 cpum_ck: oscillator2 { 264 compatible = "fixed-clock"; 265 #clock-cells = <0>; 266 clock-frequency = <0>; 267 clock-output-names = "cpum_ck"; 268 }; 269 270 thermal-zones { 271 cpu_thermal: cpu_thermal { 272 polling-delay-passive = <1000>; /* milliseconds */ 273 polling-delay = <1000>; /* milliseconds */ 274 275 thermal-sensors = <&thermal>; 276 sustainable-power = <1500>; /* milliwatts */ 277 278 trips { 279 threshold: trip-point0 { 280 temperature = <68000>; 281 hysteresis = <2000>; 282 type = "passive"; 283 }; 284 285 target: trip-point1 { 286 temperature = <85000>; 287 hysteresis = <2000>; 288 type = "passive"; 289 }; 290 291 cpu_crit: cpu_crit0 { 292 temperature = <115000>; 293 hysteresis = <2000>; 294 type = "critical"; 295 }; 296 }; 297 298 cooling-maps { 299 map0 { 300 trip = <&target>; 301 cooling-device = <&cpu0 0 0>, 302 <&cpu1 0 0>; 303 contribution = <3072>; 304 }; 305 map1 { 306 trip = <&target>; 307 cooling-device = <&cpu2 0 0>, 308 <&cpu3 0 0>; 309 contribution = <1024>; 310 }; 311 }; 312 }; 313 }; 314 315 reserved-memory { 316 #address-cells = <2>; 317 #size-cells = <2>; 318 ranges; 319 vpu_dma_reserved: vpu_dma_mem_region@b7000000 { 320 compatible = "shared-dma-pool"; 321 reg = <0 0xb7000000 0 0x500000>; 322 alignment = <0x1000>; 323 no-map; 324 }; 325 }; 326 327 timer { 328 compatible = "arm,armv8-timer"; 329 interrupt-parent = <&gic>; 330 interrupts = <GIC_PPI 13 331 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 332 <GIC_PPI 14 333 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 334 <GIC_PPI 11 335 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 336 <GIC_PPI 10 337 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 338 arm,no-tick-in-suspend; 339 }; 340 341 soc { 342 #address-cells = <2>; 343 #size-cells = <2>; 344 compatible = "simple-bus"; 345 ranges; 346 347 topckgen: clock-controller@10000000 { 348 compatible = "mediatek,mt8173-topckgen"; 349 reg = <0 0x10000000 0 0x1000>; 350 #clock-cells = <1>; 351 }; 352 353 infracfg: power-controller@10001000 { 354 compatible = "mediatek,mt8173-infracfg", "syscon"; 355 reg = <0 0x10001000 0 0x1000>; 356 #clock-cells = <1>; 357 #reset-cells = <1>; 358 }; 359 360 pericfg: power-controller@10003000 { 361 compatible = "mediatek,mt8173-pericfg", "syscon"; 362 reg = <0 0x10003000 0 0x1000>; 363 #clock-cells = <1>; 364 #reset-cells = <1>; 365 }; 366 367 syscfg_pctl_a: syscfg_pctl_a@10005000 { 368 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 369 reg = <0 0x10005000 0 0x1000>; 370 }; 371 372 pio: pinctrl@1000b000 { 373 compatible = "mediatek,mt8173-pinctrl"; 374 reg = <0 0x1000b000 0 0x1000>; 375 mediatek,pctl-regmap = <&syscfg_pctl_a>; 376 pins-are-numbered; 377 gpio-controller; 378 #gpio-cells = <2>; 379 interrupt-controller; 380 #interrupt-cells = <2>; 381 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 382 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 383 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 384 385 hdmi_pin: xxx { 386 387 /*hdmi htplg pin*/ 388 pins1 { 389 pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>; 390 input-enable; 391 bias-pull-down; 392 }; 393 }; 394 395 i2c0_pins_a: i2c0 { 396 pins1 { 397 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 398 <MT8173_PIN_46_SCL0__FUNC_SCL0>; 399 bias-disable; 400 }; 401 }; 402 403 i2c1_pins_a: i2c1 { 404 pins1 { 405 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 406 <MT8173_PIN_126_SCL1__FUNC_SCL1>; 407 bias-disable; 408 }; 409 }; 410 411 i2c2_pins_a: i2c2 { 412 pins1 { 413 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 414 <MT8173_PIN_44_SCL2__FUNC_SCL2>; 415 bias-disable; 416 }; 417 }; 418 419 i2c3_pins_a: i2c3 { 420 pins1 { 421 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 422 <MT8173_PIN_107_SCL3__FUNC_SCL3>; 423 bias-disable; 424 }; 425 }; 426 427 i2c4_pins_a: i2c4 { 428 pins1 { 429 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 430 <MT8173_PIN_134_SCL4__FUNC_SCL4>; 431 bias-disable; 432 }; 433 }; 434 435 i2c6_pins_a: i2c6 { 436 pins1 { 437 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 438 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 439 bias-disable; 440 }; 441 }; 442 }; 443 444 scpsys: power-controller@10006000 { 445 compatible = "mediatek,mt8173-scpsys"; 446 #power-domain-cells = <1>; 447 reg = <0 0x10006000 0 0x1000>; 448 clocks = <&clk26m>, 449 <&topckgen CLK_TOP_MM_SEL>, 450 <&topckgen CLK_TOP_VENC_SEL>, 451 <&topckgen CLK_TOP_VENC_LT_SEL>; 452 clock-names = "mfg", "mm", "venc", "venc_lt"; 453 infracfg = <&infracfg>; 454 }; 455 456 watchdog: watchdog@10007000 { 457 compatible = "mediatek,mt8173-wdt", 458 "mediatek,mt6589-wdt"; 459 reg = <0 0x10007000 0 0x100>; 460 }; 461 462 timer: timer@10008000 { 463 compatible = "mediatek,mt8173-timer", 464 "mediatek,mt6577-timer"; 465 reg = <0 0x10008000 0 0x1000>; 466 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 467 clocks = <&infracfg CLK_INFRA_CLK_13M>, 468 <&topckgen CLK_TOP_RTC_SEL>; 469 }; 470 471 pwrap: pwrap@1000d000 { 472 compatible = "mediatek,mt8173-pwrap"; 473 reg = <0 0x1000d000 0 0x1000>; 474 reg-names = "pwrap"; 475 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 476 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 477 reset-names = "pwrap"; 478 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 479 clock-names = "spi", "wrap"; 480 }; 481 482 cec: cec@10013000 { 483 compatible = "mediatek,mt8173-cec"; 484 reg = <0 0x10013000 0 0xbc>; 485 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; 486 clocks = <&infracfg CLK_INFRA_CEC>; 487 status = "disabled"; 488 }; 489 490 vpu: vpu@10020000 { 491 compatible = "mediatek,mt8173-vpu"; 492 reg = <0 0x10020000 0 0x30000>, 493 <0 0x10050000 0 0x100>; 494 reg-names = "tcm", "cfg_reg"; 495 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 496 clocks = <&topckgen CLK_TOP_SCP_SEL>; 497 clock-names = "main"; 498 memory-region = <&vpu_dma_reserved>; 499 }; 500 501 sysirq: intpol-controller@10200620 { 502 compatible = "mediatek,mt8173-sysirq", 503 "mediatek,mt6577-sysirq"; 504 interrupt-controller; 505 #interrupt-cells = <3>; 506 interrupt-parent = <&gic>; 507 reg = <0 0x10200620 0 0x20>; 508 }; 509 510 iommu: iommu@10205000 { 511 compatible = "mediatek,mt8173-m4u"; 512 reg = <0 0x10205000 0 0x1000>; 513 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 514 clocks = <&infracfg CLK_INFRA_M4U>; 515 clock-names = "bclk"; 516 mediatek,larbs = <&larb0 &larb1 &larb2 517 &larb3 &larb4 &larb5>; 518 #iommu-cells = <1>; 519 }; 520 521 efuse: efuse@10206000 { 522 compatible = "mediatek,mt8173-efuse"; 523 reg = <0 0x10206000 0 0x1000>; 524 #address-cells = <1>; 525 #size-cells = <1>; 526 thermal_calibration: calib@528 { 527 reg = <0x528 0xc>; 528 }; 529 }; 530 531 apmixedsys: clock-controller@10209000 { 532 compatible = "mediatek,mt8173-apmixedsys"; 533 reg = <0 0x10209000 0 0x1000>; 534 #clock-cells = <1>; 535 }; 536 537 hdmi_phy: hdmi-phy@10209100 { 538 compatible = "mediatek,mt8173-hdmi-phy"; 539 reg = <0 0x10209100 0 0x24>; 540 clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; 541 clock-names = "pll_ref"; 542 clock-output-names = "hdmitx_dig_cts"; 543 mediatek,ibias = <0xa>; 544 mediatek,ibias_up = <0x1c>; 545 #clock-cells = <0>; 546 #phy-cells = <0>; 547 status = "disabled"; 548 }; 549 550 gce: mailbox@10212000 { 551 compatible = "mediatek,mt8173-gce"; 552 reg = <0 0x10212000 0 0x1000>; 553 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 554 clocks = <&infracfg CLK_INFRA_GCE>; 555 clock-names = "gce"; 556 #mbox-cells = <2>; 557 }; 558 559 mipi_tx0: mipi-dphy@10215000 { 560 compatible = "mediatek,mt8173-mipi-tx"; 561 reg = <0 0x10215000 0 0x1000>; 562 clocks = <&clk26m>; 563 clock-output-names = "mipi_tx0_pll"; 564 #clock-cells = <0>; 565 #phy-cells = <0>; 566 status = "disabled"; 567 }; 568 569 mipi_tx1: mipi-dphy@10216000 { 570 compatible = "mediatek,mt8173-mipi-tx"; 571 reg = <0 0x10216000 0 0x1000>; 572 clocks = <&clk26m>; 573 clock-output-names = "mipi_tx1_pll"; 574 #clock-cells = <0>; 575 #phy-cells = <0>; 576 status = "disabled"; 577 }; 578 579 gic: interrupt-controller@10221000 { 580 compatible = "arm,gic-400"; 581 #interrupt-cells = <3>; 582 interrupt-parent = <&gic>; 583 interrupt-controller; 584 reg = <0 0x10221000 0 0x1000>, 585 <0 0x10222000 0 0x2000>, 586 <0 0x10224000 0 0x2000>, 587 <0 0x10226000 0 0x2000>; 588 interrupts = <GIC_PPI 9 589 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 590 }; 591 592 auxadc: auxadc@11001000 { 593 compatible = "mediatek,mt8173-auxadc"; 594 reg = <0 0x11001000 0 0x1000>; 595 clocks = <&pericfg CLK_PERI_AUXADC>; 596 clock-names = "main"; 597 #io-channel-cells = <1>; 598 }; 599 600 uart0: serial@11002000 { 601 compatible = "mediatek,mt8173-uart", 602 "mediatek,mt6577-uart"; 603 reg = <0 0x11002000 0 0x400>; 604 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 605 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 606 clock-names = "baud", "bus"; 607 status = "disabled"; 608 }; 609 610 uart1: serial@11003000 { 611 compatible = "mediatek,mt8173-uart", 612 "mediatek,mt6577-uart"; 613 reg = <0 0x11003000 0 0x400>; 614 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 615 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 616 clock-names = "baud", "bus"; 617 status = "disabled"; 618 }; 619 620 uart2: serial@11004000 { 621 compatible = "mediatek,mt8173-uart", 622 "mediatek,mt6577-uart"; 623 reg = <0 0x11004000 0 0x400>; 624 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 625 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 626 clock-names = "baud", "bus"; 627 status = "disabled"; 628 }; 629 630 uart3: serial@11005000 { 631 compatible = "mediatek,mt8173-uart", 632 "mediatek,mt6577-uart"; 633 reg = <0 0x11005000 0 0x400>; 634 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 635 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 636 clock-names = "baud", "bus"; 637 status = "disabled"; 638 }; 639 640 i2c0: i2c@11007000 { 641 compatible = "mediatek,mt8173-i2c"; 642 reg = <0 0x11007000 0 0x70>, 643 <0 0x11000100 0 0x80>; 644 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 645 clock-div = <16>; 646 clocks = <&pericfg CLK_PERI_I2C0>, 647 <&pericfg CLK_PERI_AP_DMA>; 648 clock-names = "main", "dma"; 649 pinctrl-names = "default"; 650 pinctrl-0 = <&i2c0_pins_a>; 651 #address-cells = <1>; 652 #size-cells = <0>; 653 status = "disabled"; 654 }; 655 656 i2c1: i2c@11008000 { 657 compatible = "mediatek,mt8173-i2c"; 658 reg = <0 0x11008000 0 0x70>, 659 <0 0x11000180 0 0x80>; 660 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 661 clock-div = <16>; 662 clocks = <&pericfg CLK_PERI_I2C1>, 663 <&pericfg CLK_PERI_AP_DMA>; 664 clock-names = "main", "dma"; 665 pinctrl-names = "default"; 666 pinctrl-0 = <&i2c1_pins_a>; 667 #address-cells = <1>; 668 #size-cells = <0>; 669 status = "disabled"; 670 }; 671 672 i2c2: i2c@11009000 { 673 compatible = "mediatek,mt8173-i2c"; 674 reg = <0 0x11009000 0 0x70>, 675 <0 0x11000200 0 0x80>; 676 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 677 clock-div = <16>; 678 clocks = <&pericfg CLK_PERI_I2C2>, 679 <&pericfg CLK_PERI_AP_DMA>; 680 clock-names = "main", "dma"; 681 pinctrl-names = "default"; 682 pinctrl-0 = <&i2c2_pins_a>; 683 #address-cells = <1>; 684 #size-cells = <0>; 685 status = "disabled"; 686 }; 687 688 spi: spi@1100a000 { 689 compatible = "mediatek,mt8173-spi"; 690 #address-cells = <1>; 691 #size-cells = <0>; 692 reg = <0 0x1100a000 0 0x1000>; 693 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 694 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 695 <&topckgen CLK_TOP_SPI_SEL>, 696 <&pericfg CLK_PERI_SPI0>; 697 clock-names = "parent-clk", "sel-clk", "spi-clk"; 698 status = "disabled"; 699 }; 700 701 thermal: thermal@1100b000 { 702 #thermal-sensor-cells = <0>; 703 compatible = "mediatek,mt8173-thermal"; 704 reg = <0 0x1100b000 0 0x1000>; 705 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 706 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 707 clock-names = "therm", "auxadc"; 708 resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 709 mediatek,auxadc = <&auxadc>; 710 mediatek,apmixedsys = <&apmixedsys>; 711 nvmem-cells = <&thermal_calibration>; 712 nvmem-cell-names = "calibration-data"; 713 }; 714 715 nor_flash: spi@1100d000 { 716 compatible = "mediatek,mt8173-nor"; 717 reg = <0 0x1100d000 0 0xe0>; 718 clocks = <&pericfg CLK_PERI_SPI>, 719 <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 720 clock-names = "spi", "sf"; 721 #address-cells = <1>; 722 #size-cells = <0>; 723 status = "disabled"; 724 }; 725 726 i2c3: i2c@11010000 { 727 compatible = "mediatek,mt8173-i2c"; 728 reg = <0 0x11010000 0 0x70>, 729 <0 0x11000280 0 0x80>; 730 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 731 clock-div = <16>; 732 clocks = <&pericfg CLK_PERI_I2C3>, 733 <&pericfg CLK_PERI_AP_DMA>; 734 clock-names = "main", "dma"; 735 pinctrl-names = "default"; 736 pinctrl-0 = <&i2c3_pins_a>; 737 #address-cells = <1>; 738 #size-cells = <0>; 739 status = "disabled"; 740 }; 741 742 i2c4: i2c@11011000 { 743 compatible = "mediatek,mt8173-i2c"; 744 reg = <0 0x11011000 0 0x70>, 745 <0 0x11000300 0 0x80>; 746 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 747 clock-div = <16>; 748 clocks = <&pericfg CLK_PERI_I2C4>, 749 <&pericfg CLK_PERI_AP_DMA>; 750 clock-names = "main", "dma"; 751 pinctrl-names = "default"; 752 pinctrl-0 = <&i2c4_pins_a>; 753 #address-cells = <1>; 754 #size-cells = <0>; 755 status = "disabled"; 756 }; 757 758 hdmiddc0: i2c@11012000 { 759 compatible = "mediatek,mt8173-hdmi-ddc"; 760 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 761 reg = <0 0x11012000 0 0x1C>; 762 clocks = <&pericfg CLK_PERI_I2C5>; 763 clock-names = "ddc-i2c"; 764 }; 765 766 i2c6: i2c@11013000 { 767 compatible = "mediatek,mt8173-i2c"; 768 reg = <0 0x11013000 0 0x70>, 769 <0 0x11000080 0 0x80>; 770 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 771 clock-div = <16>; 772 clocks = <&pericfg CLK_PERI_I2C6>, 773 <&pericfg CLK_PERI_AP_DMA>; 774 clock-names = "main", "dma"; 775 pinctrl-names = "default"; 776 pinctrl-0 = <&i2c6_pins_a>; 777 #address-cells = <1>; 778 #size-cells = <0>; 779 status = "disabled"; 780 }; 781 782 afe: audio-controller@11220000 { 783 compatible = "mediatek,mt8173-afe-pcm"; 784 reg = <0 0x11220000 0 0x1000>; 785 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 786 power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; 787 clocks = <&infracfg CLK_INFRA_AUDIO>, 788 <&topckgen CLK_TOP_AUDIO_SEL>, 789 <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 790 <&topckgen CLK_TOP_APLL1_DIV0>, 791 <&topckgen CLK_TOP_APLL2_DIV0>, 792 <&topckgen CLK_TOP_I2S0_M_SEL>, 793 <&topckgen CLK_TOP_I2S1_M_SEL>, 794 <&topckgen CLK_TOP_I2S2_M_SEL>, 795 <&topckgen CLK_TOP_I2S3_M_SEL>, 796 <&topckgen CLK_TOP_I2S3_B_SEL>; 797 clock-names = "infra_sys_audio_clk", 798 "top_pdn_audio", 799 "top_pdn_aud_intbus", 800 "bck0", 801 "bck1", 802 "i2s0_m", 803 "i2s1_m", 804 "i2s2_m", 805 "i2s3_m", 806 "i2s3_b"; 807 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 808 <&topckgen CLK_TOP_AUD_2_SEL>; 809 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 810 <&topckgen CLK_TOP_APLL2>; 811 }; 812 813 mmc0: mmc@11230000 { 814 compatible = "mediatek,mt8173-mmc"; 815 reg = <0 0x11230000 0 0x1000>; 816 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 817 clocks = <&pericfg CLK_PERI_MSDC30_0>, 818 <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 819 clock-names = "source", "hclk"; 820 status = "disabled"; 821 }; 822 823 mmc1: mmc@11240000 { 824 compatible = "mediatek,mt8173-mmc"; 825 reg = <0 0x11240000 0 0x1000>; 826 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 827 clocks = <&pericfg CLK_PERI_MSDC30_1>, 828 <&topckgen CLK_TOP_AXI_SEL>; 829 clock-names = "source", "hclk"; 830 status = "disabled"; 831 }; 832 833 mmc2: mmc@11250000 { 834 compatible = "mediatek,mt8173-mmc"; 835 reg = <0 0x11250000 0 0x1000>; 836 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 837 clocks = <&pericfg CLK_PERI_MSDC30_2>, 838 <&topckgen CLK_TOP_AXI_SEL>; 839 clock-names = "source", "hclk"; 840 status = "disabled"; 841 }; 842 843 mmc3: mmc@11260000 { 844 compatible = "mediatek,mt8173-mmc"; 845 reg = <0 0x11260000 0 0x1000>; 846 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 847 clocks = <&pericfg CLK_PERI_MSDC30_3>, 848 <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 849 clock-names = "source", "hclk"; 850 status = "disabled"; 851 }; 852 853 ssusb: usb@11271000 { 854 compatible = "mediatek,mt8173-mtu3"; 855 reg = <0 0x11271000 0 0x3000>, 856 <0 0x11280700 0 0x0100>; 857 reg-names = "mac", "ippc"; 858 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>; 859 phys = <&u2port0 PHY_TYPE_USB2>, 860 <&u3port0 PHY_TYPE_USB3>, 861 <&u2port1 PHY_TYPE_USB2>; 862 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 863 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 864 clock-names = "sys_ck", "ref_ck"; 865 mediatek,syscon-wakeup = <&pericfg 0x400 1>; 866 #address-cells = <2>; 867 #size-cells = <2>; 868 ranges; 869 status = "disabled"; 870 871 usb_host: xhci@11270000 { 872 compatible = "mediatek,mt8173-xhci"; 873 reg = <0 0x11270000 0 0x1000>; 874 reg-names = "mac"; 875 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 876 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 877 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 878 clock-names = "sys_ck", "ref_ck"; 879 status = "disabled"; 880 }; 881 }; 882 883 u3phy: usb-phy@11290000 { 884 compatible = "mediatek,mt8173-u3phy"; 885 reg = <0 0x11290000 0 0x800>; 886 #address-cells = <2>; 887 #size-cells = <2>; 888 ranges; 889 status = "okay"; 890 891 u2port0: usb-phy@11290800 { 892 reg = <0 0x11290800 0 0x100>; 893 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 894 clock-names = "ref"; 895 #phy-cells = <1>; 896 status = "okay"; 897 }; 898 899 u3port0: usb-phy@11290900 { 900 reg = <0 0x11290900 0 0x700>; 901 clocks = <&clk26m>; 902 clock-names = "ref"; 903 #phy-cells = <1>; 904 status = "okay"; 905 }; 906 907 u2port1: usb-phy@11291000 { 908 reg = <0 0x11291000 0 0x100>; 909 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 910 clock-names = "ref"; 911 #phy-cells = <1>; 912 status = "okay"; 913 }; 914 }; 915 916 mmsys: clock-controller@14000000 { 917 compatible = "mediatek,mt8173-mmsys", "syscon"; 918 reg = <0 0x14000000 0 0x1000>; 919 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 920 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; 921 assigned-clock-rates = <400000000>; 922 #clock-cells = <1>; 923 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 924 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 925 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 926 }; 927 928 mdp_rdma0: rdma@14001000 { 929 compatible = "mediatek,mt8173-mdp-rdma", 930 "mediatek,mt8173-mdp"; 931 reg = <0 0x14001000 0 0x1000>; 932 clocks = <&mmsys CLK_MM_MDP_RDMA0>, 933 <&mmsys CLK_MM_MUTEX_32K>; 934 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 935 iommus = <&iommu M4U_PORT_MDP_RDMA0>; 936 mediatek,larb = <&larb0>; 937 mediatek,vpu = <&vpu>; 938 }; 939 940 mdp_rdma1: rdma@14002000 { 941 compatible = "mediatek,mt8173-mdp-rdma"; 942 reg = <0 0x14002000 0 0x1000>; 943 clocks = <&mmsys CLK_MM_MDP_RDMA1>, 944 <&mmsys CLK_MM_MUTEX_32K>; 945 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 946 iommus = <&iommu M4U_PORT_MDP_RDMA1>; 947 mediatek,larb = <&larb4>; 948 }; 949 950 mdp_rsz0: rsz@14003000 { 951 compatible = "mediatek,mt8173-mdp-rsz"; 952 reg = <0 0x14003000 0 0x1000>; 953 clocks = <&mmsys CLK_MM_MDP_RSZ0>; 954 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 955 }; 956 957 mdp_rsz1: rsz@14004000 { 958 compatible = "mediatek,mt8173-mdp-rsz"; 959 reg = <0 0x14004000 0 0x1000>; 960 clocks = <&mmsys CLK_MM_MDP_RSZ1>; 961 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 962 }; 963 964 mdp_rsz2: rsz@14005000 { 965 compatible = "mediatek,mt8173-mdp-rsz"; 966 reg = <0 0x14005000 0 0x1000>; 967 clocks = <&mmsys CLK_MM_MDP_RSZ2>; 968 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 969 }; 970 971 mdp_wdma0: wdma@14006000 { 972 compatible = "mediatek,mt8173-mdp-wdma"; 973 reg = <0 0x14006000 0 0x1000>; 974 clocks = <&mmsys CLK_MM_MDP_WDMA>; 975 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 976 iommus = <&iommu M4U_PORT_MDP_WDMA>; 977 mediatek,larb = <&larb0>; 978 }; 979 980 mdp_wrot0: wrot@14007000 { 981 compatible = "mediatek,mt8173-mdp-wrot"; 982 reg = <0 0x14007000 0 0x1000>; 983 clocks = <&mmsys CLK_MM_MDP_WROT0>; 984 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 985 iommus = <&iommu M4U_PORT_MDP_WROT0>; 986 mediatek,larb = <&larb0>; 987 }; 988 989 mdp_wrot1: wrot@14008000 { 990 compatible = "mediatek,mt8173-mdp-wrot"; 991 reg = <0 0x14008000 0 0x1000>; 992 clocks = <&mmsys CLK_MM_MDP_WROT1>; 993 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 994 iommus = <&iommu M4U_PORT_MDP_WROT1>; 995 mediatek,larb = <&larb4>; 996 }; 997 998 ovl0: ovl@1400c000 { 999 compatible = "mediatek,mt8173-disp-ovl"; 1000 reg = <0 0x1400c000 0 0x1000>; 1001 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 1002 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1003 clocks = <&mmsys CLK_MM_DISP_OVL0>; 1004 iommus = <&iommu M4U_PORT_DISP_OVL0>; 1005 mediatek,larb = <&larb0>; 1006 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1007 }; 1008 1009 ovl1: ovl@1400d000 { 1010 compatible = "mediatek,mt8173-disp-ovl"; 1011 reg = <0 0x1400d000 0 0x1000>; 1012 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; 1013 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1014 clocks = <&mmsys CLK_MM_DISP_OVL1>; 1015 iommus = <&iommu M4U_PORT_DISP_OVL1>; 1016 mediatek,larb = <&larb4>; 1017 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 1018 }; 1019 1020 rdma0: rdma@1400e000 { 1021 compatible = "mediatek,mt8173-disp-rdma"; 1022 reg = <0 0x1400e000 0 0x1000>; 1023 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 1024 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1025 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1026 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 1027 mediatek,larb = <&larb0>; 1028 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1029 }; 1030 1031 rdma1: rdma@1400f000 { 1032 compatible = "mediatek,mt8173-disp-rdma"; 1033 reg = <0 0x1400f000 0 0x1000>; 1034 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; 1035 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1036 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 1037 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 1038 mediatek,larb = <&larb4>; 1039 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; 1040 }; 1041 1042 rdma2: rdma@14010000 { 1043 compatible = "mediatek,mt8173-disp-rdma"; 1044 reg = <0 0x14010000 0 0x1000>; 1045 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; 1046 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1047 clocks = <&mmsys CLK_MM_DISP_RDMA2>; 1048 iommus = <&iommu M4U_PORT_DISP_RDMA2>; 1049 mediatek,larb = <&larb4>; 1050 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; 1051 }; 1052 1053 wdma0: wdma@14011000 { 1054 compatible = "mediatek,mt8173-disp-wdma"; 1055 reg = <0 0x14011000 0 0x1000>; 1056 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 1057 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1058 clocks = <&mmsys CLK_MM_DISP_WDMA0>; 1059 iommus = <&iommu M4U_PORT_DISP_WDMA0>; 1060 mediatek,larb = <&larb0>; 1061 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 1062 }; 1063 1064 wdma1: wdma@14012000 { 1065 compatible = "mediatek,mt8173-disp-wdma"; 1066 reg = <0 0x14012000 0 0x1000>; 1067 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; 1068 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1069 clocks = <&mmsys CLK_MM_DISP_WDMA1>; 1070 iommus = <&iommu M4U_PORT_DISP_WDMA1>; 1071 mediatek,larb = <&larb4>; 1072 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; 1073 }; 1074 1075 color0: color@14013000 { 1076 compatible = "mediatek,mt8173-disp-color"; 1077 reg = <0 0x14013000 0 0x1000>; 1078 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; 1079 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1080 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1081 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>; 1082 }; 1083 1084 color1: color@14014000 { 1085 compatible = "mediatek,mt8173-disp-color"; 1086 reg = <0 0x14014000 0 0x1000>; 1087 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 1088 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1089 clocks = <&mmsys CLK_MM_DISP_COLOR1>; 1090 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; 1091 }; 1092 1093 aal@14015000 { 1094 compatible = "mediatek,mt8173-disp-aal"; 1095 reg = <0 0x14015000 0 0x1000>; 1096 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 1097 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1098 clocks = <&mmsys CLK_MM_DISP_AAL>; 1099 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; 1100 }; 1101 1102 gamma@14016000 { 1103 compatible = "mediatek,mt8173-disp-gamma"; 1104 reg = <0 0x14016000 0 0x1000>; 1105 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 1106 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1107 clocks = <&mmsys CLK_MM_DISP_GAMMA>; 1108 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; 1109 }; 1110 1111 merge@14017000 { 1112 compatible = "mediatek,mt8173-disp-merge"; 1113 reg = <0 0x14017000 0 0x1000>; 1114 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1115 clocks = <&mmsys CLK_MM_DISP_MERGE>; 1116 }; 1117 1118 split0: split@14018000 { 1119 compatible = "mediatek,mt8173-disp-split"; 1120 reg = <0 0x14018000 0 0x1000>; 1121 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1122 clocks = <&mmsys CLK_MM_DISP_SPLIT0>; 1123 }; 1124 1125 split1: split@14019000 { 1126 compatible = "mediatek,mt8173-disp-split"; 1127 reg = <0 0x14019000 0 0x1000>; 1128 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1129 clocks = <&mmsys CLK_MM_DISP_SPLIT1>; 1130 }; 1131 1132 ufoe@1401a000 { 1133 compatible = "mediatek,mt8173-disp-ufoe"; 1134 reg = <0 0x1401a000 0 0x1000>; 1135 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 1136 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1137 clocks = <&mmsys CLK_MM_DISP_UFOE>; 1138 }; 1139 1140 dsi0: dsi@1401b000 { 1141 compatible = "mediatek,mt8173-dsi"; 1142 reg = <0 0x1401b000 0 0x1000>; 1143 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 1144 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1145 clocks = <&mmsys CLK_MM_DSI0_ENGINE>, 1146 <&mmsys CLK_MM_DSI0_DIGITAL>, 1147 <&mipi_tx0>; 1148 clock-names = "engine", "digital", "hs"; 1149 phys = <&mipi_tx0>; 1150 phy-names = "dphy"; 1151 status = "disabled"; 1152 }; 1153 1154 dsi1: dsi@1401c000 { 1155 compatible = "mediatek,mt8173-dsi"; 1156 reg = <0 0x1401c000 0 0x1000>; 1157 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 1158 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1159 clocks = <&mmsys CLK_MM_DSI1_ENGINE>, 1160 <&mmsys CLK_MM_DSI1_DIGITAL>, 1161 <&mipi_tx1>; 1162 clock-names = "engine", "digital", "hs"; 1163 phy = <&mipi_tx1>; 1164 phy-names = "dphy"; 1165 status = "disabled"; 1166 }; 1167 1168 dpi0: dpi@1401d000 { 1169 compatible = "mediatek,mt8173-dpi"; 1170 reg = <0 0x1401d000 0 0x1000>; 1171 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 1172 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1173 clocks = <&mmsys CLK_MM_DPI_PIXEL>, 1174 <&mmsys CLK_MM_DPI_ENGINE>, 1175 <&apmixedsys CLK_APMIXED_TVDPLL>; 1176 clock-names = "pixel", "engine", "pll"; 1177 status = "disabled"; 1178 1179 port { 1180 dpi0_out: endpoint { 1181 remote-endpoint = <&hdmi0_in>; 1182 }; 1183 }; 1184 }; 1185 1186 pwm0: pwm@1401e000 { 1187 compatible = "mediatek,mt8173-disp-pwm", 1188 "mediatek,mt6595-disp-pwm"; 1189 reg = <0 0x1401e000 0 0x1000>; 1190 #pwm-cells = <2>; 1191 clocks = <&mmsys CLK_MM_DISP_PWM026M>, 1192 <&mmsys CLK_MM_DISP_PWM0MM>; 1193 clock-names = "main", "mm"; 1194 status = "disabled"; 1195 }; 1196 1197 pwm1: pwm@1401f000 { 1198 compatible = "mediatek,mt8173-disp-pwm", 1199 "mediatek,mt6595-disp-pwm"; 1200 reg = <0 0x1401f000 0 0x1000>; 1201 #pwm-cells = <2>; 1202 clocks = <&mmsys CLK_MM_DISP_PWM126M>, 1203 <&mmsys CLK_MM_DISP_PWM1MM>; 1204 clock-names = "main", "mm"; 1205 status = "disabled"; 1206 }; 1207 1208 mutex: mutex@14020000 { 1209 compatible = "mediatek,mt8173-disp-mutex"; 1210 reg = <0 0x14020000 0 0x1000>; 1211 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 1212 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1213 clocks = <&mmsys CLK_MM_MUTEX_32K>; 1214 mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>, 1215 <CMDQ_EVENT_MUTEX1_STREAM_EOF>; 1216 }; 1217 1218 larb0: larb@14021000 { 1219 compatible = "mediatek,mt8173-smi-larb"; 1220 reg = <0 0x14021000 0 0x1000>; 1221 mediatek,smi = <&smi_common>; 1222 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1223 clocks = <&mmsys CLK_MM_SMI_LARB0>, 1224 <&mmsys CLK_MM_SMI_LARB0>; 1225 clock-names = "apb", "smi"; 1226 }; 1227 1228 smi_common: smi@14022000 { 1229 compatible = "mediatek,mt8173-smi-common"; 1230 reg = <0 0x14022000 0 0x1000>; 1231 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1232 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1233 <&mmsys CLK_MM_SMI_COMMON>; 1234 clock-names = "apb", "smi"; 1235 }; 1236 1237 od@14023000 { 1238 compatible = "mediatek,mt8173-disp-od"; 1239 reg = <0 0x14023000 0 0x1000>; 1240 clocks = <&mmsys CLK_MM_DISP_OD>; 1241 }; 1242 1243 hdmi0: hdmi@14025000 { 1244 compatible = "mediatek,mt8173-hdmi"; 1245 reg = <0 0x14025000 0 0x400>; 1246 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>; 1247 clocks = <&mmsys CLK_MM_HDMI_PIXEL>, 1248 <&mmsys CLK_MM_HDMI_PLLCK>, 1249 <&mmsys CLK_MM_HDMI_AUDIO>, 1250 <&mmsys CLK_MM_HDMI_SPDIF>; 1251 clock-names = "pixel", "pll", "bclk", "spdif"; 1252 pinctrl-names = "default"; 1253 pinctrl-0 = <&hdmi_pin>; 1254 phys = <&hdmi_phy>; 1255 phy-names = "hdmi"; 1256 mediatek,syscon-hdmi = <&mmsys 0x900>; 1257 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; 1258 assigned-clock-parents = <&hdmi_phy>; 1259 status = "disabled"; 1260 1261 ports { 1262 #address-cells = <1>; 1263 #size-cells = <0>; 1264 1265 port@0 { 1266 reg = <0>; 1267 1268 hdmi0_in: endpoint { 1269 remote-endpoint = <&dpi0_out>; 1270 }; 1271 }; 1272 }; 1273 }; 1274 1275 larb4: larb@14027000 { 1276 compatible = "mediatek,mt8173-smi-larb"; 1277 reg = <0 0x14027000 0 0x1000>; 1278 mediatek,smi = <&smi_common>; 1279 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1280 clocks = <&mmsys CLK_MM_SMI_LARB4>, 1281 <&mmsys CLK_MM_SMI_LARB4>; 1282 clock-names = "apb", "smi"; 1283 }; 1284 1285 imgsys: clock-controller@15000000 { 1286 compatible = "mediatek,mt8173-imgsys", "syscon"; 1287 reg = <0 0x15000000 0 0x1000>; 1288 #clock-cells = <1>; 1289 }; 1290 1291 larb2: larb@15001000 { 1292 compatible = "mediatek,mt8173-smi-larb"; 1293 reg = <0 0x15001000 0 0x1000>; 1294 mediatek,smi = <&smi_common>; 1295 power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>; 1296 clocks = <&imgsys CLK_IMG_LARB2_SMI>, 1297 <&imgsys CLK_IMG_LARB2_SMI>; 1298 clock-names = "apb", "smi"; 1299 }; 1300 1301 vdecsys: clock-controller@16000000 { 1302 compatible = "mediatek,mt8173-vdecsys", "syscon"; 1303 reg = <0 0x16000000 0 0x1000>; 1304 #clock-cells = <1>; 1305 }; 1306 1307 vcodec_dec: vcodec@16000000 { 1308 compatible = "mediatek,mt8173-vcodec-dec"; 1309 reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */ 1310 <0 0x16020000 0 0x1000>, /* VDEC_MISC */ 1311 <0 0x16021000 0 0x800>, /* VDEC_LD */ 1312 <0 0x16021800 0 0x800>, /* VDEC_TOP */ 1313 <0 0x16022000 0 0x1000>, /* VDEC_CM */ 1314 <0 0x16023000 0 0x1000>, /* VDEC_AD */ 1315 <0 0x16024000 0 0x1000>, /* VDEC_AV */ 1316 <0 0x16025000 0 0x1000>, /* VDEC_PP */ 1317 <0 0x16026800 0 0x800>, /* VDEC_HWD */ 1318 <0 0x16027000 0 0x800>, /* VDEC_HWQ */ 1319 <0 0x16027800 0 0x800>, /* VDEC_HWB */ 1320 <0 0x16028400 0 0x400>; /* VDEC_HWG */ 1321 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; 1322 mediatek,larb = <&larb1>; 1323 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, 1324 <&iommu M4U_PORT_HW_VDEC_PP_EXT>, 1325 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, 1326 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, 1327 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, 1328 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, 1329 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, 1330 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; 1331 mediatek,vpu = <&vpu>; 1332 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 1333 clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, 1334 <&topckgen CLK_TOP_UNIVPLL_D2>, 1335 <&topckgen CLK_TOP_CCI400_SEL>, 1336 <&topckgen CLK_TOP_VDEC_SEL>, 1337 <&topckgen CLK_TOP_VCODECPLL>, 1338 <&apmixedsys CLK_APMIXED_VENCPLL>, 1339 <&topckgen CLK_TOP_VENC_LT_SEL>, 1340 <&topckgen CLK_TOP_VCODECPLL_370P5>; 1341 clock-names = "vcodecpll", 1342 "univpll_d2", 1343 "clk_cci400_sel", 1344 "vdec_sel", 1345 "vdecpll", 1346 "vencpll", 1347 "venc_lt_sel", 1348 "vdec_bus_clk_src"; 1349 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>, 1350 <&topckgen CLK_TOP_CCI400_SEL>, 1351 <&topckgen CLK_TOP_VDEC_SEL>, 1352 <&apmixedsys CLK_APMIXED_VCODECPLL>, 1353 <&apmixedsys CLK_APMIXED_VENCPLL>; 1354 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>, 1355 <&topckgen CLK_TOP_UNIVPLL_D2>, 1356 <&topckgen CLK_TOP_VCODECPLL>; 1357 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>; 1358 }; 1359 1360 larb1: larb@16010000 { 1361 compatible = "mediatek,mt8173-smi-larb"; 1362 reg = <0 0x16010000 0 0x1000>; 1363 mediatek,smi = <&smi_common>; 1364 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 1365 clocks = <&vdecsys CLK_VDEC_CKEN>, 1366 <&vdecsys CLK_VDEC_LARB_CKEN>; 1367 clock-names = "apb", "smi"; 1368 }; 1369 1370 vencsys: clock-controller@18000000 { 1371 compatible = "mediatek,mt8173-vencsys", "syscon"; 1372 reg = <0 0x18000000 0 0x1000>; 1373 #clock-cells = <1>; 1374 }; 1375 1376 larb3: larb@18001000 { 1377 compatible = "mediatek,mt8173-smi-larb"; 1378 reg = <0 0x18001000 0 0x1000>; 1379 mediatek,smi = <&smi_common>; 1380 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 1381 clocks = <&vencsys CLK_VENC_CKE1>, 1382 <&vencsys CLK_VENC_CKE0>; 1383 clock-names = "apb", "smi"; 1384 }; 1385 1386 vcodec_enc: vcodec@18002000 { 1387 compatible = "mediatek,mt8173-vcodec-enc"; 1388 reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */ 1389 <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ 1390 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>, 1391 <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; 1392 mediatek,larb = <&larb3>, 1393 <&larb5>; 1394 iommus = <&iommu M4U_PORT_VENC_RCPU>, 1395 <&iommu M4U_PORT_VENC_REC>, 1396 <&iommu M4U_PORT_VENC_BSDMA>, 1397 <&iommu M4U_PORT_VENC_SV_COMV>, 1398 <&iommu M4U_PORT_VENC_RD_COMV>, 1399 <&iommu M4U_PORT_VENC_CUR_LUMA>, 1400 <&iommu M4U_PORT_VENC_CUR_CHROMA>, 1401 <&iommu M4U_PORT_VENC_REF_LUMA>, 1402 <&iommu M4U_PORT_VENC_REF_CHROMA>, 1403 <&iommu M4U_PORT_VENC_NBM_RDMA>, 1404 <&iommu M4U_PORT_VENC_NBM_WDMA>, 1405 <&iommu M4U_PORT_VENC_RCPU_SET2>, 1406 <&iommu M4U_PORT_VENC_REC_FRM_SET2>, 1407 <&iommu M4U_PORT_VENC_BSDMA_SET2>, 1408 <&iommu M4U_PORT_VENC_SV_COMA_SET2>, 1409 <&iommu M4U_PORT_VENC_RD_COMA_SET2>, 1410 <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, 1411 <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, 1412 <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, 1413 <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; 1414 mediatek,vpu = <&vpu>; 1415 clocks = <&topckgen CLK_TOP_VENCPLL_D2>, 1416 <&topckgen CLK_TOP_VENC_SEL>, 1417 <&topckgen CLK_TOP_UNIVPLL1_D2>, 1418 <&topckgen CLK_TOP_VENC_LT_SEL>; 1419 clock-names = "venc_sel_src", 1420 "venc_sel", 1421 "venc_lt_sel_src", 1422 "venc_lt_sel"; 1423 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>, 1424 <&topckgen CLK_TOP_VENC_LT_SEL>; 1425 assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>, 1426 <&topckgen CLK_TOP_UNIVPLL1_D2>; 1427 }; 1428 1429 jpegdec: jpegdec@18004000 { 1430 compatible = "mediatek,mt8173-jpgdec"; 1431 reg = <0 0x18004000 0 0x1000>; 1432 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW>; 1433 clocks = <&vencsys CLK_VENC_CKE0>, 1434 <&vencsys CLK_VENC_CKE3>; 1435 clock-names = "jpgdec-smi", 1436 "jpgdec"; 1437 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 1438 mediatek,larb = <&larb3>; 1439 iommus = <&iommu M4U_PORT_JPGDEC_WDMA>, 1440 <&iommu M4U_PORT_JPGDEC_BSDMA>; 1441 }; 1442 1443 vencltsys: clock-controller@19000000 { 1444 compatible = "mediatek,mt8173-vencltsys", "syscon"; 1445 reg = <0 0x19000000 0 0x1000>; 1446 #clock-cells = <1>; 1447 }; 1448 1449 larb5: larb@19001000 { 1450 compatible = "mediatek,mt8173-smi-larb"; 1451 reg = <0 0x19001000 0 0x1000>; 1452 mediatek,smi = <&smi_common>; 1453 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; 1454 clocks = <&vencltsys CLK_VENCLT_CKE1>, 1455 <&vencltsys CLK_VENCLT_CKE0>; 1456 clock-names = "apb", "smi"; 1457 }; 1458 }; 1459}; 1460