1/* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Eddie Huang <eddie.huang@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/clock/mt8173-clk.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/memory/mt8173-larb-port.h> 18#include <dt-bindings/phy/phy.h> 19#include <dt-bindings/power/mt8173-power.h> 20#include <dt-bindings/reset/mt8173-resets.h> 21#include "mt8173-pinfunc.h" 22 23/ { 24 compatible = "mediatek,mt8173"; 25 interrupt-parent = <&sysirq>; 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 aliases { 30 ovl0 = &ovl0; 31 ovl1 = &ovl1; 32 rdma0 = &rdma0; 33 rdma1 = &rdma1; 34 rdma2 = &rdma2; 35 wdma0 = &wdma0; 36 wdma1 = &wdma1; 37 color0 = &color0; 38 color1 = &color1; 39 split0 = &split0; 40 split1 = &split1; 41 dpi0 = &dpi0; 42 dsi0 = &dsi0; 43 dsi1 = &dsi1; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 cpu-map { 51 cluster0 { 52 core0 { 53 cpu = <&cpu0>; 54 }; 55 core1 { 56 cpu = <&cpu1>; 57 }; 58 }; 59 60 cluster1 { 61 core0 { 62 cpu = <&cpu2>; 63 }; 64 core1 { 65 cpu = <&cpu3>; 66 }; 67 }; 68 }; 69 70 cpu0: cpu@0 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53"; 73 reg = <0x000>; 74 enable-method = "psci"; 75 cpu-idle-states = <&CPU_SLEEP_0>; 76 }; 77 78 cpu1: cpu@1 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a53"; 81 reg = <0x001>; 82 enable-method = "psci"; 83 cpu-idle-states = <&CPU_SLEEP_0>; 84 }; 85 86 cpu2: cpu@100 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a57"; 89 reg = <0x100>; 90 enable-method = "psci"; 91 cpu-idle-states = <&CPU_SLEEP_0>; 92 }; 93 94 cpu3: cpu@101 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a57"; 97 reg = <0x101>; 98 enable-method = "psci"; 99 cpu-idle-states = <&CPU_SLEEP_0>; 100 }; 101 102 idle-states { 103 entry-method = "psci"; 104 105 CPU_SLEEP_0: cpu-sleep-0 { 106 compatible = "arm,idle-state"; 107 local-timer-stop; 108 entry-latency-us = <639>; 109 exit-latency-us = <680>; 110 min-residency-us = <1088>; 111 arm,psci-suspend-param = <0x0010000>; 112 }; 113 }; 114 }; 115 116 psci { 117 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 118 method = "smc"; 119 cpu_suspend = <0x84000001>; 120 cpu_off = <0x84000002>; 121 cpu_on = <0x84000003>; 122 }; 123 124 clk26m: oscillator@0 { 125 compatible = "fixed-clock"; 126 #clock-cells = <0>; 127 clock-frequency = <26000000>; 128 clock-output-names = "clk26m"; 129 }; 130 131 clk32k: oscillator@1 { 132 compatible = "fixed-clock"; 133 #clock-cells = <0>; 134 clock-frequency = <32000>; 135 clock-output-names = "clk32k"; 136 }; 137 138 cpum_ck: oscillator@2 { 139 compatible = "fixed-clock"; 140 #clock-cells = <0>; 141 clock-frequency = <0>; 142 clock-output-names = "cpum_ck"; 143 }; 144 145 thermal-zones { 146 cpu_thermal: cpu_thermal { 147 polling-delay-passive = <1000>; /* milliseconds */ 148 polling-delay = <1000>; /* milliseconds */ 149 150 thermal-sensors = <&thermal>; 151 sustainable-power = <1500>; /* milliwatts */ 152 153 trips { 154 threshold: trip-point@0 { 155 temperature = <68000>; 156 hysteresis = <2000>; 157 type = "passive"; 158 }; 159 160 target: trip-point@1 { 161 temperature = <85000>; 162 hysteresis = <2000>; 163 type = "passive"; 164 }; 165 166 cpu_crit: cpu_crit@0 { 167 temperature = <115000>; 168 hysteresis = <2000>; 169 type = "critical"; 170 }; 171 }; 172 173 cooling-maps { 174 map@0 { 175 trip = <&target>; 176 cooling-device = <&cpu0 0 0>; 177 contribution = <1024>; 178 }; 179 map@1 { 180 trip = <&target>; 181 cooling-device = <&cpu2 0 0>; 182 contribution = <2048>; 183 }; 184 }; 185 }; 186 }; 187 188 reserved-memory { 189 #address-cells = <2>; 190 #size-cells = <2>; 191 ranges; 192 vpu_dma_reserved: vpu_dma_mem_region { 193 compatible = "shared-dma-pool"; 194 reg = <0 0xb7000000 0 0x500000>; 195 alignment = <0x1000>; 196 no-map; 197 }; 198 }; 199 200 timer { 201 compatible = "arm,armv8-timer"; 202 interrupt-parent = <&gic>; 203 interrupts = <GIC_PPI 13 204 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 205 <GIC_PPI 14 206 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 207 <GIC_PPI 11 208 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 209 <GIC_PPI 10 210 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 211 }; 212 213 soc { 214 #address-cells = <2>; 215 #size-cells = <2>; 216 compatible = "simple-bus"; 217 ranges; 218 219 topckgen: clock-controller@10000000 { 220 compatible = "mediatek,mt8173-topckgen"; 221 reg = <0 0x10000000 0 0x1000>; 222 #clock-cells = <1>; 223 }; 224 225 infracfg: power-controller@10001000 { 226 compatible = "mediatek,mt8173-infracfg", "syscon"; 227 reg = <0 0x10001000 0 0x1000>; 228 #clock-cells = <1>; 229 #reset-cells = <1>; 230 }; 231 232 pericfg: power-controller@10003000 { 233 compatible = "mediatek,mt8173-pericfg", "syscon"; 234 reg = <0 0x10003000 0 0x1000>; 235 #clock-cells = <1>; 236 #reset-cells = <1>; 237 }; 238 239 syscfg_pctl_a: syscfg_pctl_a@10005000 { 240 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 241 reg = <0 0x10005000 0 0x1000>; 242 }; 243 244 pio: pinctrl@0x10005000 { 245 compatible = "mediatek,mt8173-pinctrl"; 246 reg = <0 0x1000b000 0 0x1000>; 247 mediatek,pctl-regmap = <&syscfg_pctl_a>; 248 pins-are-numbered; 249 gpio-controller; 250 #gpio-cells = <2>; 251 interrupt-controller; 252 #interrupt-cells = <2>; 253 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 256 257 hdmi_pin: xxx { 258 259 /*hdmi htplg pin*/ 260 pins1 { 261 pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>; 262 input-enable; 263 bias-pull-down; 264 }; 265 }; 266 267 i2c0_pins_a: i2c0 { 268 pins1 { 269 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 270 <MT8173_PIN_46_SCL0__FUNC_SCL0>; 271 bias-disable; 272 }; 273 }; 274 275 i2c1_pins_a: i2c1 { 276 pins1 { 277 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 278 <MT8173_PIN_126_SCL1__FUNC_SCL1>; 279 bias-disable; 280 }; 281 }; 282 283 i2c2_pins_a: i2c2 { 284 pins1 { 285 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 286 <MT8173_PIN_44_SCL2__FUNC_SCL2>; 287 bias-disable; 288 }; 289 }; 290 291 i2c3_pins_a: i2c3 { 292 pins1 { 293 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 294 <MT8173_PIN_107_SCL3__FUNC_SCL3>; 295 bias-disable; 296 }; 297 }; 298 299 i2c4_pins_a: i2c4 { 300 pins1 { 301 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 302 <MT8173_PIN_134_SCL4__FUNC_SCL4>; 303 bias-disable; 304 }; 305 }; 306 307 i2c6_pins_a: i2c6 { 308 pins1 { 309 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 310 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 311 bias-disable; 312 }; 313 }; 314 }; 315 316 scpsys: scpsys@10006000 { 317 compatible = "mediatek,mt8173-scpsys"; 318 #power-domain-cells = <1>; 319 reg = <0 0x10006000 0 0x1000>; 320 clocks = <&clk26m>, 321 <&topckgen CLK_TOP_MM_SEL>, 322 <&topckgen CLK_TOP_VENC_SEL>, 323 <&topckgen CLK_TOP_VENC_LT_SEL>; 324 clock-names = "mfg", "mm", "venc", "venc_lt"; 325 infracfg = <&infracfg>; 326 }; 327 328 watchdog: watchdog@10007000 { 329 compatible = "mediatek,mt8173-wdt", 330 "mediatek,mt6589-wdt"; 331 reg = <0 0x10007000 0 0x100>; 332 }; 333 334 timer: timer@10008000 { 335 compatible = "mediatek,mt8173-timer", 336 "mediatek,mt6577-timer"; 337 reg = <0 0x10008000 0 0x1000>; 338 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 339 clocks = <&infracfg CLK_INFRA_CLK_13M>, 340 <&topckgen CLK_TOP_RTC_SEL>; 341 }; 342 343 pwrap: pwrap@1000d000 { 344 compatible = "mediatek,mt8173-pwrap"; 345 reg = <0 0x1000d000 0 0x1000>; 346 reg-names = "pwrap"; 347 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 348 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 349 reset-names = "pwrap"; 350 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 351 clock-names = "spi", "wrap"; 352 }; 353 354 cec: cec@10013000 { 355 compatible = "mediatek,mt8173-cec"; 356 reg = <0 0x10013000 0 0xbc>; 357 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; 358 clocks = <&infracfg CLK_INFRA_CEC>; 359 status = "disabled"; 360 }; 361 362 vpu: vpu@10020000 { 363 compatible = "mediatek,mt8173-vpu"; 364 reg = <0 0x10020000 0 0x30000>, 365 <0 0x10050000 0 0x100>; 366 reg-names = "tcm", "cfg_reg"; 367 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 368 clocks = <&topckgen CLK_TOP_SCP_SEL>; 369 clock-names = "main"; 370 memory-region = <&vpu_dma_reserved>; 371 }; 372 373 sysirq: intpol-controller@10200620 { 374 compatible = "mediatek,mt8173-sysirq", 375 "mediatek,mt6577-sysirq"; 376 interrupt-controller; 377 #interrupt-cells = <3>; 378 interrupt-parent = <&gic>; 379 reg = <0 0x10200620 0 0x20>; 380 }; 381 382 iommu: iommu@10205000 { 383 compatible = "mediatek,mt8173-m4u"; 384 reg = <0 0x10205000 0 0x1000>; 385 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 386 clocks = <&infracfg CLK_INFRA_M4U>; 387 clock-names = "bclk"; 388 mediatek,larbs = <&larb0 &larb1 &larb2 389 &larb3 &larb4 &larb5>; 390 #iommu-cells = <1>; 391 }; 392 393 efuse: efuse@10206000 { 394 compatible = "mediatek,mt8173-efuse"; 395 reg = <0 0x10206000 0 0x1000>; 396 }; 397 398 apmixedsys: clock-controller@10209000 { 399 compatible = "mediatek,mt8173-apmixedsys"; 400 reg = <0 0x10209000 0 0x1000>; 401 #clock-cells = <1>; 402 }; 403 404 hdmi_phy: hdmi-phy@10209100 { 405 compatible = "mediatek,mt8173-hdmi-phy"; 406 reg = <0 0x10209100 0 0x24>; 407 clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; 408 clock-names = "pll_ref"; 409 clock-output-names = "hdmitx_dig_cts"; 410 mediatek,ibias = <0xa>; 411 mediatek,ibias_up = <0x1c>; 412 #clock-cells = <0>; 413 #phy-cells = <0>; 414 status = "disabled"; 415 }; 416 417 mipi_tx0: mipi-dphy@10215000 { 418 compatible = "mediatek,mt8173-mipi-tx"; 419 reg = <0 0x10215000 0 0x1000>; 420 clocks = <&clk26m>; 421 clock-output-names = "mipi_tx0_pll"; 422 #clock-cells = <0>; 423 #phy-cells = <0>; 424 status = "disabled"; 425 }; 426 427 mipi_tx1: mipi-dphy@10216000 { 428 compatible = "mediatek,mt8173-mipi-tx"; 429 reg = <0 0x10216000 0 0x1000>; 430 clocks = <&clk26m>; 431 clock-output-names = "mipi_tx1_pll"; 432 #clock-cells = <0>; 433 #phy-cells = <0>; 434 status = "disabled"; 435 }; 436 437 gic: interrupt-controller@10220000 { 438 compatible = "arm,gic-400"; 439 #interrupt-cells = <3>; 440 interrupt-parent = <&gic>; 441 interrupt-controller; 442 reg = <0 0x10221000 0 0x1000>, 443 <0 0x10222000 0 0x2000>, 444 <0 0x10224000 0 0x2000>, 445 <0 0x10226000 0 0x2000>; 446 interrupts = <GIC_PPI 9 447 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 448 }; 449 450 auxadc: auxadc@11001000 { 451 compatible = "mediatek,mt8173-auxadc"; 452 reg = <0 0x11001000 0 0x1000>; 453 }; 454 455 uart0: serial@11002000 { 456 compatible = "mediatek,mt8173-uart", 457 "mediatek,mt6577-uart"; 458 reg = <0 0x11002000 0 0x400>; 459 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 460 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 461 clock-names = "baud", "bus"; 462 status = "disabled"; 463 }; 464 465 uart1: serial@11003000 { 466 compatible = "mediatek,mt8173-uart", 467 "mediatek,mt6577-uart"; 468 reg = <0 0x11003000 0 0x400>; 469 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 470 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 471 clock-names = "baud", "bus"; 472 status = "disabled"; 473 }; 474 475 uart2: serial@11004000 { 476 compatible = "mediatek,mt8173-uart", 477 "mediatek,mt6577-uart"; 478 reg = <0 0x11004000 0 0x400>; 479 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 480 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 481 clock-names = "baud", "bus"; 482 status = "disabled"; 483 }; 484 485 uart3: serial@11005000 { 486 compatible = "mediatek,mt8173-uart", 487 "mediatek,mt6577-uart"; 488 reg = <0 0x11005000 0 0x400>; 489 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 490 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 491 clock-names = "baud", "bus"; 492 status = "disabled"; 493 }; 494 495 i2c0: i2c@11007000 { 496 compatible = "mediatek,mt8173-i2c"; 497 reg = <0 0x11007000 0 0x70>, 498 <0 0x11000100 0 0x80>; 499 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 500 clock-div = <16>; 501 clocks = <&pericfg CLK_PERI_I2C0>, 502 <&pericfg CLK_PERI_AP_DMA>; 503 clock-names = "main", "dma"; 504 pinctrl-names = "default"; 505 pinctrl-0 = <&i2c0_pins_a>; 506 #address-cells = <1>; 507 #size-cells = <0>; 508 status = "disabled"; 509 }; 510 511 i2c1: i2c@11008000 { 512 compatible = "mediatek,mt8173-i2c"; 513 reg = <0 0x11008000 0 0x70>, 514 <0 0x11000180 0 0x80>; 515 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 516 clock-div = <16>; 517 clocks = <&pericfg CLK_PERI_I2C1>, 518 <&pericfg CLK_PERI_AP_DMA>; 519 clock-names = "main", "dma"; 520 pinctrl-names = "default"; 521 pinctrl-0 = <&i2c1_pins_a>; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 status = "disabled"; 525 }; 526 527 i2c2: i2c@11009000 { 528 compatible = "mediatek,mt8173-i2c"; 529 reg = <0 0x11009000 0 0x70>, 530 <0 0x11000200 0 0x80>; 531 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 532 clock-div = <16>; 533 clocks = <&pericfg CLK_PERI_I2C2>, 534 <&pericfg CLK_PERI_AP_DMA>; 535 clock-names = "main", "dma"; 536 pinctrl-names = "default"; 537 pinctrl-0 = <&i2c2_pins_a>; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 status = "disabled"; 541 }; 542 543 spi: spi@1100a000 { 544 compatible = "mediatek,mt8173-spi"; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 reg = <0 0x1100a000 0 0x1000>; 548 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 549 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 550 <&topckgen CLK_TOP_SPI_SEL>, 551 <&pericfg CLK_PERI_SPI0>; 552 clock-names = "parent-clk", "sel-clk", "spi-clk"; 553 status = "disabled"; 554 }; 555 556 thermal: thermal@1100b000 { 557 #thermal-sensor-cells = <0>; 558 compatible = "mediatek,mt8173-thermal"; 559 reg = <0 0x1100b000 0 0x1000>; 560 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 561 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 562 clock-names = "therm", "auxadc"; 563 resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 564 mediatek,auxadc = <&auxadc>; 565 mediatek,apmixedsys = <&apmixedsys>; 566 }; 567 568 nor_flash: spi@1100d000 { 569 compatible = "mediatek,mt8173-nor"; 570 reg = <0 0x1100d000 0 0xe0>; 571 clocks = <&pericfg CLK_PERI_SPI>, 572 <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 573 clock-names = "spi", "sf"; 574 #address-cells = <1>; 575 #size-cells = <0>; 576 status = "disabled"; 577 }; 578 579 i2c3: i2c@11010000 { 580 compatible = "mediatek,mt8173-i2c"; 581 reg = <0 0x11010000 0 0x70>, 582 <0 0x11000280 0 0x80>; 583 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 584 clock-div = <16>; 585 clocks = <&pericfg CLK_PERI_I2C3>, 586 <&pericfg CLK_PERI_AP_DMA>; 587 clock-names = "main", "dma"; 588 pinctrl-names = "default"; 589 pinctrl-0 = <&i2c3_pins_a>; 590 #address-cells = <1>; 591 #size-cells = <0>; 592 status = "disabled"; 593 }; 594 595 i2c4: i2c@11011000 { 596 compatible = "mediatek,mt8173-i2c"; 597 reg = <0 0x11011000 0 0x70>, 598 <0 0x11000300 0 0x80>; 599 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 600 clock-div = <16>; 601 clocks = <&pericfg CLK_PERI_I2C4>, 602 <&pericfg CLK_PERI_AP_DMA>; 603 clock-names = "main", "dma"; 604 pinctrl-names = "default"; 605 pinctrl-0 = <&i2c4_pins_a>; 606 #address-cells = <1>; 607 #size-cells = <0>; 608 status = "disabled"; 609 }; 610 611 hdmiddc0: i2c@11012000 { 612 compatible = "mediatek,mt8173-hdmi-ddc"; 613 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 614 reg = <0 0x11012000 0 0x1C>; 615 clocks = <&pericfg CLK_PERI_I2C5>; 616 clock-names = "ddc-i2c"; 617 }; 618 619 i2c6: i2c@11013000 { 620 compatible = "mediatek,mt8173-i2c"; 621 reg = <0 0x11013000 0 0x70>, 622 <0 0x11000080 0 0x80>; 623 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 624 clock-div = <16>; 625 clocks = <&pericfg CLK_PERI_I2C6>, 626 <&pericfg CLK_PERI_AP_DMA>; 627 clock-names = "main", "dma"; 628 pinctrl-names = "default"; 629 pinctrl-0 = <&i2c6_pins_a>; 630 #address-cells = <1>; 631 #size-cells = <0>; 632 status = "disabled"; 633 }; 634 635 afe: audio-controller@11220000 { 636 compatible = "mediatek,mt8173-afe-pcm"; 637 reg = <0 0x11220000 0 0x1000>; 638 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 639 power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; 640 clocks = <&infracfg CLK_INFRA_AUDIO>, 641 <&topckgen CLK_TOP_AUDIO_SEL>, 642 <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 643 <&topckgen CLK_TOP_APLL1_DIV0>, 644 <&topckgen CLK_TOP_APLL2_DIV0>, 645 <&topckgen CLK_TOP_I2S0_M_SEL>, 646 <&topckgen CLK_TOP_I2S1_M_SEL>, 647 <&topckgen CLK_TOP_I2S2_M_SEL>, 648 <&topckgen CLK_TOP_I2S3_M_SEL>, 649 <&topckgen CLK_TOP_I2S3_B_SEL>; 650 clock-names = "infra_sys_audio_clk", 651 "top_pdn_audio", 652 "top_pdn_aud_intbus", 653 "bck0", 654 "bck1", 655 "i2s0_m", 656 "i2s1_m", 657 "i2s2_m", 658 "i2s3_m", 659 "i2s3_b"; 660 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 661 <&topckgen CLK_TOP_AUD_2_SEL>; 662 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 663 <&topckgen CLK_TOP_APLL2>; 664 }; 665 666 mmc0: mmc@11230000 { 667 compatible = "mediatek,mt8173-mmc", 668 "mediatek,mt8135-mmc"; 669 reg = <0 0x11230000 0 0x1000>; 670 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 671 clocks = <&pericfg CLK_PERI_MSDC30_0>, 672 <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 673 clock-names = "source", "hclk"; 674 status = "disabled"; 675 }; 676 677 mmc1: mmc@11240000 { 678 compatible = "mediatek,mt8173-mmc", 679 "mediatek,mt8135-mmc"; 680 reg = <0 0x11240000 0 0x1000>; 681 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 682 clocks = <&pericfg CLK_PERI_MSDC30_1>, 683 <&topckgen CLK_TOP_AXI_SEL>; 684 clock-names = "source", "hclk"; 685 status = "disabled"; 686 }; 687 688 mmc2: mmc@11250000 { 689 compatible = "mediatek,mt8173-mmc", 690 "mediatek,mt8135-mmc"; 691 reg = <0 0x11250000 0 0x1000>; 692 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 693 clocks = <&pericfg CLK_PERI_MSDC30_2>, 694 <&topckgen CLK_TOP_AXI_SEL>; 695 clock-names = "source", "hclk"; 696 status = "disabled"; 697 }; 698 699 mmc3: mmc@11260000 { 700 compatible = "mediatek,mt8173-mmc", 701 "mediatek,mt8135-mmc"; 702 reg = <0 0x11260000 0 0x1000>; 703 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 704 clocks = <&pericfg CLK_PERI_MSDC30_3>, 705 <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 706 clock-names = "source", "hclk"; 707 status = "disabled"; 708 }; 709 710 usb30: usb@11270000 { 711 compatible = "mediatek,mt8173-xhci"; 712 reg = <0 0x11270000 0 0x1000>, 713 <0 0x11280700 0 0x0100>; 714 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 715 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 716 clocks = <&topckgen CLK_TOP_USB30_SEL>, 717 <&pericfg CLK_PERI_USB0>, 718 <&pericfg CLK_PERI_USB1>; 719 clock-names = "sys_ck", 720 "wakeup_deb_p0", 721 "wakeup_deb_p1"; 722 phys = <&phy_port0 PHY_TYPE_USB3>, 723 <&phy_port1 PHY_TYPE_USB2>; 724 mediatek,syscon-wakeup = <&pericfg>; 725 status = "okay"; 726 }; 727 728 u3phy: usb-phy@11290000 { 729 compatible = "mediatek,mt8173-u3phy"; 730 reg = <0 0x11290000 0 0x800>; 731 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 732 clock-names = "u3phya_ref"; 733 #address-cells = <2>; 734 #size-cells = <2>; 735 ranges; 736 status = "okay"; 737 738 phy_port0: port@11290800 { 739 reg = <0 0x11290800 0 0x800>; 740 #phy-cells = <1>; 741 status = "okay"; 742 }; 743 744 phy_port1: port@11291000 { 745 reg = <0 0x11291000 0 0x800>; 746 #phy-cells = <1>; 747 status = "okay"; 748 }; 749 }; 750 751 mmsys: clock-controller@14000000 { 752 compatible = "mediatek,mt8173-mmsys", "syscon"; 753 reg = <0 0x14000000 0 0x1000>; 754 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 755 #clock-cells = <1>; 756 }; 757 758 ovl0: ovl@1400c000 { 759 compatible = "mediatek,mt8173-disp-ovl"; 760 reg = <0 0x1400c000 0 0x1000>; 761 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 762 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 763 clocks = <&mmsys CLK_MM_DISP_OVL0>; 764 iommus = <&iommu M4U_PORT_DISP_OVL0>; 765 mediatek,larb = <&larb0>; 766 }; 767 768 ovl1: ovl@1400d000 { 769 compatible = "mediatek,mt8173-disp-ovl"; 770 reg = <0 0x1400d000 0 0x1000>; 771 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; 772 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 773 clocks = <&mmsys CLK_MM_DISP_OVL1>; 774 iommus = <&iommu M4U_PORT_DISP_OVL1>; 775 mediatek,larb = <&larb4>; 776 }; 777 778 rdma0: rdma@1400e000 { 779 compatible = "mediatek,mt8173-disp-rdma"; 780 reg = <0 0x1400e000 0 0x1000>; 781 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 782 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 783 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 784 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 785 mediatek,larb = <&larb0>; 786 }; 787 788 rdma1: rdma@1400f000 { 789 compatible = "mediatek,mt8173-disp-rdma"; 790 reg = <0 0x1400f000 0 0x1000>; 791 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; 792 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 793 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 794 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 795 mediatek,larb = <&larb4>; 796 }; 797 798 rdma2: rdma@14010000 { 799 compatible = "mediatek,mt8173-disp-rdma"; 800 reg = <0 0x14010000 0 0x1000>; 801 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; 802 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 803 clocks = <&mmsys CLK_MM_DISP_RDMA2>; 804 iommus = <&iommu M4U_PORT_DISP_RDMA2>; 805 mediatek,larb = <&larb4>; 806 }; 807 808 wdma0: wdma@14011000 { 809 compatible = "mediatek,mt8173-disp-wdma"; 810 reg = <0 0x14011000 0 0x1000>; 811 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 812 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 813 clocks = <&mmsys CLK_MM_DISP_WDMA0>; 814 iommus = <&iommu M4U_PORT_DISP_WDMA0>; 815 mediatek,larb = <&larb0>; 816 }; 817 818 wdma1: wdma@14012000 { 819 compatible = "mediatek,mt8173-disp-wdma"; 820 reg = <0 0x14012000 0 0x1000>; 821 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; 822 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 823 clocks = <&mmsys CLK_MM_DISP_WDMA1>; 824 iommus = <&iommu M4U_PORT_DISP_WDMA1>; 825 mediatek,larb = <&larb4>; 826 }; 827 828 color0: color@14013000 { 829 compatible = "mediatek,mt8173-disp-color"; 830 reg = <0 0x14013000 0 0x1000>; 831 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; 832 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 833 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 834 }; 835 836 color1: color@14014000 { 837 compatible = "mediatek,mt8173-disp-color"; 838 reg = <0 0x14014000 0 0x1000>; 839 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 840 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 841 clocks = <&mmsys CLK_MM_DISP_COLOR1>; 842 }; 843 844 aal@14015000 { 845 compatible = "mediatek,mt8173-disp-aal"; 846 reg = <0 0x14015000 0 0x1000>; 847 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 848 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 849 clocks = <&mmsys CLK_MM_DISP_AAL>; 850 }; 851 852 gamma@14016000 { 853 compatible = "mediatek,mt8173-disp-gamma"; 854 reg = <0 0x14016000 0 0x1000>; 855 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 856 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 857 clocks = <&mmsys CLK_MM_DISP_GAMMA>; 858 }; 859 860 merge@14017000 { 861 compatible = "mediatek,mt8173-disp-merge"; 862 reg = <0 0x14017000 0 0x1000>; 863 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 864 clocks = <&mmsys CLK_MM_DISP_MERGE>; 865 }; 866 867 split0: split@14018000 { 868 compatible = "mediatek,mt8173-disp-split"; 869 reg = <0 0x14018000 0 0x1000>; 870 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 871 clocks = <&mmsys CLK_MM_DISP_SPLIT0>; 872 }; 873 874 split1: split@14019000 { 875 compatible = "mediatek,mt8173-disp-split"; 876 reg = <0 0x14019000 0 0x1000>; 877 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 878 clocks = <&mmsys CLK_MM_DISP_SPLIT1>; 879 }; 880 881 ufoe@1401a000 { 882 compatible = "mediatek,mt8173-disp-ufoe"; 883 reg = <0 0x1401a000 0 0x1000>; 884 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 885 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 886 clocks = <&mmsys CLK_MM_DISP_UFOE>; 887 }; 888 889 dsi0: dsi@1401b000 { 890 compatible = "mediatek,mt8173-dsi"; 891 reg = <0 0x1401b000 0 0x1000>; 892 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 893 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 894 clocks = <&mmsys CLK_MM_DSI0_ENGINE>, 895 <&mmsys CLK_MM_DSI0_DIGITAL>, 896 <&mipi_tx0>; 897 clock-names = "engine", "digital", "hs"; 898 phys = <&mipi_tx0>; 899 phy-names = "dphy"; 900 status = "disabled"; 901 }; 902 903 dsi1: dsi@1401c000 { 904 compatible = "mediatek,mt8173-dsi"; 905 reg = <0 0x1401c000 0 0x1000>; 906 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 907 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 908 clocks = <&mmsys CLK_MM_DSI1_ENGINE>, 909 <&mmsys CLK_MM_DSI1_DIGITAL>, 910 <&mipi_tx1>; 911 clock-names = "engine", "digital", "hs"; 912 phy = <&mipi_tx1>; 913 phy-names = "dphy"; 914 status = "disabled"; 915 }; 916 917 dpi0: dpi@1401d000 { 918 compatible = "mediatek,mt8173-dpi"; 919 reg = <0 0x1401d000 0 0x1000>; 920 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 921 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 922 clocks = <&mmsys CLK_MM_DPI_PIXEL>, 923 <&mmsys CLK_MM_DPI_ENGINE>, 924 <&apmixedsys CLK_APMIXED_TVDPLL>; 925 clock-names = "pixel", "engine", "pll"; 926 status = "disabled"; 927 928 port { 929 dpi0_out: endpoint { 930 remote-endpoint = <&hdmi0_in>; 931 }; 932 }; 933 }; 934 935 pwm0: pwm@1401e000 { 936 compatible = "mediatek,mt8173-disp-pwm", 937 "mediatek,mt6595-disp-pwm"; 938 reg = <0 0x1401e000 0 0x1000>; 939 #pwm-cells = <2>; 940 clocks = <&mmsys CLK_MM_DISP_PWM026M>, 941 <&mmsys CLK_MM_DISP_PWM0MM>; 942 clock-names = "main", "mm"; 943 status = "disabled"; 944 }; 945 946 pwm1: pwm@1401f000 { 947 compatible = "mediatek,mt8173-disp-pwm", 948 "mediatek,mt6595-disp-pwm"; 949 reg = <0 0x1401f000 0 0x1000>; 950 #pwm-cells = <2>; 951 clocks = <&mmsys CLK_MM_DISP_PWM126M>, 952 <&mmsys CLK_MM_DISP_PWM1MM>; 953 clock-names = "main", "mm"; 954 status = "disabled"; 955 }; 956 957 mutex: mutex@14020000 { 958 compatible = "mediatek,mt8173-disp-mutex"; 959 reg = <0 0x14020000 0 0x1000>; 960 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 961 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 962 clocks = <&mmsys CLK_MM_MUTEX_32K>; 963 }; 964 965 larb0: larb@14021000 { 966 compatible = "mediatek,mt8173-smi-larb"; 967 reg = <0 0x14021000 0 0x1000>; 968 mediatek,smi = <&smi_common>; 969 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 970 clocks = <&mmsys CLK_MM_SMI_LARB0>, 971 <&mmsys CLK_MM_SMI_LARB0>; 972 clock-names = "apb", "smi"; 973 }; 974 975 smi_common: smi@14022000 { 976 compatible = "mediatek,mt8173-smi-common"; 977 reg = <0 0x14022000 0 0x1000>; 978 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 979 clocks = <&mmsys CLK_MM_SMI_COMMON>, 980 <&mmsys CLK_MM_SMI_COMMON>; 981 clock-names = "apb", "smi"; 982 }; 983 984 od@14023000 { 985 compatible = "mediatek,mt8173-disp-od"; 986 reg = <0 0x14023000 0 0x1000>; 987 clocks = <&mmsys CLK_MM_DISP_OD>; 988 }; 989 990 hdmi0: hdmi@14025000 { 991 compatible = "mediatek,mt8173-hdmi"; 992 reg = <0 0x14025000 0 0x400>; 993 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>; 994 clocks = <&mmsys CLK_MM_HDMI_PIXEL>, 995 <&mmsys CLK_MM_HDMI_PLLCK>, 996 <&mmsys CLK_MM_HDMI_AUDIO>, 997 <&mmsys CLK_MM_HDMI_SPDIF>; 998 clock-names = "pixel", "pll", "bclk", "spdif"; 999 pinctrl-names = "default"; 1000 pinctrl-0 = <&hdmi_pin>; 1001 phys = <&hdmi_phy>; 1002 phy-names = "hdmi"; 1003 mediatek,syscon-hdmi = <&mmsys 0x900>; 1004 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; 1005 assigned-clock-parents = <&hdmi_phy>; 1006 status = "disabled"; 1007 1008 ports { 1009 #address-cells = <1>; 1010 #size-cells = <0>; 1011 1012 port@0 { 1013 reg = <0>; 1014 1015 hdmi0_in: endpoint { 1016 remote-endpoint = <&dpi0_out>; 1017 }; 1018 }; 1019 }; 1020 }; 1021 1022 larb4: larb@14027000 { 1023 compatible = "mediatek,mt8173-smi-larb"; 1024 reg = <0 0x14027000 0 0x1000>; 1025 mediatek,smi = <&smi_common>; 1026 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1027 clocks = <&mmsys CLK_MM_SMI_LARB4>, 1028 <&mmsys CLK_MM_SMI_LARB4>; 1029 clock-names = "apb", "smi"; 1030 }; 1031 1032 imgsys: clock-controller@15000000 { 1033 compatible = "mediatek,mt8173-imgsys", "syscon"; 1034 reg = <0 0x15000000 0 0x1000>; 1035 #clock-cells = <1>; 1036 }; 1037 1038 larb2: larb@15001000 { 1039 compatible = "mediatek,mt8173-smi-larb"; 1040 reg = <0 0x15001000 0 0x1000>; 1041 mediatek,smi = <&smi_common>; 1042 power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>; 1043 clocks = <&imgsys CLK_IMG_LARB2_SMI>, 1044 <&imgsys CLK_IMG_LARB2_SMI>; 1045 clock-names = "apb", "smi"; 1046 }; 1047 1048 vdecsys: clock-controller@16000000 { 1049 compatible = "mediatek,mt8173-vdecsys", "syscon"; 1050 reg = <0 0x16000000 0 0x1000>; 1051 #clock-cells = <1>; 1052 }; 1053 1054 vcodec_dec: vcodec@16000000 { 1055 compatible = "mediatek,mt8173-vcodec-dec"; 1056 reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */ 1057 <0 0x16020000 0 0x1000>, /* VDEC_MISC */ 1058 <0 0x16021000 0 0x800>, /* VDEC_LD */ 1059 <0 0x16021800 0 0x800>, /* VDEC_TOP */ 1060 <0 0x16022000 0 0x1000>, /* VDEC_CM */ 1061 <0 0x16023000 0 0x1000>, /* VDEC_AD */ 1062 <0 0x16024000 0 0x1000>, /* VDEC_AV */ 1063 <0 0x16025000 0 0x1000>, /* VDEC_PP */ 1064 <0 0x16026800 0 0x800>, /* VDEC_HWD */ 1065 <0 0x16027000 0 0x800>, /* VDEC_HWQ */ 1066 <0 0x16027800 0 0x800>, /* VDEC_HWB */ 1067 <0 0x16028400 0 0x400>; /* VDEC_HWG */ 1068 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; 1069 mediatek,larb = <&larb1>; 1070 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, 1071 <&iommu M4U_PORT_HW_VDEC_PP_EXT>, 1072 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, 1073 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, 1074 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, 1075 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, 1076 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, 1077 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; 1078 mediatek,vpu = <&vpu>; 1079 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 1080 clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, 1081 <&topckgen CLK_TOP_UNIVPLL_D2>, 1082 <&topckgen CLK_TOP_CCI400_SEL>, 1083 <&topckgen CLK_TOP_VDEC_SEL>, 1084 <&topckgen CLK_TOP_VCODECPLL>, 1085 <&apmixedsys CLK_APMIXED_VENCPLL>, 1086 <&topckgen CLK_TOP_VENC_LT_SEL>, 1087 <&topckgen CLK_TOP_VCODECPLL_370P5>; 1088 clock-names = "vcodecpll", 1089 "univpll_d2", 1090 "clk_cci400_sel", 1091 "vdec_sel", 1092 "vdecpll", 1093 "vencpll", 1094 "venc_lt_sel", 1095 "vdec_bus_clk_src"; 1096 }; 1097 1098 larb1: larb@16010000 { 1099 compatible = "mediatek,mt8173-smi-larb"; 1100 reg = <0 0x16010000 0 0x1000>; 1101 mediatek,smi = <&smi_common>; 1102 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 1103 clocks = <&vdecsys CLK_VDEC_CKEN>, 1104 <&vdecsys CLK_VDEC_LARB_CKEN>; 1105 clock-names = "apb", "smi"; 1106 }; 1107 1108 vencsys: clock-controller@18000000 { 1109 compatible = "mediatek,mt8173-vencsys", "syscon"; 1110 reg = <0 0x18000000 0 0x1000>; 1111 #clock-cells = <1>; 1112 }; 1113 1114 larb3: larb@18001000 { 1115 compatible = "mediatek,mt8173-smi-larb"; 1116 reg = <0 0x18001000 0 0x1000>; 1117 mediatek,smi = <&smi_common>; 1118 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 1119 clocks = <&vencsys CLK_VENC_CKE1>, 1120 <&vencsys CLK_VENC_CKE0>; 1121 clock-names = "apb", "smi"; 1122 }; 1123 1124 vcodec_enc: vcodec@18002000 { 1125 compatible = "mediatek,mt8173-vcodec-enc"; 1126 reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */ 1127 <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ 1128 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>, 1129 <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; 1130 mediatek,larb = <&larb3>, 1131 <&larb5>; 1132 iommus = <&iommu M4U_PORT_VENC_RCPU>, 1133 <&iommu M4U_PORT_VENC_REC>, 1134 <&iommu M4U_PORT_VENC_BSDMA>, 1135 <&iommu M4U_PORT_VENC_SV_COMV>, 1136 <&iommu M4U_PORT_VENC_RD_COMV>, 1137 <&iommu M4U_PORT_VENC_CUR_LUMA>, 1138 <&iommu M4U_PORT_VENC_CUR_CHROMA>, 1139 <&iommu M4U_PORT_VENC_REF_LUMA>, 1140 <&iommu M4U_PORT_VENC_REF_CHROMA>, 1141 <&iommu M4U_PORT_VENC_NBM_RDMA>, 1142 <&iommu M4U_PORT_VENC_NBM_WDMA>, 1143 <&iommu M4U_PORT_VENC_RCPU_SET2>, 1144 <&iommu M4U_PORT_VENC_REC_FRM_SET2>, 1145 <&iommu M4U_PORT_VENC_BSDMA_SET2>, 1146 <&iommu M4U_PORT_VENC_SV_COMA_SET2>, 1147 <&iommu M4U_PORT_VENC_RD_COMA_SET2>, 1148 <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, 1149 <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, 1150 <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, 1151 <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; 1152 mediatek,vpu = <&vpu>; 1153 clocks = <&topckgen CLK_TOP_VENCPLL_D2>, 1154 <&topckgen CLK_TOP_VENC_SEL>, 1155 <&topckgen CLK_TOP_UNIVPLL1_D2>, 1156 <&topckgen CLK_TOP_VENC_LT_SEL>; 1157 clock-names = "venc_sel_src", 1158 "venc_sel", 1159 "venc_lt_sel_src", 1160 "venc_lt_sel"; 1161 }; 1162 1163 vencltsys: clock-controller@19000000 { 1164 compatible = "mediatek,mt8173-vencltsys", "syscon"; 1165 reg = <0 0x19000000 0 0x1000>; 1166 #clock-cells = <1>; 1167 }; 1168 1169 larb5: larb@19001000 { 1170 compatible = "mediatek,mt8173-smi-larb"; 1171 reg = <0 0x19001000 0 0x1000>; 1172 mediatek,smi = <&smi_common>; 1173 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; 1174 clocks = <&vencltsys CLK_VENCLT_CKE1>, 1175 <&vencltsys CLK_VENCLT_CKE0>; 1176 clock-names = "apb", "smi"; 1177 }; 1178 }; 1179}; 1180 1181