1/* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Eddie Huang <eddie.huang@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/clock/mt8173-clk.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/memory/mt8173-larb-port.h> 18#include <dt-bindings/phy/phy.h> 19#include <dt-bindings/power/mt8173-power.h> 20#include <dt-bindings/reset/mt8173-resets.h> 21#include "mt8173-pinfunc.h" 22 23/ { 24 compatible = "mediatek,mt8173"; 25 interrupt-parent = <&sysirq>; 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu-map { 34 cluster0 { 35 core0 { 36 cpu = <&cpu0>; 37 }; 38 core1 { 39 cpu = <&cpu1>; 40 }; 41 }; 42 43 cluster1 { 44 core0 { 45 cpu = <&cpu2>; 46 }; 47 core1 { 48 cpu = <&cpu3>; 49 }; 50 }; 51 }; 52 53 cpu0: cpu@0 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a53"; 56 reg = <0x000>; 57 enable-method = "psci"; 58 cpu-idle-states = <&CPU_SLEEP_0>; 59 }; 60 61 cpu1: cpu@1 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a53"; 64 reg = <0x001>; 65 enable-method = "psci"; 66 cpu-idle-states = <&CPU_SLEEP_0>; 67 }; 68 69 cpu2: cpu@100 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a57"; 72 reg = <0x100>; 73 enable-method = "psci"; 74 cpu-idle-states = <&CPU_SLEEP_0>; 75 }; 76 77 cpu3: cpu@101 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a57"; 80 reg = <0x101>; 81 enable-method = "psci"; 82 cpu-idle-states = <&CPU_SLEEP_0>; 83 }; 84 85 idle-states { 86 entry-method = "psci"; 87 88 CPU_SLEEP_0: cpu-sleep-0 { 89 compatible = "arm,idle-state"; 90 local-timer-stop; 91 entry-latency-us = <639>; 92 exit-latency-us = <680>; 93 min-residency-us = <1088>; 94 arm,psci-suspend-param = <0x0010000>; 95 }; 96 }; 97 }; 98 99 psci { 100 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 101 method = "smc"; 102 cpu_suspend = <0x84000001>; 103 cpu_off = <0x84000002>; 104 cpu_on = <0x84000003>; 105 }; 106 107 clk26m: oscillator@0 { 108 compatible = "fixed-clock"; 109 #clock-cells = <0>; 110 clock-frequency = <26000000>; 111 clock-output-names = "clk26m"; 112 }; 113 114 clk32k: oscillator@1 { 115 compatible = "fixed-clock"; 116 #clock-cells = <0>; 117 clock-frequency = <32000>; 118 clock-output-names = "clk32k"; 119 }; 120 121 cpum_ck: oscillator@2 { 122 compatible = "fixed-clock"; 123 #clock-cells = <0>; 124 clock-frequency = <0>; 125 clock-output-names = "cpum_ck"; 126 }; 127 128 timer { 129 compatible = "arm,armv8-timer"; 130 interrupt-parent = <&gic>; 131 interrupts = <GIC_PPI 13 132 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 133 <GIC_PPI 14 134 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 135 <GIC_PPI 11 136 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 137 <GIC_PPI 10 138 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 139 }; 140 141 soc { 142 #address-cells = <2>; 143 #size-cells = <2>; 144 compatible = "simple-bus"; 145 ranges; 146 147 topckgen: clock-controller@10000000 { 148 compatible = "mediatek,mt8173-topckgen"; 149 reg = <0 0x10000000 0 0x1000>; 150 #clock-cells = <1>; 151 }; 152 153 infracfg: power-controller@10001000 { 154 compatible = "mediatek,mt8173-infracfg", "syscon"; 155 reg = <0 0x10001000 0 0x1000>; 156 #clock-cells = <1>; 157 #reset-cells = <1>; 158 }; 159 160 pericfg: power-controller@10003000 { 161 compatible = "mediatek,mt8173-pericfg", "syscon"; 162 reg = <0 0x10003000 0 0x1000>; 163 #clock-cells = <1>; 164 #reset-cells = <1>; 165 }; 166 167 syscfg_pctl_a: syscfg_pctl_a@10005000 { 168 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 169 reg = <0 0x10005000 0 0x1000>; 170 }; 171 172 pio: pinctrl@0x10005000 { 173 compatible = "mediatek,mt8173-pinctrl"; 174 reg = <0 0x1000b000 0 0x1000>; 175 mediatek,pctl-regmap = <&syscfg_pctl_a>; 176 pins-are-numbered; 177 gpio-controller; 178 #gpio-cells = <2>; 179 interrupt-controller; 180 #interrupt-cells = <2>; 181 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 184 185 i2c0_pins_a: i2c0 { 186 pins1 { 187 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 188 <MT8173_PIN_46_SCL0__FUNC_SCL0>; 189 bias-disable; 190 }; 191 }; 192 193 i2c1_pins_a: i2c1 { 194 pins1 { 195 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 196 <MT8173_PIN_126_SCL1__FUNC_SCL1>; 197 bias-disable; 198 }; 199 }; 200 201 i2c2_pins_a: i2c2 { 202 pins1 { 203 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 204 <MT8173_PIN_44_SCL2__FUNC_SCL2>; 205 bias-disable; 206 }; 207 }; 208 209 i2c3_pins_a: i2c3 { 210 pins1 { 211 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 212 <MT8173_PIN_107_SCL3__FUNC_SCL3>; 213 bias-disable; 214 }; 215 }; 216 217 i2c4_pins_a: i2c4 { 218 pins1 { 219 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 220 <MT8173_PIN_134_SCL4__FUNC_SCL4>; 221 bias-disable; 222 }; 223 }; 224 225 i2c6_pins_a: i2c6 { 226 pins1 { 227 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 228 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 229 bias-disable; 230 }; 231 }; 232 }; 233 234 scpsys: scpsys@10006000 { 235 compatible = "mediatek,mt8173-scpsys"; 236 #power-domain-cells = <1>; 237 reg = <0 0x10006000 0 0x1000>; 238 clocks = <&clk26m>, 239 <&topckgen CLK_TOP_MM_SEL>, 240 <&topckgen CLK_TOP_VENC_SEL>, 241 <&topckgen CLK_TOP_VENC_LT_SEL>; 242 clock-names = "mfg", "mm", "venc", "venc_lt"; 243 infracfg = <&infracfg>; 244 }; 245 246 watchdog: watchdog@10007000 { 247 compatible = "mediatek,mt8173-wdt", 248 "mediatek,mt6589-wdt"; 249 reg = <0 0x10007000 0 0x100>; 250 }; 251 252 timer: timer@10008000 { 253 compatible = "mediatek,mt8173-timer", 254 "mediatek,mt6577-timer"; 255 reg = <0 0x10008000 0 0x1000>; 256 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 257 clocks = <&infracfg CLK_INFRA_CLK_13M>, 258 <&topckgen CLK_TOP_RTC_SEL>; 259 }; 260 261 pwrap: pwrap@1000d000 { 262 compatible = "mediatek,mt8173-pwrap"; 263 reg = <0 0x1000d000 0 0x1000>; 264 reg-names = "pwrap"; 265 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 266 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 267 reset-names = "pwrap"; 268 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 269 clock-names = "spi", "wrap"; 270 }; 271 272 sysirq: intpol-controller@10200620 { 273 compatible = "mediatek,mt8173-sysirq", 274 "mediatek,mt6577-sysirq"; 275 interrupt-controller; 276 #interrupt-cells = <3>; 277 interrupt-parent = <&gic>; 278 reg = <0 0x10200620 0 0x20>; 279 }; 280 281 iommu: iommu@10205000 { 282 compatible = "mediatek,mt8173-m4u"; 283 reg = <0 0x10205000 0 0x1000>; 284 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 285 clocks = <&infracfg CLK_INFRA_M4U>; 286 clock-names = "bclk"; 287 mediatek,larbs = <&larb0 &larb1 &larb2 288 &larb3 &larb4 &larb5>; 289 #iommu-cells = <1>; 290 }; 291 292 apmixedsys: clock-controller@10209000 { 293 compatible = "mediatek,mt8173-apmixedsys"; 294 reg = <0 0x10209000 0 0x1000>; 295 #clock-cells = <1>; 296 }; 297 298 gic: interrupt-controller@10220000 { 299 compatible = "arm,gic-400"; 300 #interrupt-cells = <3>; 301 interrupt-parent = <&gic>; 302 interrupt-controller; 303 reg = <0 0x10221000 0 0x1000>, 304 <0 0x10222000 0 0x2000>, 305 <0 0x10224000 0 0x2000>, 306 <0 0x10226000 0 0x2000>; 307 interrupts = <GIC_PPI 9 308 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 309 }; 310 311 uart0: serial@11002000 { 312 compatible = "mediatek,mt8173-uart", 313 "mediatek,mt6577-uart"; 314 reg = <0 0x11002000 0 0x400>; 315 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 316 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 317 clock-names = "baud", "bus"; 318 status = "disabled"; 319 }; 320 321 uart1: serial@11003000 { 322 compatible = "mediatek,mt8173-uart", 323 "mediatek,mt6577-uart"; 324 reg = <0 0x11003000 0 0x400>; 325 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 326 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 327 clock-names = "baud", "bus"; 328 status = "disabled"; 329 }; 330 331 uart2: serial@11004000 { 332 compatible = "mediatek,mt8173-uart", 333 "mediatek,mt6577-uart"; 334 reg = <0 0x11004000 0 0x400>; 335 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 336 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 337 clock-names = "baud", "bus"; 338 status = "disabled"; 339 }; 340 341 uart3: serial@11005000 { 342 compatible = "mediatek,mt8173-uart", 343 "mediatek,mt6577-uart"; 344 reg = <0 0x11005000 0 0x400>; 345 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 346 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 347 clock-names = "baud", "bus"; 348 status = "disabled"; 349 }; 350 351 i2c0: i2c@11007000 { 352 compatible = "mediatek,mt8173-i2c"; 353 reg = <0 0x11007000 0 0x70>, 354 <0 0x11000100 0 0x80>; 355 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 356 clock-div = <16>; 357 clocks = <&pericfg CLK_PERI_I2C0>, 358 <&pericfg CLK_PERI_AP_DMA>; 359 clock-names = "main", "dma"; 360 pinctrl-names = "default"; 361 pinctrl-0 = <&i2c0_pins_a>; 362 #address-cells = <1>; 363 #size-cells = <0>; 364 status = "disabled"; 365 }; 366 367 i2c1: i2c@11008000 { 368 compatible = "mediatek,mt8173-i2c"; 369 reg = <0 0x11008000 0 0x70>, 370 <0 0x11000180 0 0x80>; 371 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 372 clock-div = <16>; 373 clocks = <&pericfg CLK_PERI_I2C1>, 374 <&pericfg CLK_PERI_AP_DMA>; 375 clock-names = "main", "dma"; 376 pinctrl-names = "default"; 377 pinctrl-0 = <&i2c1_pins_a>; 378 #address-cells = <1>; 379 #size-cells = <0>; 380 status = "disabled"; 381 }; 382 383 i2c2: i2c@11009000 { 384 compatible = "mediatek,mt8173-i2c"; 385 reg = <0 0x11009000 0 0x70>, 386 <0 0x11000200 0 0x80>; 387 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 388 clock-div = <16>; 389 clocks = <&pericfg CLK_PERI_I2C2>, 390 <&pericfg CLK_PERI_AP_DMA>; 391 clock-names = "main", "dma"; 392 pinctrl-names = "default"; 393 pinctrl-0 = <&i2c2_pins_a>; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 status = "disabled"; 397 }; 398 399 spi: spi@1100a000 { 400 compatible = "mediatek,mt8173-spi"; 401 #address-cells = <1>; 402 #size-cells = <0>; 403 reg = <0 0x1100a000 0 0x1000>; 404 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 405 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 406 <&topckgen CLK_TOP_SPI_SEL>, 407 <&pericfg CLK_PERI_SPI0>; 408 clock-names = "parent-clk", "sel-clk", "spi-clk"; 409 status = "disabled"; 410 }; 411 412 i2c3: i2c@11010000 { 413 compatible = "mediatek,mt8173-i2c"; 414 reg = <0 0x11010000 0 0x70>, 415 <0 0x11000280 0 0x80>; 416 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 417 clock-div = <16>; 418 clocks = <&pericfg CLK_PERI_I2C3>, 419 <&pericfg CLK_PERI_AP_DMA>; 420 clock-names = "main", "dma"; 421 pinctrl-names = "default"; 422 pinctrl-0 = <&i2c3_pins_a>; 423 #address-cells = <1>; 424 #size-cells = <0>; 425 status = "disabled"; 426 }; 427 428 i2c4: i2c@11011000 { 429 compatible = "mediatek,mt8173-i2c"; 430 reg = <0 0x11011000 0 0x70>, 431 <0 0x11000300 0 0x80>; 432 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 433 clock-div = <16>; 434 clocks = <&pericfg CLK_PERI_I2C4>, 435 <&pericfg CLK_PERI_AP_DMA>; 436 clock-names = "main", "dma"; 437 pinctrl-names = "default"; 438 pinctrl-0 = <&i2c4_pins_a>; 439 #address-cells = <1>; 440 #size-cells = <0>; 441 status = "disabled"; 442 }; 443 444 i2c6: i2c@11013000 { 445 compatible = "mediatek,mt8173-i2c"; 446 reg = <0 0x11013000 0 0x70>, 447 <0 0x11000080 0 0x80>; 448 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 449 clock-div = <16>; 450 clocks = <&pericfg CLK_PERI_I2C6>, 451 <&pericfg CLK_PERI_AP_DMA>; 452 clock-names = "main", "dma"; 453 pinctrl-names = "default"; 454 pinctrl-0 = <&i2c6_pins_a>; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 status = "disabled"; 458 }; 459 460 afe: audio-controller@11220000 { 461 compatible = "mediatek,mt8173-afe-pcm"; 462 reg = <0 0x11220000 0 0x1000>; 463 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 464 power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; 465 clocks = <&infracfg CLK_INFRA_AUDIO>, 466 <&topckgen CLK_TOP_AUDIO_SEL>, 467 <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 468 <&topckgen CLK_TOP_APLL1_DIV0>, 469 <&topckgen CLK_TOP_APLL2_DIV0>, 470 <&topckgen CLK_TOP_I2S0_M_SEL>, 471 <&topckgen CLK_TOP_I2S1_M_SEL>, 472 <&topckgen CLK_TOP_I2S2_M_SEL>, 473 <&topckgen CLK_TOP_I2S3_M_SEL>, 474 <&topckgen CLK_TOP_I2S3_B_SEL>; 475 clock-names = "infra_sys_audio_clk", 476 "top_pdn_audio", 477 "top_pdn_aud_intbus", 478 "bck0", 479 "bck1", 480 "i2s0_m", 481 "i2s1_m", 482 "i2s2_m", 483 "i2s3_m", 484 "i2s3_b"; 485 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 486 <&topckgen CLK_TOP_AUD_2_SEL>; 487 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 488 <&topckgen CLK_TOP_APLL2>; 489 }; 490 491 mmc0: mmc@11230000 { 492 compatible = "mediatek,mt8173-mmc", 493 "mediatek,mt8135-mmc"; 494 reg = <0 0x11230000 0 0x1000>; 495 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 496 clocks = <&pericfg CLK_PERI_MSDC30_0>, 497 <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 498 clock-names = "source", "hclk"; 499 status = "disabled"; 500 }; 501 502 mmc1: mmc@11240000 { 503 compatible = "mediatek,mt8173-mmc", 504 "mediatek,mt8135-mmc"; 505 reg = <0 0x11240000 0 0x1000>; 506 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 507 clocks = <&pericfg CLK_PERI_MSDC30_1>, 508 <&topckgen CLK_TOP_AXI_SEL>; 509 clock-names = "source", "hclk"; 510 status = "disabled"; 511 }; 512 513 mmc2: mmc@11250000 { 514 compatible = "mediatek,mt8173-mmc", 515 "mediatek,mt8135-mmc"; 516 reg = <0 0x11250000 0 0x1000>; 517 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 518 clocks = <&pericfg CLK_PERI_MSDC30_2>, 519 <&topckgen CLK_TOP_AXI_SEL>; 520 clock-names = "source", "hclk"; 521 status = "disabled"; 522 }; 523 524 mmc3: mmc@11260000 { 525 compatible = "mediatek,mt8173-mmc", 526 "mediatek,mt8135-mmc"; 527 reg = <0 0x11260000 0 0x1000>; 528 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 529 clocks = <&pericfg CLK_PERI_MSDC30_3>, 530 <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 531 clock-names = "source", "hclk"; 532 status = "disabled"; 533 }; 534 535 usb30: usb@11270000 { 536 compatible = "mediatek,mt8173-xhci"; 537 reg = <0 0x11270000 0 0x1000>, 538 <0 0x11280700 0 0x0100>; 539 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 540 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 541 clocks = <&topckgen CLK_TOP_USB30_SEL>, 542 <&pericfg CLK_PERI_USB0>, 543 <&pericfg CLK_PERI_USB1>; 544 clock-names = "sys_ck", 545 "wakeup_deb_p0", 546 "wakeup_deb_p1"; 547 phys = <&phy_port0 PHY_TYPE_USB3>, 548 <&phy_port1 PHY_TYPE_USB2>; 549 mediatek,syscon-wakeup = <&pericfg>; 550 status = "okay"; 551 }; 552 553 u3phy: usb-phy@11290000 { 554 compatible = "mediatek,mt8173-u3phy"; 555 reg = <0 0x11290000 0 0x800>; 556 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 557 clock-names = "u3phya_ref"; 558 #address-cells = <2>; 559 #size-cells = <2>; 560 ranges; 561 status = "okay"; 562 563 phy_port0: port@11290800 { 564 reg = <0 0x11290800 0 0x800>; 565 #phy-cells = <1>; 566 status = "okay"; 567 }; 568 569 phy_port1: port@11291000 { 570 reg = <0 0x11291000 0 0x800>; 571 #phy-cells = <1>; 572 status = "okay"; 573 }; 574 }; 575 576 mmsys: clock-controller@14000000 { 577 compatible = "mediatek,mt8173-mmsys", "syscon"; 578 reg = <0 0x14000000 0 0x1000>; 579 #clock-cells = <1>; 580 }; 581 582 pwm0: pwm@1401e000 { 583 compatible = "mediatek,mt8173-disp-pwm", 584 "mediatek,mt6595-disp-pwm"; 585 reg = <0 0x1401e000 0 0x1000>; 586 #pwm-cells = <2>; 587 clocks = <&mmsys CLK_MM_DISP_PWM026M>, 588 <&mmsys CLK_MM_DISP_PWM0MM>; 589 clock-names = "main", "mm"; 590 status = "disabled"; 591 }; 592 593 pwm1: pwm@1401f000 { 594 compatible = "mediatek,mt8173-disp-pwm", 595 "mediatek,mt6595-disp-pwm"; 596 reg = <0 0x1401f000 0 0x1000>; 597 #pwm-cells = <2>; 598 clocks = <&mmsys CLK_MM_DISP_PWM126M>, 599 <&mmsys CLK_MM_DISP_PWM1MM>; 600 clock-names = "main", "mm"; 601 status = "disabled"; 602 }; 603 604 larb0: larb@14021000 { 605 compatible = "mediatek,mt8173-smi-larb"; 606 reg = <0 0x14021000 0 0x1000>; 607 mediatek,smi = <&smi_common>; 608 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 609 clocks = <&mmsys CLK_MM_SMI_LARB0>, 610 <&mmsys CLK_MM_SMI_LARB0>; 611 clock-names = "apb", "smi"; 612 }; 613 614 smi_common: smi@14022000 { 615 compatible = "mediatek,mt8173-smi-common"; 616 reg = <0 0x14022000 0 0x1000>; 617 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 618 clocks = <&mmsys CLK_MM_SMI_COMMON>, 619 <&mmsys CLK_MM_SMI_COMMON>; 620 clock-names = "apb", "smi"; 621 }; 622 623 larb4: larb@14027000 { 624 compatible = "mediatek,mt8173-smi-larb"; 625 reg = <0 0x14027000 0 0x1000>; 626 mediatek,smi = <&smi_common>; 627 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 628 clocks = <&mmsys CLK_MM_SMI_LARB4>, 629 <&mmsys CLK_MM_SMI_LARB4>; 630 clock-names = "apb", "smi"; 631 }; 632 633 imgsys: clock-controller@15000000 { 634 compatible = "mediatek,mt8173-imgsys", "syscon"; 635 reg = <0 0x15000000 0 0x1000>; 636 #clock-cells = <1>; 637 }; 638 639 larb2: larb@15001000 { 640 compatible = "mediatek,mt8173-smi-larb"; 641 reg = <0 0x15001000 0 0x1000>; 642 mediatek,smi = <&smi_common>; 643 power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>; 644 clocks = <&imgsys CLK_IMG_LARB2_SMI>, 645 <&imgsys CLK_IMG_LARB2_SMI>; 646 clock-names = "apb", "smi"; 647 }; 648 649 vdecsys: clock-controller@16000000 { 650 compatible = "mediatek,mt8173-vdecsys", "syscon"; 651 reg = <0 0x16000000 0 0x1000>; 652 #clock-cells = <1>; 653 }; 654 655 larb1: larb@16010000 { 656 compatible = "mediatek,mt8173-smi-larb"; 657 reg = <0 0x16010000 0 0x1000>; 658 mediatek,smi = <&smi_common>; 659 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 660 clocks = <&vdecsys CLK_VDEC_CKEN>, 661 <&vdecsys CLK_VDEC_LARB_CKEN>; 662 clock-names = "apb", "smi"; 663 }; 664 665 vencsys: clock-controller@18000000 { 666 compatible = "mediatek,mt8173-vencsys", "syscon"; 667 reg = <0 0x18000000 0 0x1000>; 668 #clock-cells = <1>; 669 }; 670 671 larb3: larb@18001000 { 672 compatible = "mediatek,mt8173-smi-larb"; 673 reg = <0 0x18001000 0 0x1000>; 674 mediatek,smi = <&smi_common>; 675 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 676 clocks = <&vencsys CLK_VENC_CKE1>, 677 <&vencsys CLK_VENC_CKE0>; 678 clock-names = "apb", "smi"; 679 }; 680 681 vencltsys: clock-controller@19000000 { 682 compatible = "mediatek,mt8173-vencltsys", "syscon"; 683 reg = <0 0x19000000 0 0x1000>; 684 #clock-cells = <1>; 685 }; 686 687 larb5: larb@19001000 { 688 compatible = "mediatek,mt8173-smi-larb"; 689 reg = <0 0x19001000 0 0x1000>; 690 mediatek,smi = <&smi_common>; 691 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; 692 clocks = <&vencltsys CLK_VENCLT_CKE1>, 693 <&vencltsys CLK_VENCLT_CKE0>; 694 clock-names = "apb", "smi"; 695 }; 696 }; 697}; 698 699