1/* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Eddie Huang <eddie.huang@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/clock/mt8173-clk.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/memory/mt8173-larb-port.h> 18#include <dt-bindings/phy/phy.h> 19#include <dt-bindings/power/mt8173-power.h> 20#include <dt-bindings/reset/mt8173-resets.h> 21#include "mt8173-pinfunc.h" 22 23/ { 24 compatible = "mediatek,mt8173"; 25 interrupt-parent = <&sysirq>; 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu-map { 34 cluster0 { 35 core0 { 36 cpu = <&cpu0>; 37 }; 38 core1 { 39 cpu = <&cpu1>; 40 }; 41 }; 42 43 cluster1 { 44 core0 { 45 cpu = <&cpu2>; 46 }; 47 core1 { 48 cpu = <&cpu3>; 49 }; 50 }; 51 }; 52 53 cpu0: cpu@0 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a53"; 56 reg = <0x000>; 57 enable-method = "psci"; 58 cpu-idle-states = <&CPU_SLEEP_0>; 59 }; 60 61 cpu1: cpu@1 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a53"; 64 reg = <0x001>; 65 enable-method = "psci"; 66 cpu-idle-states = <&CPU_SLEEP_0>; 67 }; 68 69 cpu2: cpu@100 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a57"; 72 reg = <0x100>; 73 enable-method = "psci"; 74 cpu-idle-states = <&CPU_SLEEP_0>; 75 }; 76 77 cpu3: cpu@101 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a57"; 80 reg = <0x101>; 81 enable-method = "psci"; 82 cpu-idle-states = <&CPU_SLEEP_0>; 83 }; 84 85 idle-states { 86 entry-method = "psci"; 87 88 CPU_SLEEP_0: cpu-sleep-0 { 89 compatible = "arm,idle-state"; 90 local-timer-stop; 91 entry-latency-us = <639>; 92 exit-latency-us = <680>; 93 min-residency-us = <1088>; 94 arm,psci-suspend-param = <0x0010000>; 95 }; 96 }; 97 }; 98 99 psci { 100 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 101 method = "smc"; 102 cpu_suspend = <0x84000001>; 103 cpu_off = <0x84000002>; 104 cpu_on = <0x84000003>; 105 }; 106 107 clk26m: oscillator@0 { 108 compatible = "fixed-clock"; 109 #clock-cells = <0>; 110 clock-frequency = <26000000>; 111 clock-output-names = "clk26m"; 112 }; 113 114 clk32k: oscillator@1 { 115 compatible = "fixed-clock"; 116 #clock-cells = <0>; 117 clock-frequency = <32000>; 118 clock-output-names = "clk32k"; 119 }; 120 121 cpum_ck: oscillator@2 { 122 compatible = "fixed-clock"; 123 #clock-cells = <0>; 124 clock-frequency = <0>; 125 clock-output-names = "cpum_ck"; 126 }; 127 128 thermal-zones { 129 cpu_thermal: cpu_thermal { 130 polling-delay-passive = <1000>; /* milliseconds */ 131 polling-delay = <1000>; /* milliseconds */ 132 133 thermal-sensors = <&thermal>; 134 sustainable-power = <1500>; /* milliwatts */ 135 136 trips { 137 threshold: trip-point@0 { 138 temperature = <68000>; 139 hysteresis = <2000>; 140 type = "passive"; 141 }; 142 143 target: trip-point@1 { 144 temperature = <85000>; 145 hysteresis = <2000>; 146 type = "passive"; 147 }; 148 149 cpu_crit: cpu_crit@0 { 150 temperature = <115000>; 151 hysteresis = <2000>; 152 type = "critical"; 153 }; 154 }; 155 156 cooling-maps { 157 map@0 { 158 trip = <&target>; 159 cooling-device = <&cpu0 0 0>; 160 contribution = <1024>; 161 }; 162 map@1 { 163 trip = <&target>; 164 cooling-device = <&cpu2 0 0>; 165 contribution = <2048>; 166 }; 167 }; 168 }; 169 }; 170 171 reserved-memory { 172 #address-cells = <2>; 173 #size-cells = <2>; 174 ranges; 175 vpu_dma_reserved: vpu_dma_mem_region { 176 compatible = "shared-dma-pool"; 177 reg = <0 0xb7000000 0 0x500000>; 178 alignment = <0x1000>; 179 no-map; 180 }; 181 }; 182 183 timer { 184 compatible = "arm,armv8-timer"; 185 interrupt-parent = <&gic>; 186 interrupts = <GIC_PPI 13 187 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 188 <GIC_PPI 14 189 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 190 <GIC_PPI 11 191 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 192 <GIC_PPI 10 193 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 194 }; 195 196 soc { 197 #address-cells = <2>; 198 #size-cells = <2>; 199 compatible = "simple-bus"; 200 ranges; 201 202 topckgen: clock-controller@10000000 { 203 compatible = "mediatek,mt8173-topckgen"; 204 reg = <0 0x10000000 0 0x1000>; 205 #clock-cells = <1>; 206 }; 207 208 infracfg: power-controller@10001000 { 209 compatible = "mediatek,mt8173-infracfg", "syscon"; 210 reg = <0 0x10001000 0 0x1000>; 211 #clock-cells = <1>; 212 #reset-cells = <1>; 213 }; 214 215 pericfg: power-controller@10003000 { 216 compatible = "mediatek,mt8173-pericfg", "syscon"; 217 reg = <0 0x10003000 0 0x1000>; 218 #clock-cells = <1>; 219 #reset-cells = <1>; 220 }; 221 222 syscfg_pctl_a: syscfg_pctl_a@10005000 { 223 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 224 reg = <0 0x10005000 0 0x1000>; 225 }; 226 227 pio: pinctrl@0x10005000 { 228 compatible = "mediatek,mt8173-pinctrl"; 229 reg = <0 0x1000b000 0 0x1000>; 230 mediatek,pctl-regmap = <&syscfg_pctl_a>; 231 pins-are-numbered; 232 gpio-controller; 233 #gpio-cells = <2>; 234 interrupt-controller; 235 #interrupt-cells = <2>; 236 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 239 240 i2c0_pins_a: i2c0 { 241 pins1 { 242 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 243 <MT8173_PIN_46_SCL0__FUNC_SCL0>; 244 bias-disable; 245 }; 246 }; 247 248 i2c1_pins_a: i2c1 { 249 pins1 { 250 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 251 <MT8173_PIN_126_SCL1__FUNC_SCL1>; 252 bias-disable; 253 }; 254 }; 255 256 i2c2_pins_a: i2c2 { 257 pins1 { 258 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 259 <MT8173_PIN_44_SCL2__FUNC_SCL2>; 260 bias-disable; 261 }; 262 }; 263 264 i2c3_pins_a: i2c3 { 265 pins1 { 266 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 267 <MT8173_PIN_107_SCL3__FUNC_SCL3>; 268 bias-disable; 269 }; 270 }; 271 272 i2c4_pins_a: i2c4 { 273 pins1 { 274 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 275 <MT8173_PIN_134_SCL4__FUNC_SCL4>; 276 bias-disable; 277 }; 278 }; 279 280 i2c6_pins_a: i2c6 { 281 pins1 { 282 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 283 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 284 bias-disable; 285 }; 286 }; 287 }; 288 289 scpsys: scpsys@10006000 { 290 compatible = "mediatek,mt8173-scpsys"; 291 #power-domain-cells = <1>; 292 reg = <0 0x10006000 0 0x1000>; 293 clocks = <&clk26m>, 294 <&topckgen CLK_TOP_MM_SEL>, 295 <&topckgen CLK_TOP_VENC_SEL>, 296 <&topckgen CLK_TOP_VENC_LT_SEL>; 297 clock-names = "mfg", "mm", "venc", "venc_lt"; 298 infracfg = <&infracfg>; 299 }; 300 301 watchdog: watchdog@10007000 { 302 compatible = "mediatek,mt8173-wdt", 303 "mediatek,mt6589-wdt"; 304 reg = <0 0x10007000 0 0x100>; 305 }; 306 307 timer: timer@10008000 { 308 compatible = "mediatek,mt8173-timer", 309 "mediatek,mt6577-timer"; 310 reg = <0 0x10008000 0 0x1000>; 311 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 312 clocks = <&infracfg CLK_INFRA_CLK_13M>, 313 <&topckgen CLK_TOP_RTC_SEL>; 314 }; 315 316 pwrap: pwrap@1000d000 { 317 compatible = "mediatek,mt8173-pwrap"; 318 reg = <0 0x1000d000 0 0x1000>; 319 reg-names = "pwrap"; 320 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 321 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 322 reset-names = "pwrap"; 323 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 324 clock-names = "spi", "wrap"; 325 }; 326 327 vpu: vpu@10020000 { 328 compatible = "mediatek,mt8173-vpu"; 329 reg = <0 0x10020000 0 0x30000>, 330 <0 0x10050000 0 0x100>; 331 reg-names = "tcm", "cfg_reg"; 332 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&topckgen CLK_TOP_SCP_SEL>; 334 clock-names = "main"; 335 memory-region = <&vpu_dma_reserved>; 336 }; 337 338 sysirq: intpol-controller@10200620 { 339 compatible = "mediatek,mt8173-sysirq", 340 "mediatek,mt6577-sysirq"; 341 interrupt-controller; 342 #interrupt-cells = <3>; 343 interrupt-parent = <&gic>; 344 reg = <0 0x10200620 0 0x20>; 345 }; 346 347 iommu: iommu@10205000 { 348 compatible = "mediatek,mt8173-m4u"; 349 reg = <0 0x10205000 0 0x1000>; 350 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 351 clocks = <&infracfg CLK_INFRA_M4U>; 352 clock-names = "bclk"; 353 mediatek,larbs = <&larb0 &larb1 &larb2 354 &larb3 &larb4 &larb5>; 355 #iommu-cells = <1>; 356 }; 357 358 efuse: efuse@10206000 { 359 compatible = "mediatek,mt8173-efuse"; 360 reg = <0 0x10206000 0 0x1000>; 361 }; 362 363 apmixedsys: clock-controller@10209000 { 364 compatible = "mediatek,mt8173-apmixedsys"; 365 reg = <0 0x10209000 0 0x1000>; 366 #clock-cells = <1>; 367 }; 368 369 gic: interrupt-controller@10220000 { 370 compatible = "arm,gic-400"; 371 #interrupt-cells = <3>; 372 interrupt-parent = <&gic>; 373 interrupt-controller; 374 reg = <0 0x10221000 0 0x1000>, 375 <0 0x10222000 0 0x2000>, 376 <0 0x10224000 0 0x2000>, 377 <0 0x10226000 0 0x2000>; 378 interrupts = <GIC_PPI 9 379 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 380 }; 381 382 auxadc: auxadc@11001000 { 383 compatible = "mediatek,mt8173-auxadc"; 384 reg = <0 0x11001000 0 0x1000>; 385 }; 386 387 uart0: serial@11002000 { 388 compatible = "mediatek,mt8173-uart", 389 "mediatek,mt6577-uart"; 390 reg = <0 0x11002000 0 0x400>; 391 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 392 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 393 clock-names = "baud", "bus"; 394 status = "disabled"; 395 }; 396 397 uart1: serial@11003000 { 398 compatible = "mediatek,mt8173-uart", 399 "mediatek,mt6577-uart"; 400 reg = <0 0x11003000 0 0x400>; 401 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 402 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 403 clock-names = "baud", "bus"; 404 status = "disabled"; 405 }; 406 407 uart2: serial@11004000 { 408 compatible = "mediatek,mt8173-uart", 409 "mediatek,mt6577-uart"; 410 reg = <0 0x11004000 0 0x400>; 411 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 412 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 413 clock-names = "baud", "bus"; 414 status = "disabled"; 415 }; 416 417 uart3: serial@11005000 { 418 compatible = "mediatek,mt8173-uart", 419 "mediatek,mt6577-uart"; 420 reg = <0 0x11005000 0 0x400>; 421 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 422 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 423 clock-names = "baud", "bus"; 424 status = "disabled"; 425 }; 426 427 i2c0: i2c@11007000 { 428 compatible = "mediatek,mt8173-i2c"; 429 reg = <0 0x11007000 0 0x70>, 430 <0 0x11000100 0 0x80>; 431 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 432 clock-div = <16>; 433 clocks = <&pericfg CLK_PERI_I2C0>, 434 <&pericfg CLK_PERI_AP_DMA>; 435 clock-names = "main", "dma"; 436 pinctrl-names = "default"; 437 pinctrl-0 = <&i2c0_pins_a>; 438 #address-cells = <1>; 439 #size-cells = <0>; 440 status = "disabled"; 441 }; 442 443 i2c1: i2c@11008000 { 444 compatible = "mediatek,mt8173-i2c"; 445 reg = <0 0x11008000 0 0x70>, 446 <0 0x11000180 0 0x80>; 447 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 448 clock-div = <16>; 449 clocks = <&pericfg CLK_PERI_I2C1>, 450 <&pericfg CLK_PERI_AP_DMA>; 451 clock-names = "main", "dma"; 452 pinctrl-names = "default"; 453 pinctrl-0 = <&i2c1_pins_a>; 454 #address-cells = <1>; 455 #size-cells = <0>; 456 status = "disabled"; 457 }; 458 459 i2c2: i2c@11009000 { 460 compatible = "mediatek,mt8173-i2c"; 461 reg = <0 0x11009000 0 0x70>, 462 <0 0x11000200 0 0x80>; 463 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 464 clock-div = <16>; 465 clocks = <&pericfg CLK_PERI_I2C2>, 466 <&pericfg CLK_PERI_AP_DMA>; 467 clock-names = "main", "dma"; 468 pinctrl-names = "default"; 469 pinctrl-0 = <&i2c2_pins_a>; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 status = "disabled"; 473 }; 474 475 spi: spi@1100a000 { 476 compatible = "mediatek,mt8173-spi"; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 reg = <0 0x1100a000 0 0x1000>; 480 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 481 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 482 <&topckgen CLK_TOP_SPI_SEL>, 483 <&pericfg CLK_PERI_SPI0>; 484 clock-names = "parent-clk", "sel-clk", "spi-clk"; 485 status = "disabled"; 486 }; 487 488 thermal: thermal@1100b000 { 489 #thermal-sensor-cells = <0>; 490 compatible = "mediatek,mt8173-thermal"; 491 reg = <0 0x1100b000 0 0x1000>; 492 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 493 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 494 clock-names = "therm", "auxadc"; 495 resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 496 mediatek,auxadc = <&auxadc>; 497 mediatek,apmixedsys = <&apmixedsys>; 498 }; 499 500 nor_flash: spi@1100d000 { 501 compatible = "mediatek,mt8173-nor"; 502 reg = <0 0x1100d000 0 0xe0>; 503 clocks = <&pericfg CLK_PERI_SPI>, 504 <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 505 clock-names = "spi", "sf"; 506 #address-cells = <1>; 507 #size-cells = <0>; 508 status = "disabled"; 509 }; 510 511 i2c3: i2c@11010000 { 512 compatible = "mediatek,mt8173-i2c"; 513 reg = <0 0x11010000 0 0x70>, 514 <0 0x11000280 0 0x80>; 515 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 516 clock-div = <16>; 517 clocks = <&pericfg CLK_PERI_I2C3>, 518 <&pericfg CLK_PERI_AP_DMA>; 519 clock-names = "main", "dma"; 520 pinctrl-names = "default"; 521 pinctrl-0 = <&i2c3_pins_a>; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 status = "disabled"; 525 }; 526 527 i2c4: i2c@11011000 { 528 compatible = "mediatek,mt8173-i2c"; 529 reg = <0 0x11011000 0 0x70>, 530 <0 0x11000300 0 0x80>; 531 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 532 clock-div = <16>; 533 clocks = <&pericfg CLK_PERI_I2C4>, 534 <&pericfg CLK_PERI_AP_DMA>; 535 clock-names = "main", "dma"; 536 pinctrl-names = "default"; 537 pinctrl-0 = <&i2c4_pins_a>; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 status = "disabled"; 541 }; 542 543 i2c6: i2c@11013000 { 544 compatible = "mediatek,mt8173-i2c"; 545 reg = <0 0x11013000 0 0x70>, 546 <0 0x11000080 0 0x80>; 547 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 548 clock-div = <16>; 549 clocks = <&pericfg CLK_PERI_I2C6>, 550 <&pericfg CLK_PERI_AP_DMA>; 551 clock-names = "main", "dma"; 552 pinctrl-names = "default"; 553 pinctrl-0 = <&i2c6_pins_a>; 554 #address-cells = <1>; 555 #size-cells = <0>; 556 status = "disabled"; 557 }; 558 559 afe: audio-controller@11220000 { 560 compatible = "mediatek,mt8173-afe-pcm"; 561 reg = <0 0x11220000 0 0x1000>; 562 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 563 power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; 564 clocks = <&infracfg CLK_INFRA_AUDIO>, 565 <&topckgen CLK_TOP_AUDIO_SEL>, 566 <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 567 <&topckgen CLK_TOP_APLL1_DIV0>, 568 <&topckgen CLK_TOP_APLL2_DIV0>, 569 <&topckgen CLK_TOP_I2S0_M_SEL>, 570 <&topckgen CLK_TOP_I2S1_M_SEL>, 571 <&topckgen CLK_TOP_I2S2_M_SEL>, 572 <&topckgen CLK_TOP_I2S3_M_SEL>, 573 <&topckgen CLK_TOP_I2S3_B_SEL>; 574 clock-names = "infra_sys_audio_clk", 575 "top_pdn_audio", 576 "top_pdn_aud_intbus", 577 "bck0", 578 "bck1", 579 "i2s0_m", 580 "i2s1_m", 581 "i2s2_m", 582 "i2s3_m", 583 "i2s3_b"; 584 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 585 <&topckgen CLK_TOP_AUD_2_SEL>; 586 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 587 <&topckgen CLK_TOP_APLL2>; 588 }; 589 590 mmc0: mmc@11230000 { 591 compatible = "mediatek,mt8173-mmc", 592 "mediatek,mt8135-mmc"; 593 reg = <0 0x11230000 0 0x1000>; 594 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 595 clocks = <&pericfg CLK_PERI_MSDC30_0>, 596 <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 597 clock-names = "source", "hclk"; 598 status = "disabled"; 599 }; 600 601 mmc1: mmc@11240000 { 602 compatible = "mediatek,mt8173-mmc", 603 "mediatek,mt8135-mmc"; 604 reg = <0 0x11240000 0 0x1000>; 605 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 606 clocks = <&pericfg CLK_PERI_MSDC30_1>, 607 <&topckgen CLK_TOP_AXI_SEL>; 608 clock-names = "source", "hclk"; 609 status = "disabled"; 610 }; 611 612 mmc2: mmc@11250000 { 613 compatible = "mediatek,mt8173-mmc", 614 "mediatek,mt8135-mmc"; 615 reg = <0 0x11250000 0 0x1000>; 616 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 617 clocks = <&pericfg CLK_PERI_MSDC30_2>, 618 <&topckgen CLK_TOP_AXI_SEL>; 619 clock-names = "source", "hclk"; 620 status = "disabled"; 621 }; 622 623 mmc3: mmc@11260000 { 624 compatible = "mediatek,mt8173-mmc", 625 "mediatek,mt8135-mmc"; 626 reg = <0 0x11260000 0 0x1000>; 627 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 628 clocks = <&pericfg CLK_PERI_MSDC30_3>, 629 <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 630 clock-names = "source", "hclk"; 631 status = "disabled"; 632 }; 633 634 usb30: usb@11270000 { 635 compatible = "mediatek,mt8173-xhci"; 636 reg = <0 0x11270000 0 0x1000>, 637 <0 0x11280700 0 0x0100>; 638 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 639 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 640 clocks = <&topckgen CLK_TOP_USB30_SEL>, 641 <&pericfg CLK_PERI_USB0>, 642 <&pericfg CLK_PERI_USB1>; 643 clock-names = "sys_ck", 644 "wakeup_deb_p0", 645 "wakeup_deb_p1"; 646 phys = <&phy_port0 PHY_TYPE_USB3>, 647 <&phy_port1 PHY_TYPE_USB2>; 648 mediatek,syscon-wakeup = <&pericfg>; 649 status = "okay"; 650 }; 651 652 u3phy: usb-phy@11290000 { 653 compatible = "mediatek,mt8173-u3phy"; 654 reg = <0 0x11290000 0 0x800>; 655 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 656 clock-names = "u3phya_ref"; 657 #address-cells = <2>; 658 #size-cells = <2>; 659 ranges; 660 status = "okay"; 661 662 phy_port0: port@11290800 { 663 reg = <0 0x11290800 0 0x800>; 664 #phy-cells = <1>; 665 status = "okay"; 666 }; 667 668 phy_port1: port@11291000 { 669 reg = <0 0x11291000 0 0x800>; 670 #phy-cells = <1>; 671 status = "okay"; 672 }; 673 }; 674 675 mmsys: clock-controller@14000000 { 676 compatible = "mediatek,mt8173-mmsys", "syscon"; 677 reg = <0 0x14000000 0 0x1000>; 678 #clock-cells = <1>; 679 }; 680 681 pwm0: pwm@1401e000 { 682 compatible = "mediatek,mt8173-disp-pwm", 683 "mediatek,mt6595-disp-pwm"; 684 reg = <0 0x1401e000 0 0x1000>; 685 #pwm-cells = <2>; 686 clocks = <&mmsys CLK_MM_DISP_PWM026M>, 687 <&mmsys CLK_MM_DISP_PWM0MM>; 688 clock-names = "main", "mm"; 689 status = "disabled"; 690 }; 691 692 pwm1: pwm@1401f000 { 693 compatible = "mediatek,mt8173-disp-pwm", 694 "mediatek,mt6595-disp-pwm"; 695 reg = <0 0x1401f000 0 0x1000>; 696 #pwm-cells = <2>; 697 clocks = <&mmsys CLK_MM_DISP_PWM126M>, 698 <&mmsys CLK_MM_DISP_PWM1MM>; 699 clock-names = "main", "mm"; 700 status = "disabled"; 701 }; 702 703 larb0: larb@14021000 { 704 compatible = "mediatek,mt8173-smi-larb"; 705 reg = <0 0x14021000 0 0x1000>; 706 mediatek,smi = <&smi_common>; 707 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 708 clocks = <&mmsys CLK_MM_SMI_LARB0>, 709 <&mmsys CLK_MM_SMI_LARB0>; 710 clock-names = "apb", "smi"; 711 }; 712 713 smi_common: smi@14022000 { 714 compatible = "mediatek,mt8173-smi-common"; 715 reg = <0 0x14022000 0 0x1000>; 716 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 717 clocks = <&mmsys CLK_MM_SMI_COMMON>, 718 <&mmsys CLK_MM_SMI_COMMON>; 719 clock-names = "apb", "smi"; 720 }; 721 722 larb4: larb@14027000 { 723 compatible = "mediatek,mt8173-smi-larb"; 724 reg = <0 0x14027000 0 0x1000>; 725 mediatek,smi = <&smi_common>; 726 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 727 clocks = <&mmsys CLK_MM_SMI_LARB4>, 728 <&mmsys CLK_MM_SMI_LARB4>; 729 clock-names = "apb", "smi"; 730 }; 731 732 imgsys: clock-controller@15000000 { 733 compatible = "mediatek,mt8173-imgsys", "syscon"; 734 reg = <0 0x15000000 0 0x1000>; 735 #clock-cells = <1>; 736 }; 737 738 larb2: larb@15001000 { 739 compatible = "mediatek,mt8173-smi-larb"; 740 reg = <0 0x15001000 0 0x1000>; 741 mediatek,smi = <&smi_common>; 742 power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>; 743 clocks = <&imgsys CLK_IMG_LARB2_SMI>, 744 <&imgsys CLK_IMG_LARB2_SMI>; 745 clock-names = "apb", "smi"; 746 }; 747 748 vdecsys: clock-controller@16000000 { 749 compatible = "mediatek,mt8173-vdecsys", "syscon"; 750 reg = <0 0x16000000 0 0x1000>; 751 #clock-cells = <1>; 752 }; 753 754 larb1: larb@16010000 { 755 compatible = "mediatek,mt8173-smi-larb"; 756 reg = <0 0x16010000 0 0x1000>; 757 mediatek,smi = <&smi_common>; 758 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 759 clocks = <&vdecsys CLK_VDEC_CKEN>, 760 <&vdecsys CLK_VDEC_LARB_CKEN>; 761 clock-names = "apb", "smi"; 762 }; 763 764 vencsys: clock-controller@18000000 { 765 compatible = "mediatek,mt8173-vencsys", "syscon"; 766 reg = <0 0x18000000 0 0x1000>; 767 #clock-cells = <1>; 768 }; 769 770 larb3: larb@18001000 { 771 compatible = "mediatek,mt8173-smi-larb"; 772 reg = <0 0x18001000 0 0x1000>; 773 mediatek,smi = <&smi_common>; 774 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 775 clocks = <&vencsys CLK_VENC_CKE1>, 776 <&vencsys CLK_VENC_CKE0>; 777 clock-names = "apb", "smi"; 778 }; 779 780 vencltsys: clock-controller@19000000 { 781 compatible = "mediatek,mt8173-vencltsys", "syscon"; 782 reg = <0 0x19000000 0 0x1000>; 783 #clock-cells = <1>; 784 }; 785 786 larb5: larb@19001000 { 787 compatible = "mediatek,mt8173-smi-larb"; 788 reg = <0 0x19001000 0 0x1000>; 789 mediatek,smi = <&smi_common>; 790 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; 791 clocks = <&vencltsys CLK_VENCLT_CKE1>, 792 <&vencltsys CLK_VENCLT_CKE0>; 793 clock-names = "apb", "smi"; 794 }; 795 }; 796}; 797 798