1/* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Eddie Huang <eddie.huang@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/clock/mt8173-clk.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/memory/mt8173-larb-port.h> 18#include <dt-bindings/phy/phy.h> 19#include <dt-bindings/power/mt8173-power.h> 20#include <dt-bindings/reset/mt8173-resets.h> 21#include <dt-bindings/gce/mt8173-gce.h> 22#include "mt8173-pinfunc.h" 23 24/ { 25 compatible = "mediatek,mt8173"; 26 interrupt-parent = <&sysirq>; 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 aliases { 31 ovl0 = &ovl0; 32 ovl1 = &ovl1; 33 rdma0 = &rdma0; 34 rdma1 = &rdma1; 35 rdma2 = &rdma2; 36 wdma0 = &wdma0; 37 wdma1 = &wdma1; 38 color0 = &color0; 39 color1 = &color1; 40 split0 = &split0; 41 split1 = &split1; 42 dpi0 = &dpi0; 43 dsi0 = &dsi0; 44 dsi1 = &dsi1; 45 mdp_rdma0 = &mdp_rdma0; 46 mdp_rdma1 = &mdp_rdma1; 47 mdp_rsz0 = &mdp_rsz0; 48 mdp_rsz1 = &mdp_rsz1; 49 mdp_rsz2 = &mdp_rsz2; 50 mdp_wdma0 = &mdp_wdma0; 51 mdp_wrot0 = &mdp_wrot0; 52 mdp_wrot1 = &mdp_wrot1; 53 }; 54 55 cluster0_opp: opp_table0 { 56 compatible = "operating-points-v2"; 57 opp-shared; 58 opp-507000000 { 59 opp-hz = /bits/ 64 <507000000>; 60 opp-microvolt = <859000>; 61 }; 62 opp-702000000 { 63 opp-hz = /bits/ 64 <702000000>; 64 opp-microvolt = <908000>; 65 }; 66 opp-1001000000 { 67 opp-hz = /bits/ 64 <1001000000>; 68 opp-microvolt = <983000>; 69 }; 70 opp-1105000000 { 71 opp-hz = /bits/ 64 <1105000000>; 72 opp-microvolt = <1009000>; 73 }; 74 opp-1209000000 { 75 opp-hz = /bits/ 64 <1209000000>; 76 opp-microvolt = <1034000>; 77 }; 78 opp-1300000000 { 79 opp-hz = /bits/ 64 <1300000000>; 80 opp-microvolt = <1057000>; 81 }; 82 opp-1508000000 { 83 opp-hz = /bits/ 64 <1508000000>; 84 opp-microvolt = <1109000>; 85 }; 86 opp-1703000000 { 87 opp-hz = /bits/ 64 <1703000000>; 88 opp-microvolt = <1125000>; 89 }; 90 }; 91 92 cluster1_opp: opp_table1 { 93 compatible = "operating-points-v2"; 94 opp-shared; 95 opp-507000000 { 96 opp-hz = /bits/ 64 <507000000>; 97 opp-microvolt = <828000>; 98 }; 99 opp-702000000 { 100 opp-hz = /bits/ 64 <702000000>; 101 opp-microvolt = <867000>; 102 }; 103 opp-1001000000 { 104 opp-hz = /bits/ 64 <1001000000>; 105 opp-microvolt = <927000>; 106 }; 107 opp-1209000000 { 108 opp-hz = /bits/ 64 <1209000000>; 109 opp-microvolt = <968000>; 110 }; 111 opp-1404000000 { 112 opp-hz = /bits/ 64 <1404000000>; 113 opp-microvolt = <1007000>; 114 }; 115 opp-1612000000 { 116 opp-hz = /bits/ 64 <1612000000>; 117 opp-microvolt = <1049000>; 118 }; 119 opp-1807000000 { 120 opp-hz = /bits/ 64 <1807000000>; 121 opp-microvolt = <1089000>; 122 }; 123 opp-2106000000 { 124 opp-hz = /bits/ 64 <2106000000>; 125 opp-microvolt = <1125000>; 126 }; 127 }; 128 129 cpus { 130 #address-cells = <1>; 131 #size-cells = <0>; 132 133 cpu-map { 134 cluster0 { 135 core0 { 136 cpu = <&cpu0>; 137 }; 138 core1 { 139 cpu = <&cpu1>; 140 }; 141 }; 142 143 cluster1 { 144 core0 { 145 cpu = <&cpu2>; 146 }; 147 core1 { 148 cpu = <&cpu3>; 149 }; 150 }; 151 }; 152 153 cpu0: cpu@0 { 154 device_type = "cpu"; 155 compatible = "arm,cortex-a53"; 156 reg = <0x000>; 157 enable-method = "psci"; 158 cpu-idle-states = <&CPU_SLEEP_0>; 159 #cooling-cells = <2>; 160 dynamic-power-coefficient = <263>; 161 clocks = <&infracfg CLK_INFRA_CA53SEL>, 162 <&apmixedsys CLK_APMIXED_MAINPLL>; 163 clock-names = "cpu", "intermediate"; 164 operating-points-v2 = <&cluster0_opp>; 165 }; 166 167 cpu1: cpu@1 { 168 device_type = "cpu"; 169 compatible = "arm,cortex-a53"; 170 reg = <0x001>; 171 enable-method = "psci"; 172 cpu-idle-states = <&CPU_SLEEP_0>; 173 #cooling-cells = <2>; 174 dynamic-power-coefficient = <263>; 175 clocks = <&infracfg CLK_INFRA_CA53SEL>, 176 <&apmixedsys CLK_APMIXED_MAINPLL>; 177 clock-names = "cpu", "intermediate"; 178 operating-points-v2 = <&cluster0_opp>; 179 }; 180 181 cpu2: cpu@100 { 182 device_type = "cpu"; 183 compatible = "arm,cortex-a72"; 184 reg = <0x100>; 185 enable-method = "psci"; 186 cpu-idle-states = <&CPU_SLEEP_0>; 187 #cooling-cells = <2>; 188 dynamic-power-coefficient = <530>; 189 clocks = <&infracfg CLK_INFRA_CA72SEL>, 190 <&apmixedsys CLK_APMIXED_MAINPLL>; 191 clock-names = "cpu", "intermediate"; 192 operating-points-v2 = <&cluster1_opp>; 193 }; 194 195 cpu3: cpu@101 { 196 device_type = "cpu"; 197 compatible = "arm,cortex-a72"; 198 reg = <0x101>; 199 enable-method = "psci"; 200 cpu-idle-states = <&CPU_SLEEP_0>; 201 #cooling-cells = <2>; 202 dynamic-power-coefficient = <530>; 203 clocks = <&infracfg CLK_INFRA_CA72SEL>, 204 <&apmixedsys CLK_APMIXED_MAINPLL>; 205 clock-names = "cpu", "intermediate"; 206 operating-points-v2 = <&cluster1_opp>; 207 }; 208 209 idle-states { 210 entry-method = "psci"; 211 212 CPU_SLEEP_0: cpu-sleep-0 { 213 compatible = "arm,idle-state"; 214 local-timer-stop; 215 entry-latency-us = <639>; 216 exit-latency-us = <680>; 217 min-residency-us = <1088>; 218 arm,psci-suspend-param = <0x0010000>; 219 }; 220 }; 221 }; 222 223 pmu_a53 { 224 compatible = "arm,cortex-a53-pmu"; 225 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, 226 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>; 227 interrupt-affinity = <&cpu0>, <&cpu1>; 228 }; 229 230 pmu_a72 { 231 compatible = "arm,cortex-a72-pmu"; 232 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>, 233 <GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>; 234 interrupt-affinity = <&cpu2>, <&cpu3>; 235 }; 236 237 psci { 238 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 239 method = "smc"; 240 cpu_suspend = <0x84000001>; 241 cpu_off = <0x84000002>; 242 cpu_on = <0x84000003>; 243 }; 244 245 clk26m: oscillator@0 { 246 compatible = "fixed-clock"; 247 #clock-cells = <0>; 248 clock-frequency = <26000000>; 249 clock-output-names = "clk26m"; 250 }; 251 252 clk32k: oscillator@1 { 253 compatible = "fixed-clock"; 254 #clock-cells = <0>; 255 clock-frequency = <32000>; 256 clock-output-names = "clk32k"; 257 }; 258 259 cpum_ck: oscillator@2 { 260 compatible = "fixed-clock"; 261 #clock-cells = <0>; 262 clock-frequency = <0>; 263 clock-output-names = "cpum_ck"; 264 }; 265 266 thermal-zones { 267 cpu_thermal: cpu_thermal { 268 polling-delay-passive = <1000>; /* milliseconds */ 269 polling-delay = <1000>; /* milliseconds */ 270 271 thermal-sensors = <&thermal>; 272 sustainable-power = <1500>; /* milliwatts */ 273 274 trips { 275 threshold: trip-point@0 { 276 temperature = <68000>; 277 hysteresis = <2000>; 278 type = "passive"; 279 }; 280 281 target: trip-point@1 { 282 temperature = <85000>; 283 hysteresis = <2000>; 284 type = "passive"; 285 }; 286 287 cpu_crit: cpu_crit@0 { 288 temperature = <115000>; 289 hysteresis = <2000>; 290 type = "critical"; 291 }; 292 }; 293 294 cooling-maps { 295 map@0 { 296 trip = <&target>; 297 cooling-device = <&cpu0 0 0>, 298 <&cpu1 0 0>; 299 contribution = <3072>; 300 }; 301 map@1 { 302 trip = <&target>; 303 cooling-device = <&cpu2 0 0>, 304 <&cpu3 0 0>; 305 contribution = <1024>; 306 }; 307 }; 308 }; 309 }; 310 311 reserved-memory { 312 #address-cells = <2>; 313 #size-cells = <2>; 314 ranges; 315 vpu_dma_reserved: vpu_dma_mem_region { 316 compatible = "shared-dma-pool"; 317 reg = <0 0xb7000000 0 0x500000>; 318 alignment = <0x1000>; 319 no-map; 320 }; 321 }; 322 323 timer { 324 compatible = "arm,armv8-timer"; 325 interrupt-parent = <&gic>; 326 interrupts = <GIC_PPI 13 327 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 328 <GIC_PPI 14 329 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 330 <GIC_PPI 11 331 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 332 <GIC_PPI 10 333 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 334 }; 335 336 soc { 337 #address-cells = <2>; 338 #size-cells = <2>; 339 compatible = "simple-bus"; 340 ranges; 341 342 topckgen: clock-controller@10000000 { 343 compatible = "mediatek,mt8173-topckgen"; 344 reg = <0 0x10000000 0 0x1000>; 345 #clock-cells = <1>; 346 }; 347 348 infracfg: power-controller@10001000 { 349 compatible = "mediatek,mt8173-infracfg", "syscon"; 350 reg = <0 0x10001000 0 0x1000>; 351 #clock-cells = <1>; 352 #reset-cells = <1>; 353 }; 354 355 pericfg: power-controller@10003000 { 356 compatible = "mediatek,mt8173-pericfg", "syscon"; 357 reg = <0 0x10003000 0 0x1000>; 358 #clock-cells = <1>; 359 #reset-cells = <1>; 360 }; 361 362 syscfg_pctl_a: syscfg_pctl_a@10005000 { 363 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 364 reg = <0 0x10005000 0 0x1000>; 365 }; 366 367 pio: pinctrl@10005000 { 368 compatible = "mediatek,mt8173-pinctrl"; 369 reg = <0 0x1000b000 0 0x1000>; 370 mediatek,pctl-regmap = <&syscfg_pctl_a>; 371 pins-are-numbered; 372 gpio-controller; 373 #gpio-cells = <2>; 374 interrupt-controller; 375 #interrupt-cells = <2>; 376 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 379 380 hdmi_pin: xxx { 381 382 /*hdmi htplg pin*/ 383 pins1 { 384 pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>; 385 input-enable; 386 bias-pull-down; 387 }; 388 }; 389 390 i2c0_pins_a: i2c0 { 391 pins1 { 392 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 393 <MT8173_PIN_46_SCL0__FUNC_SCL0>; 394 bias-disable; 395 }; 396 }; 397 398 i2c1_pins_a: i2c1 { 399 pins1 { 400 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 401 <MT8173_PIN_126_SCL1__FUNC_SCL1>; 402 bias-disable; 403 }; 404 }; 405 406 i2c2_pins_a: i2c2 { 407 pins1 { 408 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 409 <MT8173_PIN_44_SCL2__FUNC_SCL2>; 410 bias-disable; 411 }; 412 }; 413 414 i2c3_pins_a: i2c3 { 415 pins1 { 416 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 417 <MT8173_PIN_107_SCL3__FUNC_SCL3>; 418 bias-disable; 419 }; 420 }; 421 422 i2c4_pins_a: i2c4 { 423 pins1 { 424 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 425 <MT8173_PIN_134_SCL4__FUNC_SCL4>; 426 bias-disable; 427 }; 428 }; 429 430 i2c6_pins_a: i2c6 { 431 pins1 { 432 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 433 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 434 bias-disable; 435 }; 436 }; 437 }; 438 439 scpsys: scpsys@10006000 { 440 compatible = "mediatek,mt8173-scpsys"; 441 #power-domain-cells = <1>; 442 reg = <0 0x10006000 0 0x1000>; 443 clocks = <&clk26m>, 444 <&topckgen CLK_TOP_MM_SEL>, 445 <&topckgen CLK_TOP_VENC_SEL>, 446 <&topckgen CLK_TOP_VENC_LT_SEL>; 447 clock-names = "mfg", "mm", "venc", "venc_lt"; 448 infracfg = <&infracfg>; 449 }; 450 451 watchdog: watchdog@10007000 { 452 compatible = "mediatek,mt8173-wdt", 453 "mediatek,mt6589-wdt"; 454 reg = <0 0x10007000 0 0x100>; 455 }; 456 457 timer: timer@10008000 { 458 compatible = "mediatek,mt8173-timer", 459 "mediatek,mt6577-timer"; 460 reg = <0 0x10008000 0 0x1000>; 461 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 462 clocks = <&infracfg CLK_INFRA_CLK_13M>, 463 <&topckgen CLK_TOP_RTC_SEL>; 464 }; 465 466 pwrap: pwrap@1000d000 { 467 compatible = "mediatek,mt8173-pwrap"; 468 reg = <0 0x1000d000 0 0x1000>; 469 reg-names = "pwrap"; 470 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 471 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 472 reset-names = "pwrap"; 473 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 474 clock-names = "spi", "wrap"; 475 }; 476 477 cec: cec@10013000 { 478 compatible = "mediatek,mt8173-cec"; 479 reg = <0 0x10013000 0 0xbc>; 480 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; 481 clocks = <&infracfg CLK_INFRA_CEC>; 482 status = "disabled"; 483 }; 484 485 vpu: vpu@10020000 { 486 compatible = "mediatek,mt8173-vpu"; 487 reg = <0 0x10020000 0 0x30000>, 488 <0 0x10050000 0 0x100>; 489 reg-names = "tcm", "cfg_reg"; 490 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 491 clocks = <&topckgen CLK_TOP_SCP_SEL>; 492 clock-names = "main"; 493 memory-region = <&vpu_dma_reserved>; 494 }; 495 496 sysirq: intpol-controller@10200620 { 497 compatible = "mediatek,mt8173-sysirq", 498 "mediatek,mt6577-sysirq"; 499 interrupt-controller; 500 #interrupt-cells = <3>; 501 interrupt-parent = <&gic>; 502 reg = <0 0x10200620 0 0x20>; 503 }; 504 505 iommu: iommu@10205000 { 506 compatible = "mediatek,mt8173-m4u"; 507 reg = <0 0x10205000 0 0x1000>; 508 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 509 clocks = <&infracfg CLK_INFRA_M4U>; 510 clock-names = "bclk"; 511 mediatek,larbs = <&larb0 &larb1 &larb2 512 &larb3 &larb4 &larb5>; 513 #iommu-cells = <1>; 514 }; 515 516 efuse: efuse@10206000 { 517 compatible = "mediatek,mt8173-efuse"; 518 reg = <0 0x10206000 0 0x1000>; 519 #address-cells = <1>; 520 #size-cells = <1>; 521 thermal_calibration: calib@528 { 522 reg = <0x528 0xc>; 523 }; 524 }; 525 526 apmixedsys: clock-controller@10209000 { 527 compatible = "mediatek,mt8173-apmixedsys"; 528 reg = <0 0x10209000 0 0x1000>; 529 #clock-cells = <1>; 530 }; 531 532 hdmi_phy: hdmi-phy@10209100 { 533 compatible = "mediatek,mt8173-hdmi-phy"; 534 reg = <0 0x10209100 0 0x24>; 535 clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; 536 clock-names = "pll_ref"; 537 clock-output-names = "hdmitx_dig_cts"; 538 mediatek,ibias = <0xa>; 539 mediatek,ibias_up = <0x1c>; 540 #clock-cells = <0>; 541 #phy-cells = <0>; 542 status = "disabled"; 543 }; 544 545 gce: mailbox@10212000 { 546 compatible = "mediatek,mt8173-gce"; 547 reg = <0 0x10212000 0 0x1000>; 548 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 549 clocks = <&infracfg CLK_INFRA_GCE>; 550 clock-names = "gce"; 551 #mbox-cells = <3>; 552 }; 553 554 mipi_tx0: mipi-dphy@10215000 { 555 compatible = "mediatek,mt8173-mipi-tx"; 556 reg = <0 0x10215000 0 0x1000>; 557 clocks = <&clk26m>; 558 clock-output-names = "mipi_tx0_pll"; 559 #clock-cells = <0>; 560 #phy-cells = <0>; 561 status = "disabled"; 562 }; 563 564 mipi_tx1: mipi-dphy@10216000 { 565 compatible = "mediatek,mt8173-mipi-tx"; 566 reg = <0 0x10216000 0 0x1000>; 567 clocks = <&clk26m>; 568 clock-output-names = "mipi_tx1_pll"; 569 #clock-cells = <0>; 570 #phy-cells = <0>; 571 status = "disabled"; 572 }; 573 574 gic: interrupt-controller@10220000 { 575 compatible = "arm,gic-400"; 576 #interrupt-cells = <3>; 577 interrupt-parent = <&gic>; 578 interrupt-controller; 579 reg = <0 0x10221000 0 0x1000>, 580 <0 0x10222000 0 0x2000>, 581 <0 0x10224000 0 0x2000>, 582 <0 0x10226000 0 0x2000>; 583 interrupts = <GIC_PPI 9 584 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 585 }; 586 587 auxadc: auxadc@11001000 { 588 compatible = "mediatek,mt8173-auxadc"; 589 reg = <0 0x11001000 0 0x1000>; 590 clocks = <&pericfg CLK_PERI_AUXADC>; 591 clock-names = "main"; 592 #io-channel-cells = <1>; 593 }; 594 595 uart0: serial@11002000 { 596 compatible = "mediatek,mt8173-uart", 597 "mediatek,mt6577-uart"; 598 reg = <0 0x11002000 0 0x400>; 599 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 600 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 601 clock-names = "baud", "bus"; 602 status = "disabled"; 603 }; 604 605 uart1: serial@11003000 { 606 compatible = "mediatek,mt8173-uart", 607 "mediatek,mt6577-uart"; 608 reg = <0 0x11003000 0 0x400>; 609 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 610 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 611 clock-names = "baud", "bus"; 612 status = "disabled"; 613 }; 614 615 uart2: serial@11004000 { 616 compatible = "mediatek,mt8173-uart", 617 "mediatek,mt6577-uart"; 618 reg = <0 0x11004000 0 0x400>; 619 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 620 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 621 clock-names = "baud", "bus"; 622 status = "disabled"; 623 }; 624 625 uart3: serial@11005000 { 626 compatible = "mediatek,mt8173-uart", 627 "mediatek,mt6577-uart"; 628 reg = <0 0x11005000 0 0x400>; 629 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 630 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 631 clock-names = "baud", "bus"; 632 status = "disabled"; 633 }; 634 635 i2c0: i2c@11007000 { 636 compatible = "mediatek,mt8173-i2c"; 637 reg = <0 0x11007000 0 0x70>, 638 <0 0x11000100 0 0x80>; 639 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 640 clock-div = <16>; 641 clocks = <&pericfg CLK_PERI_I2C0>, 642 <&pericfg CLK_PERI_AP_DMA>; 643 clock-names = "main", "dma"; 644 pinctrl-names = "default"; 645 pinctrl-0 = <&i2c0_pins_a>; 646 #address-cells = <1>; 647 #size-cells = <0>; 648 status = "disabled"; 649 }; 650 651 i2c1: i2c@11008000 { 652 compatible = "mediatek,mt8173-i2c"; 653 reg = <0 0x11008000 0 0x70>, 654 <0 0x11000180 0 0x80>; 655 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 656 clock-div = <16>; 657 clocks = <&pericfg CLK_PERI_I2C1>, 658 <&pericfg CLK_PERI_AP_DMA>; 659 clock-names = "main", "dma"; 660 pinctrl-names = "default"; 661 pinctrl-0 = <&i2c1_pins_a>; 662 #address-cells = <1>; 663 #size-cells = <0>; 664 status = "disabled"; 665 }; 666 667 i2c2: i2c@11009000 { 668 compatible = "mediatek,mt8173-i2c"; 669 reg = <0 0x11009000 0 0x70>, 670 <0 0x11000200 0 0x80>; 671 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 672 clock-div = <16>; 673 clocks = <&pericfg CLK_PERI_I2C2>, 674 <&pericfg CLK_PERI_AP_DMA>; 675 clock-names = "main", "dma"; 676 pinctrl-names = "default"; 677 pinctrl-0 = <&i2c2_pins_a>; 678 #address-cells = <1>; 679 #size-cells = <0>; 680 status = "disabled"; 681 }; 682 683 spi: spi@1100a000 { 684 compatible = "mediatek,mt8173-spi"; 685 #address-cells = <1>; 686 #size-cells = <0>; 687 reg = <0 0x1100a000 0 0x1000>; 688 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 689 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 690 <&topckgen CLK_TOP_SPI_SEL>, 691 <&pericfg CLK_PERI_SPI0>; 692 clock-names = "parent-clk", "sel-clk", "spi-clk"; 693 status = "disabled"; 694 }; 695 696 thermal: thermal@1100b000 { 697 #thermal-sensor-cells = <0>; 698 compatible = "mediatek,mt8173-thermal"; 699 reg = <0 0x1100b000 0 0x1000>; 700 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 701 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 702 clock-names = "therm", "auxadc"; 703 resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 704 mediatek,auxadc = <&auxadc>; 705 mediatek,apmixedsys = <&apmixedsys>; 706 nvmem-cells = <&thermal_calibration>; 707 nvmem-cell-names = "calibration-data"; 708 }; 709 710 nor_flash: spi@1100d000 { 711 compatible = "mediatek,mt8173-nor"; 712 reg = <0 0x1100d000 0 0xe0>; 713 clocks = <&pericfg CLK_PERI_SPI>, 714 <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 715 clock-names = "spi", "sf"; 716 #address-cells = <1>; 717 #size-cells = <0>; 718 status = "disabled"; 719 }; 720 721 i2c3: i2c@11010000 { 722 compatible = "mediatek,mt8173-i2c"; 723 reg = <0 0x11010000 0 0x70>, 724 <0 0x11000280 0 0x80>; 725 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 726 clock-div = <16>; 727 clocks = <&pericfg CLK_PERI_I2C3>, 728 <&pericfg CLK_PERI_AP_DMA>; 729 clock-names = "main", "dma"; 730 pinctrl-names = "default"; 731 pinctrl-0 = <&i2c3_pins_a>; 732 #address-cells = <1>; 733 #size-cells = <0>; 734 status = "disabled"; 735 }; 736 737 i2c4: i2c@11011000 { 738 compatible = "mediatek,mt8173-i2c"; 739 reg = <0 0x11011000 0 0x70>, 740 <0 0x11000300 0 0x80>; 741 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 742 clock-div = <16>; 743 clocks = <&pericfg CLK_PERI_I2C4>, 744 <&pericfg CLK_PERI_AP_DMA>; 745 clock-names = "main", "dma"; 746 pinctrl-names = "default"; 747 pinctrl-0 = <&i2c4_pins_a>; 748 #address-cells = <1>; 749 #size-cells = <0>; 750 status = "disabled"; 751 }; 752 753 hdmiddc0: i2c@11012000 { 754 compatible = "mediatek,mt8173-hdmi-ddc"; 755 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 756 reg = <0 0x11012000 0 0x1C>; 757 clocks = <&pericfg CLK_PERI_I2C5>; 758 clock-names = "ddc-i2c"; 759 }; 760 761 i2c6: i2c@11013000 { 762 compatible = "mediatek,mt8173-i2c"; 763 reg = <0 0x11013000 0 0x70>, 764 <0 0x11000080 0 0x80>; 765 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 766 clock-div = <16>; 767 clocks = <&pericfg CLK_PERI_I2C6>, 768 <&pericfg CLK_PERI_AP_DMA>; 769 clock-names = "main", "dma"; 770 pinctrl-names = "default"; 771 pinctrl-0 = <&i2c6_pins_a>; 772 #address-cells = <1>; 773 #size-cells = <0>; 774 status = "disabled"; 775 }; 776 777 afe: audio-controller@11220000 { 778 compatible = "mediatek,mt8173-afe-pcm"; 779 reg = <0 0x11220000 0 0x1000>; 780 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 781 power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; 782 clocks = <&infracfg CLK_INFRA_AUDIO>, 783 <&topckgen CLK_TOP_AUDIO_SEL>, 784 <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 785 <&topckgen CLK_TOP_APLL1_DIV0>, 786 <&topckgen CLK_TOP_APLL2_DIV0>, 787 <&topckgen CLK_TOP_I2S0_M_SEL>, 788 <&topckgen CLK_TOP_I2S1_M_SEL>, 789 <&topckgen CLK_TOP_I2S2_M_SEL>, 790 <&topckgen CLK_TOP_I2S3_M_SEL>, 791 <&topckgen CLK_TOP_I2S3_B_SEL>; 792 clock-names = "infra_sys_audio_clk", 793 "top_pdn_audio", 794 "top_pdn_aud_intbus", 795 "bck0", 796 "bck1", 797 "i2s0_m", 798 "i2s1_m", 799 "i2s2_m", 800 "i2s3_m", 801 "i2s3_b"; 802 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 803 <&topckgen CLK_TOP_AUD_2_SEL>; 804 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 805 <&topckgen CLK_TOP_APLL2>; 806 }; 807 808 mmc0: mmc@11230000 { 809 compatible = "mediatek,mt8173-mmc"; 810 reg = <0 0x11230000 0 0x1000>; 811 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 812 clocks = <&pericfg CLK_PERI_MSDC30_0>, 813 <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 814 clock-names = "source", "hclk"; 815 status = "disabled"; 816 }; 817 818 mmc1: mmc@11240000 { 819 compatible = "mediatek,mt8173-mmc"; 820 reg = <0 0x11240000 0 0x1000>; 821 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 822 clocks = <&pericfg CLK_PERI_MSDC30_1>, 823 <&topckgen CLK_TOP_AXI_SEL>; 824 clock-names = "source", "hclk"; 825 status = "disabled"; 826 }; 827 828 mmc2: mmc@11250000 { 829 compatible = "mediatek,mt8173-mmc"; 830 reg = <0 0x11250000 0 0x1000>; 831 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 832 clocks = <&pericfg CLK_PERI_MSDC30_2>, 833 <&topckgen CLK_TOP_AXI_SEL>; 834 clock-names = "source", "hclk"; 835 status = "disabled"; 836 }; 837 838 mmc3: mmc@11260000 { 839 compatible = "mediatek,mt8173-mmc"; 840 reg = <0 0x11260000 0 0x1000>; 841 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 842 clocks = <&pericfg CLK_PERI_MSDC30_3>, 843 <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 844 clock-names = "source", "hclk"; 845 status = "disabled"; 846 }; 847 848 ssusb: usb@11271000 { 849 compatible = "mediatek,mt8173-mtu3"; 850 reg = <0 0x11271000 0 0x3000>, 851 <0 0x11280700 0 0x0100>; 852 reg-names = "mac", "ippc"; 853 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>; 854 phys = <&u2port0 PHY_TYPE_USB2>, 855 <&u3port0 PHY_TYPE_USB3>, 856 <&u2port1 PHY_TYPE_USB2>; 857 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 858 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 859 clock-names = "sys_ck", "ref_ck"; 860 mediatek,syscon-wakeup = <&pericfg 0x400 1>; 861 #address-cells = <2>; 862 #size-cells = <2>; 863 ranges; 864 status = "disabled"; 865 866 usb_host: xhci@11270000 { 867 compatible = "mediatek,mt8173-xhci"; 868 reg = <0 0x11270000 0 0x1000>; 869 reg-names = "mac"; 870 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 871 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 872 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 873 clock-names = "sys_ck", "ref_ck"; 874 status = "disabled"; 875 }; 876 }; 877 878 u3phy: usb-phy@11290000 { 879 compatible = "mediatek,mt8173-u3phy"; 880 reg = <0 0x11290000 0 0x800>; 881 #address-cells = <2>; 882 #size-cells = <2>; 883 ranges; 884 status = "okay"; 885 886 u2port0: usb-phy@11290800 { 887 reg = <0 0x11290800 0 0x100>; 888 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 889 clock-names = "ref"; 890 #phy-cells = <1>; 891 status = "okay"; 892 }; 893 894 u3port0: usb-phy@11290900 { 895 reg = <0 0x11290900 0 0x700>; 896 clocks = <&clk26m>; 897 clock-names = "ref"; 898 #phy-cells = <1>; 899 status = "okay"; 900 }; 901 902 u2port1: usb-phy@11291000 { 903 reg = <0 0x11291000 0 0x100>; 904 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 905 clock-names = "ref"; 906 #phy-cells = <1>; 907 status = "okay"; 908 }; 909 }; 910 911 mmsys: clock-controller@14000000 { 912 compatible = "mediatek,mt8173-mmsys", "syscon"; 913 reg = <0 0x14000000 0 0x1000>; 914 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 915 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; 916 assigned-clock-rates = <400000000>; 917 #clock-cells = <1>; 918 }; 919 920 mdp_rdma0: rdma@14001000 { 921 compatible = "mediatek,mt8173-mdp-rdma", 922 "mediatek,mt8173-mdp"; 923 reg = <0 0x14001000 0 0x1000>; 924 clocks = <&mmsys CLK_MM_MDP_RDMA0>, 925 <&mmsys CLK_MM_MUTEX_32K>; 926 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 927 iommus = <&iommu M4U_PORT_MDP_RDMA0>; 928 mediatek,larb = <&larb0>; 929 mediatek,vpu = <&vpu>; 930 }; 931 932 mdp_rdma1: rdma@14002000 { 933 compatible = "mediatek,mt8173-mdp-rdma"; 934 reg = <0 0x14002000 0 0x1000>; 935 clocks = <&mmsys CLK_MM_MDP_RDMA1>, 936 <&mmsys CLK_MM_MUTEX_32K>; 937 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 938 iommus = <&iommu M4U_PORT_MDP_RDMA1>; 939 mediatek,larb = <&larb4>; 940 }; 941 942 mdp_rsz0: rsz@14003000 { 943 compatible = "mediatek,mt8173-mdp-rsz"; 944 reg = <0 0x14003000 0 0x1000>; 945 clocks = <&mmsys CLK_MM_MDP_RSZ0>; 946 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 947 }; 948 949 mdp_rsz1: rsz@14004000 { 950 compatible = "mediatek,mt8173-mdp-rsz"; 951 reg = <0 0x14004000 0 0x1000>; 952 clocks = <&mmsys CLK_MM_MDP_RSZ1>; 953 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 954 }; 955 956 mdp_rsz2: rsz@14005000 { 957 compatible = "mediatek,mt8173-mdp-rsz"; 958 reg = <0 0x14005000 0 0x1000>; 959 clocks = <&mmsys CLK_MM_MDP_RSZ2>; 960 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 961 }; 962 963 mdp_wdma0: wdma@14006000 { 964 compatible = "mediatek,mt8173-mdp-wdma"; 965 reg = <0 0x14006000 0 0x1000>; 966 clocks = <&mmsys CLK_MM_MDP_WDMA>; 967 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 968 iommus = <&iommu M4U_PORT_MDP_WDMA>; 969 mediatek,larb = <&larb0>; 970 }; 971 972 mdp_wrot0: wrot@14007000 { 973 compatible = "mediatek,mt8173-mdp-wrot"; 974 reg = <0 0x14007000 0 0x1000>; 975 clocks = <&mmsys CLK_MM_MDP_WROT0>; 976 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 977 iommus = <&iommu M4U_PORT_MDP_WROT0>; 978 mediatek,larb = <&larb0>; 979 }; 980 981 mdp_wrot1: wrot@14008000 { 982 compatible = "mediatek,mt8173-mdp-wrot"; 983 reg = <0 0x14008000 0 0x1000>; 984 clocks = <&mmsys CLK_MM_MDP_WROT1>; 985 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 986 iommus = <&iommu M4U_PORT_MDP_WROT1>; 987 mediatek,larb = <&larb4>; 988 }; 989 990 ovl0: ovl@1400c000 { 991 compatible = "mediatek,mt8173-disp-ovl"; 992 reg = <0 0x1400c000 0 0x1000>; 993 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 994 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 995 clocks = <&mmsys CLK_MM_DISP_OVL0>; 996 iommus = <&iommu M4U_PORT_DISP_OVL0>; 997 mediatek,larb = <&larb0>; 998 }; 999 1000 ovl1: ovl@1400d000 { 1001 compatible = "mediatek,mt8173-disp-ovl"; 1002 reg = <0 0x1400d000 0 0x1000>; 1003 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; 1004 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1005 clocks = <&mmsys CLK_MM_DISP_OVL1>; 1006 iommus = <&iommu M4U_PORT_DISP_OVL1>; 1007 mediatek,larb = <&larb4>; 1008 }; 1009 1010 rdma0: rdma@1400e000 { 1011 compatible = "mediatek,mt8173-disp-rdma"; 1012 reg = <0 0x1400e000 0 0x1000>; 1013 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 1014 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1015 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1016 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 1017 mediatek,larb = <&larb0>; 1018 }; 1019 1020 rdma1: rdma@1400f000 { 1021 compatible = "mediatek,mt8173-disp-rdma"; 1022 reg = <0 0x1400f000 0 0x1000>; 1023 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; 1024 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1025 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 1026 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 1027 mediatek,larb = <&larb4>; 1028 }; 1029 1030 rdma2: rdma@14010000 { 1031 compatible = "mediatek,mt8173-disp-rdma"; 1032 reg = <0 0x14010000 0 0x1000>; 1033 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; 1034 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1035 clocks = <&mmsys CLK_MM_DISP_RDMA2>; 1036 iommus = <&iommu M4U_PORT_DISP_RDMA2>; 1037 mediatek,larb = <&larb4>; 1038 }; 1039 1040 wdma0: wdma@14011000 { 1041 compatible = "mediatek,mt8173-disp-wdma"; 1042 reg = <0 0x14011000 0 0x1000>; 1043 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 1044 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1045 clocks = <&mmsys CLK_MM_DISP_WDMA0>; 1046 iommus = <&iommu M4U_PORT_DISP_WDMA0>; 1047 mediatek,larb = <&larb0>; 1048 }; 1049 1050 wdma1: wdma@14012000 { 1051 compatible = "mediatek,mt8173-disp-wdma"; 1052 reg = <0 0x14012000 0 0x1000>; 1053 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; 1054 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1055 clocks = <&mmsys CLK_MM_DISP_WDMA1>; 1056 iommus = <&iommu M4U_PORT_DISP_WDMA1>; 1057 mediatek,larb = <&larb4>; 1058 }; 1059 1060 color0: color@14013000 { 1061 compatible = "mediatek,mt8173-disp-color"; 1062 reg = <0 0x14013000 0 0x1000>; 1063 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; 1064 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1065 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1066 }; 1067 1068 color1: color@14014000 { 1069 compatible = "mediatek,mt8173-disp-color"; 1070 reg = <0 0x14014000 0 0x1000>; 1071 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 1072 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1073 clocks = <&mmsys CLK_MM_DISP_COLOR1>; 1074 }; 1075 1076 aal@14015000 { 1077 compatible = "mediatek,mt8173-disp-aal"; 1078 reg = <0 0x14015000 0 0x1000>; 1079 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 1080 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1081 clocks = <&mmsys CLK_MM_DISP_AAL>; 1082 }; 1083 1084 gamma@14016000 { 1085 compatible = "mediatek,mt8173-disp-gamma"; 1086 reg = <0 0x14016000 0 0x1000>; 1087 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 1088 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1089 clocks = <&mmsys CLK_MM_DISP_GAMMA>; 1090 }; 1091 1092 merge@14017000 { 1093 compatible = "mediatek,mt8173-disp-merge"; 1094 reg = <0 0x14017000 0 0x1000>; 1095 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1096 clocks = <&mmsys CLK_MM_DISP_MERGE>; 1097 }; 1098 1099 split0: split@14018000 { 1100 compatible = "mediatek,mt8173-disp-split"; 1101 reg = <0 0x14018000 0 0x1000>; 1102 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1103 clocks = <&mmsys CLK_MM_DISP_SPLIT0>; 1104 }; 1105 1106 split1: split@14019000 { 1107 compatible = "mediatek,mt8173-disp-split"; 1108 reg = <0 0x14019000 0 0x1000>; 1109 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1110 clocks = <&mmsys CLK_MM_DISP_SPLIT1>; 1111 }; 1112 1113 ufoe@1401a000 { 1114 compatible = "mediatek,mt8173-disp-ufoe"; 1115 reg = <0 0x1401a000 0 0x1000>; 1116 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 1117 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1118 clocks = <&mmsys CLK_MM_DISP_UFOE>; 1119 }; 1120 1121 dsi0: dsi@1401b000 { 1122 compatible = "mediatek,mt8173-dsi"; 1123 reg = <0 0x1401b000 0 0x1000>; 1124 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 1125 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1126 clocks = <&mmsys CLK_MM_DSI0_ENGINE>, 1127 <&mmsys CLK_MM_DSI0_DIGITAL>, 1128 <&mipi_tx0>; 1129 clock-names = "engine", "digital", "hs"; 1130 phys = <&mipi_tx0>; 1131 phy-names = "dphy"; 1132 status = "disabled"; 1133 }; 1134 1135 dsi1: dsi@1401c000 { 1136 compatible = "mediatek,mt8173-dsi"; 1137 reg = <0 0x1401c000 0 0x1000>; 1138 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 1139 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1140 clocks = <&mmsys CLK_MM_DSI1_ENGINE>, 1141 <&mmsys CLK_MM_DSI1_DIGITAL>, 1142 <&mipi_tx1>; 1143 clock-names = "engine", "digital", "hs"; 1144 phy = <&mipi_tx1>; 1145 phy-names = "dphy"; 1146 status = "disabled"; 1147 }; 1148 1149 dpi0: dpi@1401d000 { 1150 compatible = "mediatek,mt8173-dpi"; 1151 reg = <0 0x1401d000 0 0x1000>; 1152 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 1153 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1154 clocks = <&mmsys CLK_MM_DPI_PIXEL>, 1155 <&mmsys CLK_MM_DPI_ENGINE>, 1156 <&apmixedsys CLK_APMIXED_TVDPLL>; 1157 clock-names = "pixel", "engine", "pll"; 1158 status = "disabled"; 1159 1160 port { 1161 dpi0_out: endpoint { 1162 remote-endpoint = <&hdmi0_in>; 1163 }; 1164 }; 1165 }; 1166 1167 pwm0: pwm@1401e000 { 1168 compatible = "mediatek,mt8173-disp-pwm", 1169 "mediatek,mt6595-disp-pwm"; 1170 reg = <0 0x1401e000 0 0x1000>; 1171 #pwm-cells = <2>; 1172 clocks = <&mmsys CLK_MM_DISP_PWM026M>, 1173 <&mmsys CLK_MM_DISP_PWM0MM>; 1174 clock-names = "main", "mm"; 1175 status = "disabled"; 1176 }; 1177 1178 pwm1: pwm@1401f000 { 1179 compatible = "mediatek,mt8173-disp-pwm", 1180 "mediatek,mt6595-disp-pwm"; 1181 reg = <0 0x1401f000 0 0x1000>; 1182 #pwm-cells = <2>; 1183 clocks = <&mmsys CLK_MM_DISP_PWM126M>, 1184 <&mmsys CLK_MM_DISP_PWM1MM>; 1185 clock-names = "main", "mm"; 1186 status = "disabled"; 1187 }; 1188 1189 mutex: mutex@14020000 { 1190 compatible = "mediatek,mt8173-disp-mutex"; 1191 reg = <0 0x14020000 0 0x1000>; 1192 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 1193 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1194 clocks = <&mmsys CLK_MM_MUTEX_32K>; 1195 }; 1196 1197 larb0: larb@14021000 { 1198 compatible = "mediatek,mt8173-smi-larb"; 1199 reg = <0 0x14021000 0 0x1000>; 1200 mediatek,smi = <&smi_common>; 1201 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1202 clocks = <&mmsys CLK_MM_SMI_LARB0>, 1203 <&mmsys CLK_MM_SMI_LARB0>; 1204 clock-names = "apb", "smi"; 1205 }; 1206 1207 smi_common: smi@14022000 { 1208 compatible = "mediatek,mt8173-smi-common"; 1209 reg = <0 0x14022000 0 0x1000>; 1210 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1211 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1212 <&mmsys CLK_MM_SMI_COMMON>; 1213 clock-names = "apb", "smi"; 1214 }; 1215 1216 od@14023000 { 1217 compatible = "mediatek,mt8173-disp-od"; 1218 reg = <0 0x14023000 0 0x1000>; 1219 clocks = <&mmsys CLK_MM_DISP_OD>; 1220 }; 1221 1222 hdmi0: hdmi@14025000 { 1223 compatible = "mediatek,mt8173-hdmi"; 1224 reg = <0 0x14025000 0 0x400>; 1225 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>; 1226 clocks = <&mmsys CLK_MM_HDMI_PIXEL>, 1227 <&mmsys CLK_MM_HDMI_PLLCK>, 1228 <&mmsys CLK_MM_HDMI_AUDIO>, 1229 <&mmsys CLK_MM_HDMI_SPDIF>; 1230 clock-names = "pixel", "pll", "bclk", "spdif"; 1231 pinctrl-names = "default"; 1232 pinctrl-0 = <&hdmi_pin>; 1233 phys = <&hdmi_phy>; 1234 phy-names = "hdmi"; 1235 mediatek,syscon-hdmi = <&mmsys 0x900>; 1236 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; 1237 assigned-clock-parents = <&hdmi_phy>; 1238 status = "disabled"; 1239 1240 ports { 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 1244 port@0 { 1245 reg = <0>; 1246 1247 hdmi0_in: endpoint { 1248 remote-endpoint = <&dpi0_out>; 1249 }; 1250 }; 1251 }; 1252 }; 1253 1254 larb4: larb@14027000 { 1255 compatible = "mediatek,mt8173-smi-larb"; 1256 reg = <0 0x14027000 0 0x1000>; 1257 mediatek,smi = <&smi_common>; 1258 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1259 clocks = <&mmsys CLK_MM_SMI_LARB4>, 1260 <&mmsys CLK_MM_SMI_LARB4>; 1261 clock-names = "apb", "smi"; 1262 }; 1263 1264 imgsys: clock-controller@15000000 { 1265 compatible = "mediatek,mt8173-imgsys", "syscon"; 1266 reg = <0 0x15000000 0 0x1000>; 1267 #clock-cells = <1>; 1268 }; 1269 1270 larb2: larb@15001000 { 1271 compatible = "mediatek,mt8173-smi-larb"; 1272 reg = <0 0x15001000 0 0x1000>; 1273 mediatek,smi = <&smi_common>; 1274 power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>; 1275 clocks = <&imgsys CLK_IMG_LARB2_SMI>, 1276 <&imgsys CLK_IMG_LARB2_SMI>; 1277 clock-names = "apb", "smi"; 1278 }; 1279 1280 vdecsys: clock-controller@16000000 { 1281 compatible = "mediatek,mt8173-vdecsys", "syscon"; 1282 reg = <0 0x16000000 0 0x1000>; 1283 #clock-cells = <1>; 1284 }; 1285 1286 vcodec_dec: vcodec@16000000 { 1287 compatible = "mediatek,mt8173-vcodec-dec"; 1288 reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */ 1289 <0 0x16020000 0 0x1000>, /* VDEC_MISC */ 1290 <0 0x16021000 0 0x800>, /* VDEC_LD */ 1291 <0 0x16021800 0 0x800>, /* VDEC_TOP */ 1292 <0 0x16022000 0 0x1000>, /* VDEC_CM */ 1293 <0 0x16023000 0 0x1000>, /* VDEC_AD */ 1294 <0 0x16024000 0 0x1000>, /* VDEC_AV */ 1295 <0 0x16025000 0 0x1000>, /* VDEC_PP */ 1296 <0 0x16026800 0 0x800>, /* VDEC_HWD */ 1297 <0 0x16027000 0 0x800>, /* VDEC_HWQ */ 1298 <0 0x16027800 0 0x800>, /* VDEC_HWB */ 1299 <0 0x16028400 0 0x400>; /* VDEC_HWG */ 1300 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; 1301 mediatek,larb = <&larb1>; 1302 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, 1303 <&iommu M4U_PORT_HW_VDEC_PP_EXT>, 1304 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, 1305 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, 1306 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, 1307 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, 1308 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, 1309 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; 1310 mediatek,vpu = <&vpu>; 1311 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 1312 clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, 1313 <&topckgen CLK_TOP_UNIVPLL_D2>, 1314 <&topckgen CLK_TOP_CCI400_SEL>, 1315 <&topckgen CLK_TOP_VDEC_SEL>, 1316 <&topckgen CLK_TOP_VCODECPLL>, 1317 <&apmixedsys CLK_APMIXED_VENCPLL>, 1318 <&topckgen CLK_TOP_VENC_LT_SEL>, 1319 <&topckgen CLK_TOP_VCODECPLL_370P5>; 1320 clock-names = "vcodecpll", 1321 "univpll_d2", 1322 "clk_cci400_sel", 1323 "vdec_sel", 1324 "vdecpll", 1325 "vencpll", 1326 "venc_lt_sel", 1327 "vdec_bus_clk_src"; 1328 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>, 1329 <&topckgen CLK_TOP_CCI400_SEL>, 1330 <&topckgen CLK_TOP_VDEC_SEL>, 1331 <&apmixedsys CLK_APMIXED_VCODECPLL>, 1332 <&apmixedsys CLK_APMIXED_VENCPLL>; 1333 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>, 1334 <&topckgen CLK_TOP_UNIVPLL_D2>, 1335 <&topckgen CLK_TOP_VCODECPLL>; 1336 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>; 1337 }; 1338 1339 larb1: larb@16010000 { 1340 compatible = "mediatek,mt8173-smi-larb"; 1341 reg = <0 0x16010000 0 0x1000>; 1342 mediatek,smi = <&smi_common>; 1343 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 1344 clocks = <&vdecsys CLK_VDEC_CKEN>, 1345 <&vdecsys CLK_VDEC_LARB_CKEN>; 1346 clock-names = "apb", "smi"; 1347 }; 1348 1349 vencsys: clock-controller@18000000 { 1350 compatible = "mediatek,mt8173-vencsys", "syscon"; 1351 reg = <0 0x18000000 0 0x1000>; 1352 #clock-cells = <1>; 1353 }; 1354 1355 larb3: larb@18001000 { 1356 compatible = "mediatek,mt8173-smi-larb"; 1357 reg = <0 0x18001000 0 0x1000>; 1358 mediatek,smi = <&smi_common>; 1359 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 1360 clocks = <&vencsys CLK_VENC_CKE1>, 1361 <&vencsys CLK_VENC_CKE0>; 1362 clock-names = "apb", "smi"; 1363 }; 1364 1365 vcodec_enc: vcodec@18002000 { 1366 compatible = "mediatek,mt8173-vcodec-enc"; 1367 reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */ 1368 <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ 1369 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>, 1370 <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; 1371 mediatek,larb = <&larb3>, 1372 <&larb5>; 1373 iommus = <&iommu M4U_PORT_VENC_RCPU>, 1374 <&iommu M4U_PORT_VENC_REC>, 1375 <&iommu M4U_PORT_VENC_BSDMA>, 1376 <&iommu M4U_PORT_VENC_SV_COMV>, 1377 <&iommu M4U_PORT_VENC_RD_COMV>, 1378 <&iommu M4U_PORT_VENC_CUR_LUMA>, 1379 <&iommu M4U_PORT_VENC_CUR_CHROMA>, 1380 <&iommu M4U_PORT_VENC_REF_LUMA>, 1381 <&iommu M4U_PORT_VENC_REF_CHROMA>, 1382 <&iommu M4U_PORT_VENC_NBM_RDMA>, 1383 <&iommu M4U_PORT_VENC_NBM_WDMA>, 1384 <&iommu M4U_PORT_VENC_RCPU_SET2>, 1385 <&iommu M4U_PORT_VENC_REC_FRM_SET2>, 1386 <&iommu M4U_PORT_VENC_BSDMA_SET2>, 1387 <&iommu M4U_PORT_VENC_SV_COMA_SET2>, 1388 <&iommu M4U_PORT_VENC_RD_COMA_SET2>, 1389 <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, 1390 <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, 1391 <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, 1392 <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; 1393 mediatek,vpu = <&vpu>; 1394 clocks = <&topckgen CLK_TOP_VENCPLL_D2>, 1395 <&topckgen CLK_TOP_VENC_SEL>, 1396 <&topckgen CLK_TOP_UNIVPLL1_D2>, 1397 <&topckgen CLK_TOP_VENC_LT_SEL>; 1398 clock-names = "venc_sel_src", 1399 "venc_sel", 1400 "venc_lt_sel_src", 1401 "venc_lt_sel"; 1402 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>, 1403 <&topckgen CLK_TOP_VENC_LT_SEL>; 1404 assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>, 1405 <&topckgen CLK_TOP_UNIVPLL1_D2>; 1406 }; 1407 1408 vencltsys: clock-controller@19000000 { 1409 compatible = "mediatek,mt8173-vencltsys", "syscon"; 1410 reg = <0 0x19000000 0 0x1000>; 1411 #clock-cells = <1>; 1412 }; 1413 1414 larb5: larb@19001000 { 1415 compatible = "mediatek,mt8173-smi-larb"; 1416 reg = <0 0x19001000 0 0x1000>; 1417 mediatek,smi = <&smi_common>; 1418 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; 1419 clocks = <&vencltsys CLK_VENCLT_CKE1>, 1420 <&vencltsys CLK_VENCLT_CKE0>; 1421 clock-names = "apb", "smi"; 1422 }; 1423 }; 1424}; 1425 1426