1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Eddie Huang <eddie.huang@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11 * GNU General Public License for more details.
12 */
13
14#include <dt-bindings/clock/mt8173-clk.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/interrupt-controller/arm-gic.h>
17#include <dt-bindings/reset-controller/mt8173-resets.h>
18#include "mt8173-pinfunc.h"
19
20/ {
21	compatible = "mediatek,mt8173";
22	interrupt-parent = <&sysirq>;
23	#address-cells = <2>;
24	#size-cells = <2>;
25
26	cpus {
27		#address-cells = <1>;
28		#size-cells = <0>;
29
30		cpu-map {
31			cluster0 {
32				core0 {
33					cpu = <&cpu0>;
34				};
35				core1 {
36					cpu = <&cpu1>;
37				};
38			};
39
40			cluster1 {
41				core0 {
42					cpu = <&cpu2>;
43				};
44				core1 {
45					cpu = <&cpu3>;
46				};
47			};
48		};
49
50		cpu0: cpu@0 {
51			device_type = "cpu";
52			compatible = "arm,cortex-a53";
53			reg = <0x000>;
54		};
55
56		cpu1: cpu@1 {
57			device_type = "cpu";
58			compatible = "arm,cortex-a53";
59			reg = <0x001>;
60			enable-method = "psci";
61		};
62
63		cpu2: cpu@100 {
64			device_type = "cpu";
65			compatible = "arm,cortex-a57";
66			reg = <0x100>;
67			enable-method = "psci";
68		};
69
70		cpu3: cpu@101 {
71			device_type = "cpu";
72			compatible = "arm,cortex-a57";
73			reg = <0x101>;
74			enable-method = "psci";
75		};
76	};
77
78	psci {
79		compatible = "arm,psci";
80		method = "smc";
81		cpu_suspend   = <0x84000001>;
82		cpu_off	      = <0x84000002>;
83		cpu_on	      = <0x84000003>;
84	};
85
86	clk26m: oscillator@0 {
87		compatible = "fixed-clock";
88		#clock-cells = <0>;
89		clock-frequency = <26000000>;
90		clock-output-names = "clk26m";
91	};
92
93	clk32k: oscillator@1 {
94		compatible = "fixed-clock";
95		#clock-cells = <0>;
96		clock-frequency = <32000>;
97		clock-output-names = "clk32k";
98	};
99
100	timer {
101		compatible = "arm,armv8-timer";
102		interrupt-parent = <&gic>;
103		interrupts = <GIC_PPI 13
104			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
105			     <GIC_PPI 14
106			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
107			     <GIC_PPI 11
108			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
109			     <GIC_PPI 10
110			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
111	};
112
113	soc {
114		#address-cells = <2>;
115		#size-cells = <2>;
116		compatible = "simple-bus";
117		ranges;
118
119		topckgen: clock-controller@10000000 {
120			compatible = "mediatek,mt8173-topckgen";
121			reg = <0 0x10000000 0 0x1000>;
122			#clock-cells = <1>;
123		};
124
125		infracfg: power-controller@10001000 {
126			compatible = "mediatek,mt8173-infracfg", "syscon";
127			reg = <0 0x10001000 0 0x1000>;
128			#clock-cells = <1>;
129			#reset-cells = <1>;
130		};
131
132		pericfg: power-controller@10003000 {
133			compatible = "mediatek,mt8173-pericfg", "syscon";
134			reg = <0 0x10003000 0 0x1000>;
135			#clock-cells = <1>;
136			#reset-cells = <1>;
137		};
138
139		syscfg_pctl_a: syscfg_pctl_a@10005000 {
140			compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
141			reg = <0 0x10005000 0 0x1000>;
142		};
143
144		pio: pinctrl@0x10005000 {
145			compatible = "mediatek,mt8173-pinctrl";
146			reg = <0 0x1000b000 0 0x1000>;
147			mediatek,pctl-regmap = <&syscfg_pctl_a>;
148			pins-are-numbered;
149			gpio-controller;
150			#gpio-cells = <2>;
151			interrupt-controller;
152			#interrupt-cells = <2>;
153			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
154				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
155				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
156		};
157
158		syscfg_pctl_a: syscfg_pctl_a@10005000 {
159			compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
160			reg = <0 0x10005000 0 0x1000>;
161		};
162
163		watchdog: watchdog@10007000 {
164			compatible = "mediatek,mt8173-wdt",
165				     "mediatek,mt6589-wdt";
166			reg = <0 0x10007000 0 0x100>;
167		};
168
169		pwrap: pwrap@1000d000 {
170			compatible = "mediatek,mt8173-pwrap";
171			reg = <0 0x1000d000 0 0x1000>;
172			reg-names = "pwrap";
173			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
174			resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
175			reset-names = "pwrap";
176			clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
177			clock-names = "spi", "wrap";
178		};
179
180		sysirq: intpol-controller@10200620 {
181			compatible = "mediatek,mt8173-sysirq",
182				     "mediatek,mt6577-sysirq";
183			interrupt-controller;
184			#interrupt-cells = <3>;
185			interrupt-parent = <&gic>;
186			reg = <0 0x10200620 0 0x20>;
187		};
188
189		apmixedsys: clock-controller@10209000 {
190			compatible = "mediatek,mt8173-apmixedsys";
191			reg = <0 0x10209000 0 0x1000>;
192			#clock-cells = <1>;
193		};
194
195		gic: interrupt-controller@10220000 {
196			compatible = "arm,gic-400";
197			#interrupt-cells = <3>;
198			interrupt-parent = <&gic>;
199			interrupt-controller;
200			reg = <0 0x10221000 0 0x1000>,
201			      <0 0x10222000 0 0x2000>,
202			      <0 0x10224000 0 0x2000>,
203			      <0 0x10226000 0 0x2000>;
204			interrupts = <GIC_PPI 9
205				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
206		};
207
208		uart0: serial@11002000 {
209			compatible = "mediatek,mt8173-uart",
210				     "mediatek,mt6577-uart";
211			reg = <0 0x11002000 0 0x400>;
212			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
213			clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
214			clock-names = "baud", "bus";
215			status = "disabled";
216		};
217
218		uart1: serial@11003000 {
219			compatible = "mediatek,mt8173-uart",
220				     "mediatek,mt6577-uart";
221			reg = <0 0x11003000 0 0x400>;
222			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
223			clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
224			clock-names = "baud", "bus";
225			status = "disabled";
226		};
227
228		uart2: serial@11004000 {
229			compatible = "mediatek,mt8173-uart",
230				     "mediatek,mt6577-uart";
231			reg = <0 0x11004000 0 0x400>;
232			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
233			clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
234			clock-names = "baud", "bus";
235			status = "disabled";
236		};
237
238		uart3: serial@11005000 {
239			compatible = "mediatek,mt8173-uart",
240				     "mediatek,mt6577-uart";
241			reg = <0 0x11005000 0 0x400>;
242			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
243			clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
244			clock-names = "baud", "bus";
245			status = "disabled";
246		};
247	};
248};
249
250