1/* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Eddie Huang <eddie.huang@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/clock/mt8173-clk.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include "mt8173-pinfunc.h" 18 19/ { 20 compatible = "mediatek,mt8173"; 21 interrupt-parent = <&sysirq>; 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 cpu-map { 30 cluster0 { 31 core0 { 32 cpu = <&cpu0>; 33 }; 34 core1 { 35 cpu = <&cpu1>; 36 }; 37 }; 38 39 cluster1 { 40 core0 { 41 cpu = <&cpu2>; 42 }; 43 core1 { 44 cpu = <&cpu3>; 45 }; 46 }; 47 }; 48 49 cpu0: cpu@0 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53"; 52 reg = <0x000>; 53 }; 54 55 cpu1: cpu@1 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a53"; 58 reg = <0x001>; 59 enable-method = "psci"; 60 }; 61 62 cpu2: cpu@100 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a57"; 65 reg = <0x100>; 66 enable-method = "psci"; 67 }; 68 69 cpu3: cpu@101 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a57"; 72 reg = <0x101>; 73 enable-method = "psci"; 74 }; 75 }; 76 77 psci { 78 compatible = "arm,psci"; 79 method = "smc"; 80 cpu_suspend = <0x84000001>; 81 cpu_off = <0x84000002>; 82 cpu_on = <0x84000003>; 83 }; 84 85 clk26m: oscillator@0 { 86 compatible = "fixed-clock"; 87 #clock-cells = <0>; 88 clock-frequency = <26000000>; 89 clock-output-names = "clk26m"; 90 }; 91 92 clk32k: oscillator@1 { 93 compatible = "fixed-clock"; 94 #clock-cells = <0>; 95 clock-frequency = <32000>; 96 clock-output-names = "clk32k"; 97 }; 98 99 timer { 100 compatible = "arm,armv8-timer"; 101 interrupt-parent = <&gic>; 102 interrupts = <GIC_PPI 13 103 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 104 <GIC_PPI 14 105 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 106 <GIC_PPI 11 107 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 108 <GIC_PPI 10 109 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 110 }; 111 112 soc { 113 #address-cells = <2>; 114 #size-cells = <2>; 115 compatible = "simple-bus"; 116 ranges; 117 118 topckgen: clock-controller@10000000 { 119 compatible = "mediatek,mt8173-topckgen"; 120 reg = <0 0x10000000 0 0x1000>; 121 #clock-cells = <1>; 122 }; 123 124 infracfg: power-controller@10001000 { 125 compatible = "mediatek,mt8173-infracfg", "syscon"; 126 reg = <0 0x10001000 0 0x1000>; 127 #clock-cells = <1>; 128 #reset-cells = <1>; 129 }; 130 131 pericfg: power-controller@10003000 { 132 compatible = "mediatek,mt8173-pericfg", "syscon"; 133 reg = <0 0x10003000 0 0x1000>; 134 #clock-cells = <1>; 135 #reset-cells = <1>; 136 }; 137 138 syscfg_pctl_a: syscfg_pctl_a@10005000 { 139 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 140 reg = <0 0x10005000 0 0x1000>; 141 }; 142 143 pio: pinctrl@0x10005000 { 144 compatible = "mediatek,mt8173-pinctrl"; 145 reg = <0 0x1000b000 0 0x1000>; 146 mediatek,pctl-regmap = <&syscfg_pctl_a>; 147 pins-are-numbered; 148 gpio-controller; 149 #gpio-cells = <2>; 150 interrupt-controller; 151 #interrupt-cells = <2>; 152 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 155 }; 156 157 syscfg_pctl_a: syscfg_pctl_a@10005000 { 158 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 159 reg = <0 0x10005000 0 0x1000>; 160 }; 161 162 sysirq: intpol-controller@10200620 { 163 compatible = "mediatek,mt8173-sysirq", 164 "mediatek,mt6577-sysirq"; 165 interrupt-controller; 166 #interrupt-cells = <3>; 167 interrupt-parent = <&gic>; 168 reg = <0 0x10200620 0 0x20>; 169 }; 170 171 apmixedsys: clock-controller@10209000 { 172 compatible = "mediatek,mt8173-apmixedsys"; 173 reg = <0 0x10209000 0 0x1000>; 174 #clock-cells = <1>; 175 }; 176 177 gic: interrupt-controller@10220000 { 178 compatible = "arm,gic-400"; 179 #interrupt-cells = <3>; 180 interrupt-parent = <&gic>; 181 interrupt-controller; 182 reg = <0 0x10221000 0 0x1000>, 183 <0 0x10222000 0 0x2000>, 184 <0 0x10224000 0 0x2000>, 185 <0 0x10226000 0 0x2000>; 186 interrupts = <GIC_PPI 9 187 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 188 }; 189 190 uart0: serial@11002000 { 191 compatible = "mediatek,mt8173-uart", 192 "mediatek,mt6577-uart"; 193 reg = <0 0x11002000 0 0x400>; 194 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 195 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 196 clock-names = "baud", "bus"; 197 status = "disabled"; 198 }; 199 200 uart1: serial@11003000 { 201 compatible = "mediatek,mt8173-uart", 202 "mediatek,mt6577-uart"; 203 reg = <0 0x11003000 0 0x400>; 204 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 205 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 206 clock-names = "baud", "bus"; 207 status = "disabled"; 208 }; 209 210 uart2: serial@11004000 { 211 compatible = "mediatek,mt8173-uart", 212 "mediatek,mt6577-uart"; 213 reg = <0 0x11004000 0 0x400>; 214 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 215 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 216 clock-names = "baud", "bus"; 217 status = "disabled"; 218 }; 219 220 uart3: serial@11005000 { 221 compatible = "mediatek,mt8173-uart", 222 "mediatek,mt6577-uart"; 223 reg = <0 0x11005000 0 0x400>; 224 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 225 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 226 clock-names = "baud", "bus"; 227 status = "disabled"; 228 }; 229 }; 230}; 231 232