1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Eddie Huang <eddie.huang@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11 * GNU General Public License for more details.
12 */
13
14#include <dt-bindings/clock/mt8173-clk.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/interrupt-controller/arm-gic.h>
17#include <dt-bindings/reset-controller/mt8173-resets.h>
18#include "mt8173-pinfunc.h"
19
20/ {
21	compatible = "mediatek,mt8173";
22	interrupt-parent = <&sysirq>;
23	#address-cells = <2>;
24	#size-cells = <2>;
25
26	cpus {
27		#address-cells = <1>;
28		#size-cells = <0>;
29
30		cpu-map {
31			cluster0 {
32				core0 {
33					cpu = <&cpu0>;
34				};
35				core1 {
36					cpu = <&cpu1>;
37				};
38			};
39
40			cluster1 {
41				core0 {
42					cpu = <&cpu2>;
43				};
44				core1 {
45					cpu = <&cpu3>;
46				};
47			};
48		};
49
50		cpu0: cpu@0 {
51			device_type = "cpu";
52			compatible = "arm,cortex-a53";
53			reg = <0x000>;
54		};
55
56		cpu1: cpu@1 {
57			device_type = "cpu";
58			compatible = "arm,cortex-a53";
59			reg = <0x001>;
60			enable-method = "psci";
61		};
62
63		cpu2: cpu@100 {
64			device_type = "cpu";
65			compatible = "arm,cortex-a57";
66			reg = <0x100>;
67			enable-method = "psci";
68		};
69
70		cpu3: cpu@101 {
71			device_type = "cpu";
72			compatible = "arm,cortex-a57";
73			reg = <0x101>;
74			enable-method = "psci";
75		};
76	};
77
78	psci {
79		compatible = "arm,psci";
80		method = "smc";
81		cpu_suspend   = <0x84000001>;
82		cpu_off	      = <0x84000002>;
83		cpu_on	      = <0x84000003>;
84	};
85
86	clk26m: oscillator@0 {
87		compatible = "fixed-clock";
88		#clock-cells = <0>;
89		clock-frequency = <26000000>;
90		clock-output-names = "clk26m";
91	};
92
93	clk32k: oscillator@1 {
94		compatible = "fixed-clock";
95		#clock-cells = <0>;
96		clock-frequency = <32000>;
97		clock-output-names = "clk32k";
98	};
99
100	timer {
101		compatible = "arm,armv8-timer";
102		interrupt-parent = <&gic>;
103		interrupts = <GIC_PPI 13
104			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
105			     <GIC_PPI 14
106			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
107			     <GIC_PPI 11
108			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
109			     <GIC_PPI 10
110			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
111	};
112
113	soc {
114		#address-cells = <2>;
115		#size-cells = <2>;
116		compatible = "simple-bus";
117		ranges;
118
119		topckgen: clock-controller@10000000 {
120			compatible = "mediatek,mt8173-topckgen";
121			reg = <0 0x10000000 0 0x1000>;
122			#clock-cells = <1>;
123		};
124
125		infracfg: power-controller@10001000 {
126			compatible = "mediatek,mt8173-infracfg", "syscon";
127			reg = <0 0x10001000 0 0x1000>;
128			#clock-cells = <1>;
129			#reset-cells = <1>;
130		};
131
132		pericfg: power-controller@10003000 {
133			compatible = "mediatek,mt8173-pericfg", "syscon";
134			reg = <0 0x10003000 0 0x1000>;
135			#clock-cells = <1>;
136			#reset-cells = <1>;
137		};
138
139		syscfg_pctl_a: syscfg_pctl_a@10005000 {
140			compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
141			reg = <0 0x10005000 0 0x1000>;
142		};
143
144		pio: pinctrl@0x10005000 {
145			compatible = "mediatek,mt8173-pinctrl";
146			reg = <0 0x1000b000 0 0x1000>;
147			mediatek,pctl-regmap = <&syscfg_pctl_a>;
148			pins-are-numbered;
149			gpio-controller;
150			#gpio-cells = <2>;
151			interrupt-controller;
152			#interrupt-cells = <2>;
153			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
154				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
155				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
156
157			i2c0_pins_a: i2c0 {
158				pins1 {
159					pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
160						 <MT8173_PIN_46_SCL0__FUNC_SCL0>;
161					bias-disable;
162				};
163			};
164
165			i2c1_pins_a: i2c1 {
166				pins1 {
167					pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
168						 <MT8173_PIN_126_SCL1__FUNC_SCL1>;
169					bias-disable;
170				};
171			};
172
173			i2c2_pins_a: i2c2 {
174				pins1 {
175					pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
176						 <MT8173_PIN_44_SCL2__FUNC_SCL2>;
177					bias-disable;
178				};
179			};
180
181			i2c3_pins_a: i2c3 {
182				pins1 {
183					pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
184						 <MT8173_PIN_107_SCL3__FUNC_SCL3>;
185					bias-disable;
186				};
187			};
188
189			i2c4_pins_a: i2c4 {
190				pins1 {
191					pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
192						 <MT8173_PIN_134_SCL4__FUNC_SCL4>;
193					bias-disable;
194				};
195			};
196
197			i2c6_pins_a: i2c6 {
198				pins1 {
199					pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
200						 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
201					bias-disable;
202				};
203			};
204		};
205
206		watchdog: watchdog@10007000 {
207			compatible = "mediatek,mt8173-wdt",
208				     "mediatek,mt6589-wdt";
209			reg = <0 0x10007000 0 0x100>;
210		};
211
212		pwrap: pwrap@1000d000 {
213			compatible = "mediatek,mt8173-pwrap";
214			reg = <0 0x1000d000 0 0x1000>;
215			reg-names = "pwrap";
216			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
217			resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
218			reset-names = "pwrap";
219			clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
220			clock-names = "spi", "wrap";
221		};
222
223		sysirq: intpol-controller@10200620 {
224			compatible = "mediatek,mt8173-sysirq",
225				     "mediatek,mt6577-sysirq";
226			interrupt-controller;
227			#interrupt-cells = <3>;
228			interrupt-parent = <&gic>;
229			reg = <0 0x10200620 0 0x20>;
230		};
231
232		apmixedsys: clock-controller@10209000 {
233			compatible = "mediatek,mt8173-apmixedsys";
234			reg = <0 0x10209000 0 0x1000>;
235			#clock-cells = <1>;
236		};
237
238		gic: interrupt-controller@10220000 {
239			compatible = "arm,gic-400";
240			#interrupt-cells = <3>;
241			interrupt-parent = <&gic>;
242			interrupt-controller;
243			reg = <0 0x10221000 0 0x1000>,
244			      <0 0x10222000 0 0x2000>,
245			      <0 0x10224000 0 0x2000>,
246			      <0 0x10226000 0 0x2000>;
247			interrupts = <GIC_PPI 9
248				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
249		};
250
251		uart0: serial@11002000 {
252			compatible = "mediatek,mt8173-uart",
253				     "mediatek,mt6577-uart";
254			reg = <0 0x11002000 0 0x400>;
255			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
256			clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
257			clock-names = "baud", "bus";
258			status = "disabled";
259		};
260
261		uart1: serial@11003000 {
262			compatible = "mediatek,mt8173-uart",
263				     "mediatek,mt6577-uart";
264			reg = <0 0x11003000 0 0x400>;
265			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
266			clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
267			clock-names = "baud", "bus";
268			status = "disabled";
269		};
270
271		uart2: serial@11004000 {
272			compatible = "mediatek,mt8173-uart",
273				     "mediatek,mt6577-uart";
274			reg = <0 0x11004000 0 0x400>;
275			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
276			clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
277			clock-names = "baud", "bus";
278			status = "disabled";
279		};
280
281		uart3: serial@11005000 {
282			compatible = "mediatek,mt8173-uart",
283				     "mediatek,mt6577-uart";
284			reg = <0 0x11005000 0 0x400>;
285			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
286			clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
287			clock-names = "baud", "bus";
288			status = "disabled";
289		};
290
291		i2c0: i2c@11007000 {
292			compatible = "mediatek,mt8173-i2c";
293			reg = <0 0x11007000 0 0x70>,
294			      <0 0x11000100 0 0x80>;
295			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
296			clock-div = <16>;
297			clocks = <&pericfg CLK_PERI_I2C0>,
298				 <&pericfg CLK_PERI_AP_DMA>;
299			clock-names = "main", "dma";
300			pinctrl-names = "default";
301			pinctrl-0 = <&i2c0_pins_a>;
302			#address-cells = <1>;
303			#size-cells = <0>;
304			status = "disabled";
305		};
306
307		i2c1: i2c@11008000 {
308			compatible = "mediatek,mt8173-i2c";
309			reg = <0 0x11008000 0 0x70>,
310			      <0 0x11000180 0 0x80>;
311			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
312			clock-div = <16>;
313			clocks = <&pericfg CLK_PERI_I2C1>,
314				 <&pericfg CLK_PERI_AP_DMA>;
315			clock-names = "main", "dma";
316			pinctrl-names = "default";
317			pinctrl-0 = <&i2c1_pins_a>;
318			#address-cells = <1>;
319			#size-cells = <0>;
320			status = "disabled";
321		};
322
323		i2c2: i2c@11009000 {
324			compatible = "mediatek,mt8173-i2c";
325			reg = <0 0x11009000 0 0x70>,
326			      <0 0x11000200 0 0x80>;
327			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
328			clock-div = <16>;
329			clocks = <&pericfg CLK_PERI_I2C2>,
330				 <&pericfg CLK_PERI_AP_DMA>;
331			clock-names = "main", "dma";
332			pinctrl-names = "default";
333			pinctrl-0 = <&i2c2_pins_a>;
334			#address-cells = <1>;
335			#size-cells = <0>;
336			status = "disabled";
337		};
338
339		i2c3: i2c3@11010000 {
340			compatible = "mediatek,mt8173-i2c";
341			reg = <0 0x11010000 0 0x70>,
342			      <0 0x11000280 0 0x80>;
343			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
344			clock-div = <16>;
345			clocks = <&pericfg CLK_PERI_I2C3>,
346				 <&pericfg CLK_PERI_AP_DMA>;
347			clock-names = "main", "dma";
348			pinctrl-names = "default";
349			pinctrl-0 = <&i2c3_pins_a>;
350			#address-cells = <1>;
351			#size-cells = <0>;
352			status = "disabled";
353		};
354
355		i2c4: i2c4@11011000 {
356			compatible = "mediatek,mt8173-i2c";
357			reg = <0 0x11011000 0 0x70>,
358			      <0 0x11000300 0 0x80>;
359			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
360			clock-div = <16>;
361			clocks = <&pericfg CLK_PERI_I2C4>,
362				 <&pericfg CLK_PERI_AP_DMA>;
363			clock-names = "main", "dma";
364			pinctrl-names = "default";
365			pinctrl-0 = <&i2c4_pins_a>;
366			#address-cells = <1>;
367			#size-cells = <0>;
368			status = "disabled";
369		};
370
371		i2c6: i2c6@11013000 {
372			compatible = "mediatek,mt8173-i2c";
373			reg = <0 0x11013000 0 0x70>,
374			      <0 0x11000080 0 0x80>;
375			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
376			clock-div = <16>;
377			clocks = <&pericfg CLK_PERI_I2C6>,
378				 <&pericfg CLK_PERI_AP_DMA>;
379			clock-names = "main", "dma";
380			pinctrl-names = "default";
381			pinctrl-0 = <&i2c6_pins_a>;
382			#address-cells = <1>;
383			#size-cells = <0>;
384			status = "disabled";
385		};
386	};
387};
388
389