1b3a37248SEddie Huang/* 2b3a37248SEddie Huang * Copyright (c) 2014 MediaTek Inc. 3b3a37248SEddie Huang * Author: Eddie Huang <eddie.huang@mediatek.com> 4b3a37248SEddie Huang * 5b3a37248SEddie Huang * This program is free software; you can redistribute it and/or modify 6b3a37248SEddie Huang * it under the terms of the GNU General Public License version 2 as 7b3a37248SEddie Huang * published by the Free Software Foundation. 8b3a37248SEddie Huang * 9b3a37248SEddie Huang * This program is distributed in the hope that it will be useful, 10b3a37248SEddie Huang * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11b3a37248SEddie Huang * GNU General Public License for more details. 12b3a37248SEddie Huang */ 13b3a37248SEddie Huang 14f2ce7014SSascha Hauer#include <dt-bindings/clock/mt8173-clk.h> 15b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/irq.h> 16b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/arm-gic.h> 17359f9365SHongzhou Yang#include "mt8173-pinfunc.h" 18b3a37248SEddie Huang 19b3a37248SEddie Huang/ { 20b3a37248SEddie Huang compatible = "mediatek,mt8173"; 21b3a37248SEddie Huang interrupt-parent = <&sysirq>; 22b3a37248SEddie Huang #address-cells = <2>; 23b3a37248SEddie Huang #size-cells = <2>; 24b3a37248SEddie Huang 25b3a37248SEddie Huang cpus { 26b3a37248SEddie Huang #address-cells = <1>; 27b3a37248SEddie Huang #size-cells = <0>; 28b3a37248SEddie Huang 29b3a37248SEddie Huang cpu-map { 30b3a37248SEddie Huang cluster0 { 31b3a37248SEddie Huang core0 { 32b3a37248SEddie Huang cpu = <&cpu0>; 33b3a37248SEddie Huang }; 34b3a37248SEddie Huang core1 { 35b3a37248SEddie Huang cpu = <&cpu1>; 36b3a37248SEddie Huang }; 37b3a37248SEddie Huang }; 38b3a37248SEddie Huang 39b3a37248SEddie Huang cluster1 { 40b3a37248SEddie Huang core0 { 41b3a37248SEddie Huang cpu = <&cpu2>; 42b3a37248SEddie Huang }; 43b3a37248SEddie Huang core1 { 44b3a37248SEddie Huang cpu = <&cpu3>; 45b3a37248SEddie Huang }; 46b3a37248SEddie Huang }; 47b3a37248SEddie Huang }; 48b3a37248SEddie Huang 49b3a37248SEddie Huang cpu0: cpu@0 { 50b3a37248SEddie Huang device_type = "cpu"; 51b3a37248SEddie Huang compatible = "arm,cortex-a53"; 52b3a37248SEddie Huang reg = <0x000>; 53b3a37248SEddie Huang }; 54b3a37248SEddie Huang 55b3a37248SEddie Huang cpu1: cpu@1 { 56b3a37248SEddie Huang device_type = "cpu"; 57b3a37248SEddie Huang compatible = "arm,cortex-a53"; 58b3a37248SEddie Huang reg = <0x001>; 59b3a37248SEddie Huang enable-method = "psci"; 60b3a37248SEddie Huang }; 61b3a37248SEddie Huang 62b3a37248SEddie Huang cpu2: cpu@100 { 63b3a37248SEddie Huang device_type = "cpu"; 64b3a37248SEddie Huang compatible = "arm,cortex-a57"; 65b3a37248SEddie Huang reg = <0x100>; 66b3a37248SEddie Huang enable-method = "psci"; 67b3a37248SEddie Huang }; 68b3a37248SEddie Huang 69b3a37248SEddie Huang cpu3: cpu@101 { 70b3a37248SEddie Huang device_type = "cpu"; 71b3a37248SEddie Huang compatible = "arm,cortex-a57"; 72b3a37248SEddie Huang reg = <0x101>; 73b3a37248SEddie Huang enable-method = "psci"; 74b3a37248SEddie Huang }; 75b3a37248SEddie Huang }; 76b3a37248SEddie Huang 77b3a37248SEddie Huang psci { 78b3a37248SEddie Huang compatible = "arm,psci"; 79b3a37248SEddie Huang method = "smc"; 80b3a37248SEddie Huang cpu_suspend = <0x84000001>; 81b3a37248SEddie Huang cpu_off = <0x84000002>; 82b3a37248SEddie Huang cpu_on = <0x84000003>; 83b3a37248SEddie Huang }; 84b3a37248SEddie Huang 85b3a37248SEddie Huang uart_clk: dummy26m { 86b3a37248SEddie Huang compatible = "fixed-clock"; 87b3a37248SEddie Huang clock-frequency = <26000000>; 88b3a37248SEddie Huang #clock-cells = <0>; 89b3a37248SEddie Huang }; 90b3a37248SEddie Huang 91f2ce7014SSascha Hauer clk26m: oscillator@0 { 92f2ce7014SSascha Hauer compatible = "fixed-clock"; 93f2ce7014SSascha Hauer #clock-cells = <0>; 94f2ce7014SSascha Hauer clock-frequency = <26000000>; 95f2ce7014SSascha Hauer clock-output-names = "clk26m"; 96f2ce7014SSascha Hauer }; 97f2ce7014SSascha Hauer 98f2ce7014SSascha Hauer clk32k: oscillator@1 { 99f2ce7014SSascha Hauer compatible = "fixed-clock"; 100f2ce7014SSascha Hauer #clock-cells = <0>; 101f2ce7014SSascha Hauer clock-frequency = <32000>; 102f2ce7014SSascha Hauer clock-output-names = "clk32k"; 103f2ce7014SSascha Hauer }; 104f2ce7014SSascha Hauer 105b3a37248SEddie Huang timer { 106b3a37248SEddie Huang compatible = "arm,armv8-timer"; 107b3a37248SEddie Huang interrupt-parent = <&gic>; 108b3a37248SEddie Huang interrupts = <GIC_PPI 13 109b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 110b3a37248SEddie Huang <GIC_PPI 14 111b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 112b3a37248SEddie Huang <GIC_PPI 11 113b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 114b3a37248SEddie Huang <GIC_PPI 10 115b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 116b3a37248SEddie Huang }; 117b3a37248SEddie Huang 118b3a37248SEddie Huang soc { 119b3a37248SEddie Huang #address-cells = <2>; 120b3a37248SEddie Huang #size-cells = <2>; 121b3a37248SEddie Huang compatible = "simple-bus"; 122b3a37248SEddie Huang ranges; 123b3a37248SEddie Huang 124f2ce7014SSascha Hauer topckgen: clock-controller@10000000 { 125f2ce7014SSascha Hauer compatible = "mediatek,mt8173-topckgen"; 126f2ce7014SSascha Hauer reg = <0 0x10000000 0 0x1000>; 127f2ce7014SSascha Hauer #clock-cells = <1>; 128f2ce7014SSascha Hauer }; 129f2ce7014SSascha Hauer 130f2ce7014SSascha Hauer infracfg: power-controller@10001000 { 131f2ce7014SSascha Hauer compatible = "mediatek,mt8173-infracfg", "syscon"; 132f2ce7014SSascha Hauer reg = <0 0x10001000 0 0x1000>; 133f2ce7014SSascha Hauer #clock-cells = <1>; 134f2ce7014SSascha Hauer #reset-cells = <1>; 135f2ce7014SSascha Hauer }; 136f2ce7014SSascha Hauer 137f2ce7014SSascha Hauer pericfg: power-controller@10003000 { 138f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pericfg", "syscon"; 139f2ce7014SSascha Hauer reg = <0 0x10003000 0 0x1000>; 140f2ce7014SSascha Hauer #clock-cells = <1>; 141f2ce7014SSascha Hauer #reset-cells = <1>; 142f2ce7014SSascha Hauer }; 143f2ce7014SSascha Hauer 144f2ce7014SSascha Hauer syscfg_pctl_a: syscfg_pctl_a@10005000 { 145f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 146f2ce7014SSascha Hauer reg = <0 0x10005000 0 0x1000>; 147f2ce7014SSascha Hauer }; 148f2ce7014SSascha Hauer 149f2ce7014SSascha Hauer pio: pinctrl@0x10005000 { 150359f9365SHongzhou Yang compatible = "mediatek,mt8173-pinctrl"; 1516769b93cSYingjoe Chen reg = <0 0x1000b000 0 0x1000>; 152359f9365SHongzhou Yang mediatek,pctl-regmap = <&syscfg_pctl_a>; 153359f9365SHongzhou Yang pins-are-numbered; 154359f9365SHongzhou Yang gpio-controller; 155359f9365SHongzhou Yang #gpio-cells = <2>; 156359f9365SHongzhou Yang interrupt-controller; 157359f9365SHongzhou Yang #interrupt-cells = <2>; 158359f9365SHongzhou Yang interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 159359f9365SHongzhou Yang <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 160359f9365SHongzhou Yang <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 161359f9365SHongzhou Yang }; 162359f9365SHongzhou Yang 1636769b93cSYingjoe Chen syscfg_pctl_a: syscfg_pctl_a@10005000 { 1646769b93cSYingjoe Chen compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 1656769b93cSYingjoe Chen reg = <0 0x10005000 0 0x1000>; 1666769b93cSYingjoe Chen }; 1676769b93cSYingjoe Chen 168b3a37248SEddie Huang sysirq: intpol-controller@10200620 { 169b3a37248SEddie Huang compatible = "mediatek,mt8173-sysirq", 170b3a37248SEddie Huang "mediatek,mt6577-sysirq"; 171b3a37248SEddie Huang interrupt-controller; 172b3a37248SEddie Huang #interrupt-cells = <3>; 173b3a37248SEddie Huang interrupt-parent = <&gic>; 174b3a37248SEddie Huang reg = <0 0x10200620 0 0x20>; 175b3a37248SEddie Huang }; 176b3a37248SEddie Huang 177f2ce7014SSascha Hauer apmixedsys: clock-controller@10209000 { 178f2ce7014SSascha Hauer compatible = "mediatek,mt8173-apmixedsys"; 179f2ce7014SSascha Hauer reg = <0 0x10209000 0 0x1000>; 180f2ce7014SSascha Hauer #clock-cells = <1>; 181f2ce7014SSascha Hauer }; 182f2ce7014SSascha Hauer 183b3a37248SEddie Huang gic: interrupt-controller@10220000 { 184b3a37248SEddie Huang compatible = "arm,gic-400"; 185b3a37248SEddie Huang #interrupt-cells = <3>; 186b3a37248SEddie Huang interrupt-parent = <&gic>; 187b3a37248SEddie Huang interrupt-controller; 188b3a37248SEddie Huang reg = <0 0x10221000 0 0x1000>, 189b3a37248SEddie Huang <0 0x10222000 0 0x2000>, 190b3a37248SEddie Huang <0 0x10224000 0 0x2000>, 191b3a37248SEddie Huang <0 0x10226000 0 0x2000>; 192b3a37248SEddie Huang interrupts = <GIC_PPI 9 193b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 194b3a37248SEddie Huang }; 195b3a37248SEddie Huang 196b3a37248SEddie Huang uart0: serial@11002000 { 197b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 198b3a37248SEddie Huang "mediatek,mt6577-uart"; 199b3a37248SEddie Huang reg = <0 0x11002000 0 0x400>; 200b3a37248SEddie Huang interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 201b3a37248SEddie Huang clocks = <&uart_clk>; 202b3a37248SEddie Huang status = "disabled"; 203b3a37248SEddie Huang }; 204b3a37248SEddie Huang 205b3a37248SEddie Huang uart1: serial@11003000 { 206b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 207b3a37248SEddie Huang "mediatek,mt6577-uart"; 208b3a37248SEddie Huang reg = <0 0x11003000 0 0x400>; 209b3a37248SEddie Huang interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 210b3a37248SEddie Huang clocks = <&uart_clk>; 211b3a37248SEddie Huang status = "disabled"; 212b3a37248SEddie Huang }; 213b3a37248SEddie Huang 214b3a37248SEddie Huang uart2: serial@11004000 { 215b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 216b3a37248SEddie Huang "mediatek,mt6577-uart"; 217b3a37248SEddie Huang reg = <0 0x11004000 0 0x400>; 218b3a37248SEddie Huang interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 219b3a37248SEddie Huang clocks = <&uart_clk>; 220b3a37248SEddie Huang status = "disabled"; 221b3a37248SEddie Huang }; 222b3a37248SEddie Huang 223b3a37248SEddie Huang uart3: serial@11005000 { 224b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 225b3a37248SEddie Huang "mediatek,mt6577-uart"; 226b3a37248SEddie Huang reg = <0 0x11005000 0 0x400>; 227b3a37248SEddie Huang interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 228b3a37248SEddie Huang clocks = <&uart_clk>; 229b3a37248SEddie Huang status = "disabled"; 230b3a37248SEddie Huang }; 231b3a37248SEddie Huang }; 232b3a37248SEddie Huang}; 233b3a37248SEddie Huang 234