1b3a37248SEddie Huang/* 2b3a37248SEddie Huang * Copyright (c) 2014 MediaTek Inc. 3b3a37248SEddie Huang * Author: Eddie Huang <eddie.huang@mediatek.com> 4b3a37248SEddie Huang * 5b3a37248SEddie Huang * This program is free software; you can redistribute it and/or modify 6b3a37248SEddie Huang * it under the terms of the GNU General Public License version 2 as 7b3a37248SEddie Huang * published by the Free Software Foundation. 8b3a37248SEddie Huang * 9b3a37248SEddie Huang * This program is distributed in the hope that it will be useful, 10b3a37248SEddie Huang * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11b3a37248SEddie Huang * GNU General Public License for more details. 12b3a37248SEddie Huang */ 13b3a37248SEddie Huang 14f2ce7014SSascha Hauer#include <dt-bindings/clock/mt8173-clk.h> 15b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/irq.h> 16b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/arm-gic.h> 175ff6b3a6SYong Wu#include <dt-bindings/memory/mt8173-larb-port.h> 18bfcce47aSChunfeng Yun#include <dt-bindings/phy/phy.h> 19c02e0e86SKoro Chen#include <dt-bindings/power/mt8173-power.h> 20967313e2SPhilipp Zabel#include <dt-bindings/reset/mt8173-resets.h> 21359f9365SHongzhou Yang#include "mt8173-pinfunc.h" 22b3a37248SEddie Huang 23b3a37248SEddie Huang/ { 24b3a37248SEddie Huang compatible = "mediatek,mt8173"; 25b3a37248SEddie Huang interrupt-parent = <&sysirq>; 26b3a37248SEddie Huang #address-cells = <2>; 27b3a37248SEddie Huang #size-cells = <2>; 28b3a37248SEddie Huang 2981ad4dbaSCK Hu aliases { 3081ad4dbaSCK Hu ovl0 = &ovl0; 3181ad4dbaSCK Hu ovl1 = &ovl1; 3281ad4dbaSCK Hu rdma0 = &rdma0; 3381ad4dbaSCK Hu rdma1 = &rdma1; 3481ad4dbaSCK Hu rdma2 = &rdma2; 3581ad4dbaSCK Hu wdma0 = &wdma0; 3681ad4dbaSCK Hu wdma1 = &wdma1; 3781ad4dbaSCK Hu color0 = &color0; 3881ad4dbaSCK Hu color1 = &color1; 3981ad4dbaSCK Hu split0 = &split0; 4081ad4dbaSCK Hu split1 = &split1; 4181ad4dbaSCK Hu dpi0 = &dpi0; 4281ad4dbaSCK Hu dsi0 = &dsi0; 4381ad4dbaSCK Hu dsi1 = &dsi1; 44989b292aSMinghsiu Tsai mdp_rdma0 = &mdp_rdma0; 45989b292aSMinghsiu Tsai mdp_rdma1 = &mdp_rdma1; 46989b292aSMinghsiu Tsai mdp_rsz0 = &mdp_rsz0; 47989b292aSMinghsiu Tsai mdp_rsz1 = &mdp_rsz1; 48989b292aSMinghsiu Tsai mdp_rsz2 = &mdp_rsz2; 49989b292aSMinghsiu Tsai mdp_wdma0 = &mdp_wdma0; 50989b292aSMinghsiu Tsai mdp_wrot0 = &mdp_wrot0; 51989b292aSMinghsiu Tsai mdp_wrot1 = &mdp_wrot1; 5281ad4dbaSCK Hu }; 5381ad4dbaSCK Hu 54b3a37248SEddie Huang cpus { 55b3a37248SEddie Huang #address-cells = <1>; 56b3a37248SEddie Huang #size-cells = <0>; 57b3a37248SEddie Huang 58b3a37248SEddie Huang cpu-map { 59b3a37248SEddie Huang cluster0 { 60b3a37248SEddie Huang core0 { 61b3a37248SEddie Huang cpu = <&cpu0>; 62b3a37248SEddie Huang }; 63b3a37248SEddie Huang core1 { 64b3a37248SEddie Huang cpu = <&cpu1>; 65b3a37248SEddie Huang }; 66b3a37248SEddie Huang }; 67b3a37248SEddie Huang 68b3a37248SEddie Huang cluster1 { 69b3a37248SEddie Huang core0 { 70b3a37248SEddie Huang cpu = <&cpu2>; 71b3a37248SEddie Huang }; 72b3a37248SEddie Huang core1 { 73b3a37248SEddie Huang cpu = <&cpu3>; 74b3a37248SEddie Huang }; 75b3a37248SEddie Huang }; 76b3a37248SEddie Huang }; 77b3a37248SEddie Huang 78b3a37248SEddie Huang cpu0: cpu@0 { 79b3a37248SEddie Huang device_type = "cpu"; 80b3a37248SEddie Huang compatible = "arm,cortex-a53"; 81b3a37248SEddie Huang reg = <0x000>; 82ad4df7a5SHoward Chen enable-method = "psci"; 83ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 84b3a37248SEddie Huang }; 85b3a37248SEddie Huang 86b3a37248SEddie Huang cpu1: cpu@1 { 87b3a37248SEddie Huang device_type = "cpu"; 88b3a37248SEddie Huang compatible = "arm,cortex-a53"; 89b3a37248SEddie Huang reg = <0x001>; 90b3a37248SEddie Huang enable-method = "psci"; 91ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 92b3a37248SEddie Huang }; 93b3a37248SEddie Huang 94b3a37248SEddie Huang cpu2: cpu@100 { 95b3a37248SEddie Huang device_type = "cpu"; 96b3a37248SEddie Huang compatible = "arm,cortex-a57"; 97b3a37248SEddie Huang reg = <0x100>; 98b3a37248SEddie Huang enable-method = "psci"; 99ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 100b3a37248SEddie Huang }; 101b3a37248SEddie Huang 102b3a37248SEddie Huang cpu3: cpu@101 { 103b3a37248SEddie Huang device_type = "cpu"; 104b3a37248SEddie Huang compatible = "arm,cortex-a57"; 105b3a37248SEddie Huang reg = <0x101>; 106b3a37248SEddie Huang enable-method = "psci"; 107ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 108ad4df7a5SHoward Chen }; 109ad4df7a5SHoward Chen 110ad4df7a5SHoward Chen idle-states { 111a13f18f5SLorenzo Pieralisi entry-method = "psci"; 112ad4df7a5SHoward Chen 113ad4df7a5SHoward Chen CPU_SLEEP_0: cpu-sleep-0 { 114ad4df7a5SHoward Chen compatible = "arm,idle-state"; 115ad4df7a5SHoward Chen local-timer-stop; 116ad4df7a5SHoward Chen entry-latency-us = <639>; 117ad4df7a5SHoward Chen exit-latency-us = <680>; 118ad4df7a5SHoward Chen min-residency-us = <1088>; 119ad4df7a5SHoward Chen arm,psci-suspend-param = <0x0010000>; 120ad4df7a5SHoward Chen }; 121b3a37248SEddie Huang }; 122b3a37248SEddie Huang }; 123b3a37248SEddie Huang 124b3a37248SEddie Huang psci { 12505bdabe7SFan Chen compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 126b3a37248SEddie Huang method = "smc"; 127b3a37248SEddie Huang cpu_suspend = <0x84000001>; 128b3a37248SEddie Huang cpu_off = <0x84000002>; 129b3a37248SEddie Huang cpu_on = <0x84000003>; 130b3a37248SEddie Huang }; 131b3a37248SEddie Huang 132f2ce7014SSascha Hauer clk26m: oscillator@0 { 133f2ce7014SSascha Hauer compatible = "fixed-clock"; 134f2ce7014SSascha Hauer #clock-cells = <0>; 135f2ce7014SSascha Hauer clock-frequency = <26000000>; 136f2ce7014SSascha Hauer clock-output-names = "clk26m"; 137f2ce7014SSascha Hauer }; 138f2ce7014SSascha Hauer 139f2ce7014SSascha Hauer clk32k: oscillator@1 { 140f2ce7014SSascha Hauer compatible = "fixed-clock"; 141f2ce7014SSascha Hauer #clock-cells = <0>; 142f2ce7014SSascha Hauer clock-frequency = <32000>; 143f2ce7014SSascha Hauer clock-output-names = "clk32k"; 144f2ce7014SSascha Hauer }; 145f2ce7014SSascha Hauer 14667e56c56SJames Liao cpum_ck: oscillator@2 { 14767e56c56SJames Liao compatible = "fixed-clock"; 14867e56c56SJames Liao #clock-cells = <0>; 14967e56c56SJames Liao clock-frequency = <0>; 15067e56c56SJames Liao clock-output-names = "cpum_ck"; 15167e56c56SJames Liao }; 15267e56c56SJames Liao 153962f5143Sdawei.chien@mediatek.com thermal-zones { 154962f5143Sdawei.chien@mediatek.com cpu_thermal: cpu_thermal { 155962f5143Sdawei.chien@mediatek.com polling-delay-passive = <1000>; /* milliseconds */ 156962f5143Sdawei.chien@mediatek.com polling-delay = <1000>; /* milliseconds */ 157962f5143Sdawei.chien@mediatek.com 158962f5143Sdawei.chien@mediatek.com thermal-sensors = <&thermal>; 159962f5143Sdawei.chien@mediatek.com sustainable-power = <1500>; /* milliwatts */ 160962f5143Sdawei.chien@mediatek.com 161962f5143Sdawei.chien@mediatek.com trips { 162962f5143Sdawei.chien@mediatek.com threshold: trip-point@0 { 163962f5143Sdawei.chien@mediatek.com temperature = <68000>; 164962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 165962f5143Sdawei.chien@mediatek.com type = "passive"; 166962f5143Sdawei.chien@mediatek.com }; 167962f5143Sdawei.chien@mediatek.com 168962f5143Sdawei.chien@mediatek.com target: trip-point@1 { 169962f5143Sdawei.chien@mediatek.com temperature = <85000>; 170962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 171962f5143Sdawei.chien@mediatek.com type = "passive"; 172962f5143Sdawei.chien@mediatek.com }; 173962f5143Sdawei.chien@mediatek.com 174962f5143Sdawei.chien@mediatek.com cpu_crit: cpu_crit@0 { 175962f5143Sdawei.chien@mediatek.com temperature = <115000>; 176962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 177962f5143Sdawei.chien@mediatek.com type = "critical"; 178962f5143Sdawei.chien@mediatek.com }; 179962f5143Sdawei.chien@mediatek.com }; 180962f5143Sdawei.chien@mediatek.com 181962f5143Sdawei.chien@mediatek.com cooling-maps { 182962f5143Sdawei.chien@mediatek.com map@0 { 183962f5143Sdawei.chien@mediatek.com trip = <&target>; 184962f5143Sdawei.chien@mediatek.com cooling-device = <&cpu0 0 0>; 1857fcef92dSDaniel Kurtz contribution = <3072>; 186962f5143Sdawei.chien@mediatek.com }; 187962f5143Sdawei.chien@mediatek.com map@1 { 188962f5143Sdawei.chien@mediatek.com trip = <&target>; 189962f5143Sdawei.chien@mediatek.com cooling-device = <&cpu2 0 0>; 1907fcef92dSDaniel Kurtz contribution = <1024>; 191962f5143Sdawei.chien@mediatek.com }; 192962f5143Sdawei.chien@mediatek.com }; 193962f5143Sdawei.chien@mediatek.com }; 194962f5143Sdawei.chien@mediatek.com }; 195962f5143Sdawei.chien@mediatek.com 196404b2819SAndrew-CT Chen reserved-memory { 197404b2819SAndrew-CT Chen #address-cells = <2>; 198404b2819SAndrew-CT Chen #size-cells = <2>; 199404b2819SAndrew-CT Chen ranges; 200404b2819SAndrew-CT Chen vpu_dma_reserved: vpu_dma_mem_region { 201404b2819SAndrew-CT Chen compatible = "shared-dma-pool"; 202404b2819SAndrew-CT Chen reg = <0 0xb7000000 0 0x500000>; 203404b2819SAndrew-CT Chen alignment = <0x1000>; 204404b2819SAndrew-CT Chen no-map; 205404b2819SAndrew-CT Chen }; 206404b2819SAndrew-CT Chen }; 207404b2819SAndrew-CT Chen 208b3a37248SEddie Huang timer { 209b3a37248SEddie Huang compatible = "arm,armv8-timer"; 210b3a37248SEddie Huang interrupt-parent = <&gic>; 211b3a37248SEddie Huang interrupts = <GIC_PPI 13 212b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 213b3a37248SEddie Huang <GIC_PPI 14 214b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 215b3a37248SEddie Huang <GIC_PPI 11 216b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 217b3a37248SEddie Huang <GIC_PPI 10 218b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 219b3a37248SEddie Huang }; 220b3a37248SEddie Huang 221b3a37248SEddie Huang soc { 222b3a37248SEddie Huang #address-cells = <2>; 223b3a37248SEddie Huang #size-cells = <2>; 224b3a37248SEddie Huang compatible = "simple-bus"; 225b3a37248SEddie Huang ranges; 226b3a37248SEddie Huang 227f2ce7014SSascha Hauer topckgen: clock-controller@10000000 { 228f2ce7014SSascha Hauer compatible = "mediatek,mt8173-topckgen"; 229f2ce7014SSascha Hauer reg = <0 0x10000000 0 0x1000>; 230f2ce7014SSascha Hauer #clock-cells = <1>; 231f2ce7014SSascha Hauer }; 232f2ce7014SSascha Hauer 233f2ce7014SSascha Hauer infracfg: power-controller@10001000 { 234f2ce7014SSascha Hauer compatible = "mediatek,mt8173-infracfg", "syscon"; 235f2ce7014SSascha Hauer reg = <0 0x10001000 0 0x1000>; 236f2ce7014SSascha Hauer #clock-cells = <1>; 237f2ce7014SSascha Hauer #reset-cells = <1>; 238f2ce7014SSascha Hauer }; 239f2ce7014SSascha Hauer 240f2ce7014SSascha Hauer pericfg: power-controller@10003000 { 241f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pericfg", "syscon"; 242f2ce7014SSascha Hauer reg = <0 0x10003000 0 0x1000>; 243f2ce7014SSascha Hauer #clock-cells = <1>; 244f2ce7014SSascha Hauer #reset-cells = <1>; 245f2ce7014SSascha Hauer }; 246f2ce7014SSascha Hauer 247f2ce7014SSascha Hauer syscfg_pctl_a: syscfg_pctl_a@10005000 { 248f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 249f2ce7014SSascha Hauer reg = <0 0x10005000 0 0x1000>; 250f2ce7014SSascha Hauer }; 251f2ce7014SSascha Hauer 252f2ce7014SSascha Hauer pio: pinctrl@0x10005000 { 253359f9365SHongzhou Yang compatible = "mediatek,mt8173-pinctrl"; 2546769b93cSYingjoe Chen reg = <0 0x1000b000 0 0x1000>; 255359f9365SHongzhou Yang mediatek,pctl-regmap = <&syscfg_pctl_a>; 256359f9365SHongzhou Yang pins-are-numbered; 257359f9365SHongzhou Yang gpio-controller; 258359f9365SHongzhou Yang #gpio-cells = <2>; 259359f9365SHongzhou Yang interrupt-controller; 260359f9365SHongzhou Yang #interrupt-cells = <2>; 261359f9365SHongzhou Yang interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 262359f9365SHongzhou Yang <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 263359f9365SHongzhou Yang <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 264091cf598SEddie Huang 265a10b57f4SCK Hu hdmi_pin: xxx { 266a10b57f4SCK Hu 267a10b57f4SCK Hu /*hdmi htplg pin*/ 268a10b57f4SCK Hu pins1 { 269a10b57f4SCK Hu pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>; 270a10b57f4SCK Hu input-enable; 271a10b57f4SCK Hu bias-pull-down; 272a10b57f4SCK Hu }; 273a10b57f4SCK Hu }; 274a10b57f4SCK Hu 275091cf598SEddie Huang i2c0_pins_a: i2c0 { 276091cf598SEddie Huang pins1 { 277091cf598SEddie Huang pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 278091cf598SEddie Huang <MT8173_PIN_46_SCL0__FUNC_SCL0>; 279091cf598SEddie Huang bias-disable; 280091cf598SEddie Huang }; 281359f9365SHongzhou Yang }; 282359f9365SHongzhou Yang 283091cf598SEddie Huang i2c1_pins_a: i2c1 { 284091cf598SEddie Huang pins1 { 285091cf598SEddie Huang pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 286091cf598SEddie Huang <MT8173_PIN_126_SCL1__FUNC_SCL1>; 287091cf598SEddie Huang bias-disable; 288091cf598SEddie Huang }; 289091cf598SEddie Huang }; 290091cf598SEddie Huang 291091cf598SEddie Huang i2c2_pins_a: i2c2 { 292091cf598SEddie Huang pins1 { 293091cf598SEddie Huang pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 294091cf598SEddie Huang <MT8173_PIN_44_SCL2__FUNC_SCL2>; 295091cf598SEddie Huang bias-disable; 296091cf598SEddie Huang }; 297091cf598SEddie Huang }; 298091cf598SEddie Huang 299091cf598SEddie Huang i2c3_pins_a: i2c3 { 300091cf598SEddie Huang pins1 { 301091cf598SEddie Huang pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 302091cf598SEddie Huang <MT8173_PIN_107_SCL3__FUNC_SCL3>; 303091cf598SEddie Huang bias-disable; 304091cf598SEddie Huang }; 305091cf598SEddie Huang }; 306091cf598SEddie Huang 307091cf598SEddie Huang i2c4_pins_a: i2c4 { 308091cf598SEddie Huang pins1 { 309091cf598SEddie Huang pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 310091cf598SEddie Huang <MT8173_PIN_134_SCL4__FUNC_SCL4>; 311091cf598SEddie Huang bias-disable; 312091cf598SEddie Huang }; 313091cf598SEddie Huang }; 314091cf598SEddie Huang 315091cf598SEddie Huang i2c6_pins_a: i2c6 { 316091cf598SEddie Huang pins1 { 317091cf598SEddie Huang pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 318091cf598SEddie Huang <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 319091cf598SEddie Huang bias-disable; 320091cf598SEddie Huang }; 321091cf598SEddie Huang }; 3226769b93cSYingjoe Chen }; 3236769b93cSYingjoe Chen 324c010ff53SSascha Hauer scpsys: scpsys@10006000 { 325c010ff53SSascha Hauer compatible = "mediatek,mt8173-scpsys"; 326c010ff53SSascha Hauer #power-domain-cells = <1>; 327c010ff53SSascha Hauer reg = <0 0x10006000 0 0x1000>; 328c010ff53SSascha Hauer clocks = <&clk26m>, 329e34573c9SJames Liao <&topckgen CLK_TOP_MM_SEL>, 330e34573c9SJames Liao <&topckgen CLK_TOP_VENC_SEL>, 331e34573c9SJames Liao <&topckgen CLK_TOP_VENC_LT_SEL>; 332e34573c9SJames Liao clock-names = "mfg", "mm", "venc", "venc_lt"; 333c010ff53SSascha Hauer infracfg = <&infracfg>; 334c010ff53SSascha Hauer }; 335c010ff53SSascha Hauer 33613421b3eSEddie Huang watchdog: watchdog@10007000 { 33713421b3eSEddie Huang compatible = "mediatek,mt8173-wdt", 33813421b3eSEddie Huang "mediatek,mt6589-wdt"; 33913421b3eSEddie Huang reg = <0 0x10007000 0 0x100>; 34013421b3eSEddie Huang }; 34113421b3eSEddie Huang 342b2c76e27SDaniel Kurtz timer: timer@10008000 { 343b2c76e27SDaniel Kurtz compatible = "mediatek,mt8173-timer", 344b2c76e27SDaniel Kurtz "mediatek,mt6577-timer"; 345b2c76e27SDaniel Kurtz reg = <0 0x10008000 0 0x1000>; 346b2c76e27SDaniel Kurtz interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 347b2c76e27SDaniel Kurtz clocks = <&infracfg CLK_INFRA_CLK_13M>, 348b2c76e27SDaniel Kurtz <&topckgen CLK_TOP_RTC_SEL>; 349b2c76e27SDaniel Kurtz }; 350b2c76e27SDaniel Kurtz 3516cf15fc2SSascha Hauer pwrap: pwrap@1000d000 { 3526cf15fc2SSascha Hauer compatible = "mediatek,mt8173-pwrap"; 3536cf15fc2SSascha Hauer reg = <0 0x1000d000 0 0x1000>; 3546cf15fc2SSascha Hauer reg-names = "pwrap"; 3556cf15fc2SSascha Hauer interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 3566cf15fc2SSascha Hauer resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 3576cf15fc2SSascha Hauer reset-names = "pwrap"; 3586cf15fc2SSascha Hauer clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 3596cf15fc2SSascha Hauer clock-names = "spi", "wrap"; 3606cf15fc2SSascha Hauer }; 3616cf15fc2SSascha Hauer 362a10b57f4SCK Hu cec: cec@10013000 { 363a10b57f4SCK Hu compatible = "mediatek,mt8173-cec"; 364a10b57f4SCK Hu reg = <0 0x10013000 0 0xbc>; 365a10b57f4SCK Hu interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; 366a10b57f4SCK Hu clocks = <&infracfg CLK_INFRA_CEC>; 367a10b57f4SCK Hu status = "disabled"; 368a10b57f4SCK Hu }; 369a10b57f4SCK Hu 370404b2819SAndrew-CT Chen vpu: vpu@10020000 { 371404b2819SAndrew-CT Chen compatible = "mediatek,mt8173-vpu"; 372404b2819SAndrew-CT Chen reg = <0 0x10020000 0 0x30000>, 373404b2819SAndrew-CT Chen <0 0x10050000 0 0x100>; 374404b2819SAndrew-CT Chen reg-names = "tcm", "cfg_reg"; 375404b2819SAndrew-CT Chen interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 376404b2819SAndrew-CT Chen clocks = <&topckgen CLK_TOP_SCP_SEL>; 377404b2819SAndrew-CT Chen clock-names = "main"; 378404b2819SAndrew-CT Chen memory-region = <&vpu_dma_reserved>; 379404b2819SAndrew-CT Chen }; 380404b2819SAndrew-CT Chen 381b3a37248SEddie Huang sysirq: intpol-controller@10200620 { 382b3a37248SEddie Huang compatible = "mediatek,mt8173-sysirq", 383b3a37248SEddie Huang "mediatek,mt6577-sysirq"; 384b3a37248SEddie Huang interrupt-controller; 385b3a37248SEddie Huang #interrupt-cells = <3>; 386b3a37248SEddie Huang interrupt-parent = <&gic>; 387b3a37248SEddie Huang reg = <0 0x10200620 0 0x20>; 388b3a37248SEddie Huang }; 389b3a37248SEddie Huang 3905ff6b3a6SYong Wu iommu: iommu@10205000 { 3915ff6b3a6SYong Wu compatible = "mediatek,mt8173-m4u"; 3925ff6b3a6SYong Wu reg = <0 0x10205000 0 0x1000>; 3935ff6b3a6SYong Wu interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 3945ff6b3a6SYong Wu clocks = <&infracfg CLK_INFRA_M4U>; 3955ff6b3a6SYong Wu clock-names = "bclk"; 3965ff6b3a6SYong Wu mediatek,larbs = <&larb0 &larb1 &larb2 3975ff6b3a6SYong Wu &larb3 &larb4 &larb5>; 3985ff6b3a6SYong Wu #iommu-cells = <1>; 3995ff6b3a6SYong Wu }; 4005ff6b3a6SYong Wu 40193e9f5eeSandrew-ct.chen@mediatek.com efuse: efuse@10206000 { 40293e9f5eeSandrew-ct.chen@mediatek.com compatible = "mediatek,mt8173-efuse"; 40393e9f5eeSandrew-ct.chen@mediatek.com reg = <0 0x10206000 0 0x1000>; 4046de18454Sdawei.chien@mediatek.com #address-cells = <1>; 4056de18454Sdawei.chien@mediatek.com #size-cells = <1>; 4066de18454Sdawei.chien@mediatek.com thermal_calibration: calib@528 { 4076de18454Sdawei.chien@mediatek.com reg = <0x528 0xc>; 4086de18454Sdawei.chien@mediatek.com }; 40993e9f5eeSandrew-ct.chen@mediatek.com }; 41093e9f5eeSandrew-ct.chen@mediatek.com 411f2ce7014SSascha Hauer apmixedsys: clock-controller@10209000 { 412f2ce7014SSascha Hauer compatible = "mediatek,mt8173-apmixedsys"; 413f2ce7014SSascha Hauer reg = <0 0x10209000 0 0x1000>; 414f2ce7014SSascha Hauer #clock-cells = <1>; 415f2ce7014SSascha Hauer }; 416f2ce7014SSascha Hauer 417a10b57f4SCK Hu hdmi_phy: hdmi-phy@10209100 { 418a10b57f4SCK Hu compatible = "mediatek,mt8173-hdmi-phy"; 419a10b57f4SCK Hu reg = <0 0x10209100 0 0x24>; 420a10b57f4SCK Hu clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; 421a10b57f4SCK Hu clock-names = "pll_ref"; 422a10b57f4SCK Hu clock-output-names = "hdmitx_dig_cts"; 423a10b57f4SCK Hu mediatek,ibias = <0xa>; 424a10b57f4SCK Hu mediatek,ibias_up = <0x1c>; 425a10b57f4SCK Hu #clock-cells = <0>; 426a10b57f4SCK Hu #phy-cells = <0>; 427a10b57f4SCK Hu status = "disabled"; 428a10b57f4SCK Hu }; 429a10b57f4SCK Hu 43081ad4dbaSCK Hu mipi_tx0: mipi-dphy@10215000 { 43181ad4dbaSCK Hu compatible = "mediatek,mt8173-mipi-tx"; 43281ad4dbaSCK Hu reg = <0 0x10215000 0 0x1000>; 43381ad4dbaSCK Hu clocks = <&clk26m>; 43481ad4dbaSCK Hu clock-output-names = "mipi_tx0_pll"; 43581ad4dbaSCK Hu #clock-cells = <0>; 43681ad4dbaSCK Hu #phy-cells = <0>; 43781ad4dbaSCK Hu status = "disabled"; 43881ad4dbaSCK Hu }; 43981ad4dbaSCK Hu 44081ad4dbaSCK Hu mipi_tx1: mipi-dphy@10216000 { 44181ad4dbaSCK Hu compatible = "mediatek,mt8173-mipi-tx"; 44281ad4dbaSCK Hu reg = <0 0x10216000 0 0x1000>; 44381ad4dbaSCK Hu clocks = <&clk26m>; 44481ad4dbaSCK Hu clock-output-names = "mipi_tx1_pll"; 44581ad4dbaSCK Hu #clock-cells = <0>; 44681ad4dbaSCK Hu #phy-cells = <0>; 44781ad4dbaSCK Hu status = "disabled"; 44881ad4dbaSCK Hu }; 44981ad4dbaSCK Hu 450b3a37248SEddie Huang gic: interrupt-controller@10220000 { 451b3a37248SEddie Huang compatible = "arm,gic-400"; 452b3a37248SEddie Huang #interrupt-cells = <3>; 453b3a37248SEddie Huang interrupt-parent = <&gic>; 454b3a37248SEddie Huang interrupt-controller; 455b3a37248SEddie Huang reg = <0 0x10221000 0 0x1000>, 456b3a37248SEddie Huang <0 0x10222000 0 0x2000>, 457b3a37248SEddie Huang <0 0x10224000 0 0x2000>, 458b3a37248SEddie Huang <0 0x10226000 0 0x2000>; 459b3a37248SEddie Huang interrupts = <GIC_PPI 9 460b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 461b3a37248SEddie Huang }; 462b3a37248SEddie Huang 463748c7d4dSSascha Hauer auxadc: auxadc@11001000 { 464748c7d4dSSascha Hauer compatible = "mediatek,mt8173-auxadc"; 465748c7d4dSSascha Hauer reg = <0 0x11001000 0 0x1000>; 466a3207d64SMatthias Brugger clocks = <&pericfg CLK_PERI_AUXADC>; 467a3207d64SMatthias Brugger clock-names = "main"; 468a3207d64SMatthias Brugger #io-channel-cells = <1>; 469748c7d4dSSascha Hauer }; 470748c7d4dSSascha Hauer 471b3a37248SEddie Huang uart0: serial@11002000 { 472b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 473b3a37248SEddie Huang "mediatek,mt6577-uart"; 474b3a37248SEddie Huang reg = <0 0x11002000 0 0x400>; 475b3a37248SEddie Huang interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 4760e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 4770e84faa1SSascha Hauer clock-names = "baud", "bus"; 478b3a37248SEddie Huang status = "disabled"; 479b3a37248SEddie Huang }; 480b3a37248SEddie Huang 481b3a37248SEddie Huang uart1: serial@11003000 { 482b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 483b3a37248SEddie Huang "mediatek,mt6577-uart"; 484b3a37248SEddie Huang reg = <0 0x11003000 0 0x400>; 485b3a37248SEddie Huang interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 4860e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 4870e84faa1SSascha Hauer clock-names = "baud", "bus"; 488b3a37248SEddie Huang status = "disabled"; 489b3a37248SEddie Huang }; 490b3a37248SEddie Huang 491b3a37248SEddie Huang uart2: serial@11004000 { 492b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 493b3a37248SEddie Huang "mediatek,mt6577-uart"; 494b3a37248SEddie Huang reg = <0 0x11004000 0 0x400>; 495b3a37248SEddie Huang interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 4960e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 4970e84faa1SSascha Hauer clock-names = "baud", "bus"; 498b3a37248SEddie Huang status = "disabled"; 499b3a37248SEddie Huang }; 500b3a37248SEddie Huang 501b3a37248SEddie Huang uart3: serial@11005000 { 502b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 503b3a37248SEddie Huang "mediatek,mt6577-uart"; 504b3a37248SEddie Huang reg = <0 0x11005000 0 0x400>; 505b3a37248SEddie Huang interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 5060e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 5070e84faa1SSascha Hauer clock-names = "baud", "bus"; 508b3a37248SEddie Huang status = "disabled"; 509b3a37248SEddie Huang }; 510091cf598SEddie Huang 511091cf598SEddie Huang i2c0: i2c@11007000 { 512091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 513091cf598SEddie Huang reg = <0 0x11007000 0 0x70>, 514091cf598SEddie Huang <0 0x11000100 0 0x80>; 515091cf598SEddie Huang interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 516091cf598SEddie Huang clock-div = <16>; 517091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C0>, 518091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 519091cf598SEddie Huang clock-names = "main", "dma"; 520091cf598SEddie Huang pinctrl-names = "default"; 521091cf598SEddie Huang pinctrl-0 = <&i2c0_pins_a>; 522091cf598SEddie Huang #address-cells = <1>; 523091cf598SEddie Huang #size-cells = <0>; 524091cf598SEddie Huang status = "disabled"; 525091cf598SEddie Huang }; 526091cf598SEddie Huang 527091cf598SEddie Huang i2c1: i2c@11008000 { 528091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 529091cf598SEddie Huang reg = <0 0x11008000 0 0x70>, 530091cf598SEddie Huang <0 0x11000180 0 0x80>; 531091cf598SEddie Huang interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 532091cf598SEddie Huang clock-div = <16>; 533091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C1>, 534091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 535091cf598SEddie Huang clock-names = "main", "dma"; 536091cf598SEddie Huang pinctrl-names = "default"; 537091cf598SEddie Huang pinctrl-0 = <&i2c1_pins_a>; 538091cf598SEddie Huang #address-cells = <1>; 539091cf598SEddie Huang #size-cells = <0>; 540091cf598SEddie Huang status = "disabled"; 541091cf598SEddie Huang }; 542091cf598SEddie Huang 543091cf598SEddie Huang i2c2: i2c@11009000 { 544091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 545091cf598SEddie Huang reg = <0 0x11009000 0 0x70>, 546091cf598SEddie Huang <0 0x11000200 0 0x80>; 547091cf598SEddie Huang interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 548091cf598SEddie Huang clock-div = <16>; 549091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C2>, 550091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 551091cf598SEddie Huang clock-names = "main", "dma"; 552091cf598SEddie Huang pinctrl-names = "default"; 553091cf598SEddie Huang pinctrl-0 = <&i2c2_pins_a>; 554091cf598SEddie Huang #address-cells = <1>; 555091cf598SEddie Huang #size-cells = <0>; 556091cf598SEddie Huang status = "disabled"; 557091cf598SEddie Huang }; 558091cf598SEddie Huang 559b0c936f5SLeilk Liu spi: spi@1100a000 { 560b0c936f5SLeilk Liu compatible = "mediatek,mt8173-spi"; 561b0c936f5SLeilk Liu #address-cells = <1>; 562b0c936f5SLeilk Liu #size-cells = <0>; 563b0c936f5SLeilk Liu reg = <0 0x1100a000 0 0x1000>; 564b0c936f5SLeilk Liu interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 565b0c936f5SLeilk Liu clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 566b0c936f5SLeilk Liu <&topckgen CLK_TOP_SPI_SEL>, 567b0c936f5SLeilk Liu <&pericfg CLK_PERI_SPI0>; 568b0c936f5SLeilk Liu clock-names = "parent-clk", "sel-clk", "spi-clk"; 569b0c936f5SLeilk Liu status = "disabled"; 570b0c936f5SLeilk Liu }; 571b0c936f5SLeilk Liu 572748c7d4dSSascha Hauer thermal: thermal@1100b000 { 573748c7d4dSSascha Hauer #thermal-sensor-cells = <0>; 574748c7d4dSSascha Hauer compatible = "mediatek,mt8173-thermal"; 575748c7d4dSSascha Hauer reg = <0 0x1100b000 0 0x1000>; 576748c7d4dSSascha Hauer interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 577748c7d4dSSascha Hauer clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 578748c7d4dSSascha Hauer clock-names = "therm", "auxadc"; 579748c7d4dSSascha Hauer resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 580748c7d4dSSascha Hauer mediatek,auxadc = <&auxadc>; 581748c7d4dSSascha Hauer mediatek,apmixedsys = <&apmixedsys>; 5826de18454Sdawei.chien@mediatek.com nvmem-cells = <&thermal_calibration>; 5836de18454Sdawei.chien@mediatek.com nvmem-cell-names = "calibration-data"; 584748c7d4dSSascha Hauer }; 585748c7d4dSSascha Hauer 58686cb8a88SBayi Cheng nor_flash: spi@1100d000 { 58786cb8a88SBayi Cheng compatible = "mediatek,mt8173-nor"; 58886cb8a88SBayi Cheng reg = <0 0x1100d000 0 0xe0>; 58986cb8a88SBayi Cheng clocks = <&pericfg CLK_PERI_SPI>, 59086cb8a88SBayi Cheng <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 59186cb8a88SBayi Cheng clock-names = "spi", "sf"; 59286cb8a88SBayi Cheng #address-cells = <1>; 59386cb8a88SBayi Cheng #size-cells = <0>; 59486cb8a88SBayi Cheng status = "disabled"; 59586cb8a88SBayi Cheng }; 59686cb8a88SBayi Cheng 5971ee35c05SYingjoe Chen i2c3: i2c@11010000 { 598091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 599091cf598SEddie Huang reg = <0 0x11010000 0 0x70>, 600091cf598SEddie Huang <0 0x11000280 0 0x80>; 601091cf598SEddie Huang interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 602091cf598SEddie Huang clock-div = <16>; 603091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C3>, 604091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 605091cf598SEddie Huang clock-names = "main", "dma"; 606091cf598SEddie Huang pinctrl-names = "default"; 607091cf598SEddie Huang pinctrl-0 = <&i2c3_pins_a>; 608091cf598SEddie Huang #address-cells = <1>; 609091cf598SEddie Huang #size-cells = <0>; 610091cf598SEddie Huang status = "disabled"; 611091cf598SEddie Huang }; 612091cf598SEddie Huang 6131ee35c05SYingjoe Chen i2c4: i2c@11011000 { 614091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 615091cf598SEddie Huang reg = <0 0x11011000 0 0x70>, 616091cf598SEddie Huang <0 0x11000300 0 0x80>; 617091cf598SEddie Huang interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 618091cf598SEddie Huang clock-div = <16>; 619091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C4>, 620091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 621091cf598SEddie Huang clock-names = "main", "dma"; 622091cf598SEddie Huang pinctrl-names = "default"; 623091cf598SEddie Huang pinctrl-0 = <&i2c4_pins_a>; 624091cf598SEddie Huang #address-cells = <1>; 625091cf598SEddie Huang #size-cells = <0>; 626091cf598SEddie Huang status = "disabled"; 627091cf598SEddie Huang }; 628091cf598SEddie Huang 629a10b57f4SCK Hu hdmiddc0: i2c@11012000 { 630a10b57f4SCK Hu compatible = "mediatek,mt8173-hdmi-ddc"; 631a10b57f4SCK Hu interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 632a10b57f4SCK Hu reg = <0 0x11012000 0 0x1C>; 633a10b57f4SCK Hu clocks = <&pericfg CLK_PERI_I2C5>; 634a10b57f4SCK Hu clock-names = "ddc-i2c"; 635a10b57f4SCK Hu }; 636a10b57f4SCK Hu 6371ee35c05SYingjoe Chen i2c6: i2c@11013000 { 638091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 639091cf598SEddie Huang reg = <0 0x11013000 0 0x70>, 640091cf598SEddie Huang <0 0x11000080 0 0x80>; 641091cf598SEddie Huang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 642091cf598SEddie Huang clock-div = <16>; 643091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C6>, 644091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 645091cf598SEddie Huang clock-names = "main", "dma"; 646091cf598SEddie Huang pinctrl-names = "default"; 647091cf598SEddie Huang pinctrl-0 = <&i2c6_pins_a>; 648091cf598SEddie Huang #address-cells = <1>; 649091cf598SEddie Huang #size-cells = <0>; 650091cf598SEddie Huang status = "disabled"; 651091cf598SEddie Huang }; 652c02e0e86SKoro Chen 653c02e0e86SKoro Chen afe: audio-controller@11220000 { 654c02e0e86SKoro Chen compatible = "mediatek,mt8173-afe-pcm"; 655c02e0e86SKoro Chen reg = <0 0x11220000 0 0x1000>; 656c02e0e86SKoro Chen interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 657c02e0e86SKoro Chen power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; 658c02e0e86SKoro Chen clocks = <&infracfg CLK_INFRA_AUDIO>, 659c02e0e86SKoro Chen <&topckgen CLK_TOP_AUDIO_SEL>, 660c02e0e86SKoro Chen <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 661c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL1_DIV0>, 662c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL2_DIV0>, 663c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S0_M_SEL>, 664c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S1_M_SEL>, 665c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S2_M_SEL>, 666c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S3_M_SEL>, 667c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S3_B_SEL>; 668c02e0e86SKoro Chen clock-names = "infra_sys_audio_clk", 669c02e0e86SKoro Chen "top_pdn_audio", 670c02e0e86SKoro Chen "top_pdn_aud_intbus", 671c02e0e86SKoro Chen "bck0", 672c02e0e86SKoro Chen "bck1", 673c02e0e86SKoro Chen "i2s0_m", 674c02e0e86SKoro Chen "i2s1_m", 675c02e0e86SKoro Chen "i2s2_m", 676c02e0e86SKoro Chen "i2s3_m", 677c02e0e86SKoro Chen "i2s3_b"; 678c02e0e86SKoro Chen assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 679c02e0e86SKoro Chen <&topckgen CLK_TOP_AUD_2_SEL>; 680c02e0e86SKoro Chen assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 681c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL2>; 682c02e0e86SKoro Chen }; 6839719fa5aSEddie Huang 6849719fa5aSEddie Huang mmc0: mmc@11230000 { 6859719fa5aSEddie Huang compatible = "mediatek,mt8173-mmc", 6869719fa5aSEddie Huang "mediatek,mt8135-mmc"; 6879719fa5aSEddie Huang reg = <0 0x11230000 0 0x1000>; 6889719fa5aSEddie Huang interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 6899719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_0>, 6909719fa5aSEddie Huang <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 6919719fa5aSEddie Huang clock-names = "source", "hclk"; 6929719fa5aSEddie Huang status = "disabled"; 6939719fa5aSEddie Huang }; 6949719fa5aSEddie Huang 6959719fa5aSEddie Huang mmc1: mmc@11240000 { 6969719fa5aSEddie Huang compatible = "mediatek,mt8173-mmc", 6979719fa5aSEddie Huang "mediatek,mt8135-mmc"; 6989719fa5aSEddie Huang reg = <0 0x11240000 0 0x1000>; 6999719fa5aSEddie Huang interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 7009719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_1>, 7019719fa5aSEddie Huang <&topckgen CLK_TOP_AXI_SEL>; 7029719fa5aSEddie Huang clock-names = "source", "hclk"; 7039719fa5aSEddie Huang status = "disabled"; 7049719fa5aSEddie Huang }; 7059719fa5aSEddie Huang 7069719fa5aSEddie Huang mmc2: mmc@11250000 { 7079719fa5aSEddie Huang compatible = "mediatek,mt8173-mmc", 7089719fa5aSEddie Huang "mediatek,mt8135-mmc"; 7099719fa5aSEddie Huang reg = <0 0x11250000 0 0x1000>; 7109719fa5aSEddie Huang interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 7119719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_2>, 7129719fa5aSEddie Huang <&topckgen CLK_TOP_AXI_SEL>; 7139719fa5aSEddie Huang clock-names = "source", "hclk"; 7149719fa5aSEddie Huang status = "disabled"; 7159719fa5aSEddie Huang }; 7169719fa5aSEddie Huang 7179719fa5aSEddie Huang mmc3: mmc@11260000 { 7189719fa5aSEddie Huang compatible = "mediatek,mt8173-mmc", 7199719fa5aSEddie Huang "mediatek,mt8135-mmc"; 7209719fa5aSEddie Huang reg = <0 0x11260000 0 0x1000>; 7219719fa5aSEddie Huang interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 7229719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_3>, 7239719fa5aSEddie Huang <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 7249719fa5aSEddie Huang clock-names = "source", "hclk"; 7259719fa5aSEddie Huang status = "disabled"; 7269719fa5aSEddie Huang }; 72767e56c56SJames Liao 728c0891284SChunfeng Yun ssusb: usb@11271000 { 729c0891284SChunfeng Yun compatible = "mediatek,mt8173-mtu3"; 730c0891284SChunfeng Yun reg = <0 0x11271000 0 0x3000>, 731bfcce47aSChunfeng Yun <0 0x11280700 0 0x0100>; 732c0891284SChunfeng Yun reg-names = "mac", "ippc"; 733c0891284SChunfeng Yun interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>; 734ebf61c63Schunfeng.yun@mediatek.com phys = <&u2port0 PHY_TYPE_USB2>, 735ebf61c63Schunfeng.yun@mediatek.com <&u3port0 PHY_TYPE_USB3>, 736ebf61c63Schunfeng.yun@mediatek.com <&u2port1 PHY_TYPE_USB2>; 737bfcce47aSChunfeng Yun power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 738bfcce47aSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>, 739cb6efc7bSChunfeng Yun <&clk26m>, 740bfcce47aSChunfeng Yun <&pericfg CLK_PERI_USB0>, 741bfcce47aSChunfeng Yun <&pericfg CLK_PERI_USB1>; 742bfcce47aSChunfeng Yun clock-names = "sys_ck", 743cb6efc7bSChunfeng Yun "ref_ck", 744bfcce47aSChunfeng Yun "wakeup_deb_p0", 745bfcce47aSChunfeng Yun "wakeup_deb_p1"; 746bfcce47aSChunfeng Yun mediatek,syscon-wakeup = <&pericfg>; 747c0891284SChunfeng Yun #address-cells = <2>; 748c0891284SChunfeng Yun #size-cells = <2>; 749c0891284SChunfeng Yun ranges; 750c0891284SChunfeng Yun status = "disabled"; 751c0891284SChunfeng Yun 752c0891284SChunfeng Yun usb_host: xhci@11270000 { 753c0891284SChunfeng Yun compatible = "mediatek,mt8173-xhci"; 754c0891284SChunfeng Yun reg = <0 0x11270000 0 0x1000>; 755c0891284SChunfeng Yun reg-names = "mac"; 756c0891284SChunfeng Yun interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 757c0891284SChunfeng Yun power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 758cb6efc7bSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 759cb6efc7bSChunfeng Yun clock-names = "sys_ck", "ref_ck"; 760c0891284SChunfeng Yun status = "disabled"; 761c0891284SChunfeng Yun }; 762bfcce47aSChunfeng Yun }; 763bfcce47aSChunfeng Yun 764bfcce47aSChunfeng Yun u3phy: usb-phy@11290000 { 765bfcce47aSChunfeng Yun compatible = "mediatek,mt8173-u3phy"; 766bfcce47aSChunfeng Yun reg = <0 0x11290000 0 0x800>; 767bfcce47aSChunfeng Yun clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 768bfcce47aSChunfeng Yun clock-names = "u3phya_ref"; 769bfcce47aSChunfeng Yun #address-cells = <2>; 770bfcce47aSChunfeng Yun #size-cells = <2>; 771bfcce47aSChunfeng Yun ranges; 772bfcce47aSChunfeng Yun status = "okay"; 773bfcce47aSChunfeng Yun 774ebf61c63Schunfeng.yun@mediatek.com u2port0: usb-phy@11290800 { 775ebf61c63Schunfeng.yun@mediatek.com reg = <0 0x11290800 0 0x100>; 776bfcce47aSChunfeng Yun #phy-cells = <1>; 777bfcce47aSChunfeng Yun status = "okay"; 778bfcce47aSChunfeng Yun }; 779bfcce47aSChunfeng Yun 780ebf61c63Schunfeng.yun@mediatek.com u3port0: usb-phy@11290900 { 781ebf61c63Schunfeng.yun@mediatek.com reg = <0 0x11290900 0 0x700>; 782ebf61c63Schunfeng.yun@mediatek.com #phy-cells = <1>; 783ebf61c63Schunfeng.yun@mediatek.com status = "okay"; 784ebf61c63Schunfeng.yun@mediatek.com }; 785ebf61c63Schunfeng.yun@mediatek.com 786ebf61c63Schunfeng.yun@mediatek.com u2port1: usb-phy@11291000 { 787ebf61c63Schunfeng.yun@mediatek.com reg = <0 0x11291000 0 0x100>; 788bfcce47aSChunfeng Yun #phy-cells = <1>; 789bfcce47aSChunfeng Yun status = "okay"; 790bfcce47aSChunfeng Yun }; 791bfcce47aSChunfeng Yun }; 792bfcce47aSChunfeng Yun 79367e56c56SJames Liao mmsys: clock-controller@14000000 { 79467e56c56SJames Liao compatible = "mediatek,mt8173-mmsys", "syscon"; 79567e56c56SJames Liao reg = <0 0x14000000 0 0x1000>; 79681ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 797fc6634acSBibby Hsieh assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; 798fc6634acSBibby Hsieh assigned-clock-rates = <400000000>; 79967e56c56SJames Liao #clock-cells = <1>; 80067e56c56SJames Liao }; 80167e56c56SJames Liao 802989b292aSMinghsiu Tsai mdp { 803989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp"; 804989b292aSMinghsiu Tsai #address-cells = <2>; 805989b292aSMinghsiu Tsai #size-cells = <2>; 806989b292aSMinghsiu Tsai ranges; 807989b292aSMinghsiu Tsai mediatek,vpu = <&vpu>; 808989b292aSMinghsiu Tsai 809989b292aSMinghsiu Tsai mdp_rdma0: rdma@14001000 { 810989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rdma"; 811989b292aSMinghsiu Tsai reg = <0 0x14001000 0 0x1000>; 812989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RDMA0>, 813989b292aSMinghsiu Tsai <&mmsys CLK_MM_MUTEX_32K>; 814989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 815989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_RDMA0>; 816989b292aSMinghsiu Tsai mediatek,larb = <&larb0>; 817989b292aSMinghsiu Tsai }; 818989b292aSMinghsiu Tsai 819989b292aSMinghsiu Tsai mdp_rdma1: rdma@14002000 { 820989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rdma"; 821989b292aSMinghsiu Tsai reg = <0 0x14002000 0 0x1000>; 822989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RDMA1>, 823989b292aSMinghsiu Tsai <&mmsys CLK_MM_MUTEX_32K>; 824989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 825989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_RDMA1>; 826989b292aSMinghsiu Tsai mediatek,larb = <&larb4>; 827989b292aSMinghsiu Tsai }; 828989b292aSMinghsiu Tsai 829989b292aSMinghsiu Tsai mdp_rsz0: rsz@14003000 { 830989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rsz"; 831989b292aSMinghsiu Tsai reg = <0 0x14003000 0 0x1000>; 832989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RSZ0>; 833989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 834989b292aSMinghsiu Tsai }; 835989b292aSMinghsiu Tsai 836989b292aSMinghsiu Tsai mdp_rsz1: rsz@14004000 { 837989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rsz"; 838989b292aSMinghsiu Tsai reg = <0 0x14004000 0 0x1000>; 839989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RSZ1>; 840989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 841989b292aSMinghsiu Tsai }; 842989b292aSMinghsiu Tsai 843989b292aSMinghsiu Tsai mdp_rsz2: rsz@14005000 { 844989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rsz"; 845989b292aSMinghsiu Tsai reg = <0 0x14005000 0 0x1000>; 846989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RSZ2>; 847989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 848989b292aSMinghsiu Tsai }; 849989b292aSMinghsiu Tsai 850989b292aSMinghsiu Tsai mdp_wdma0: wdma@14006000 { 851989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-wdma"; 852989b292aSMinghsiu Tsai reg = <0 0x14006000 0 0x1000>; 853989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_WDMA>; 854989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 855989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_WDMA>; 856989b292aSMinghsiu Tsai mediatek,larb = <&larb0>; 857989b292aSMinghsiu Tsai }; 858989b292aSMinghsiu Tsai 859989b292aSMinghsiu Tsai mdp_wrot0: wrot@14007000 { 860989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-wrot"; 861989b292aSMinghsiu Tsai reg = <0 0x14007000 0 0x1000>; 862989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_WROT0>; 863989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 864989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_WROT0>; 865989b292aSMinghsiu Tsai mediatek,larb = <&larb0>; 866989b292aSMinghsiu Tsai }; 867989b292aSMinghsiu Tsai 868989b292aSMinghsiu Tsai mdp_wrot1: wrot@14008000 { 869989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-wrot"; 870989b292aSMinghsiu Tsai reg = <0 0x14008000 0 0x1000>; 871989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_WROT1>; 872989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 873989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_WROT1>; 874989b292aSMinghsiu Tsai mediatek,larb = <&larb4>; 875989b292aSMinghsiu Tsai }; 876989b292aSMinghsiu Tsai }; 877989b292aSMinghsiu Tsai 87881ad4dbaSCK Hu ovl0: ovl@1400c000 { 87981ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-ovl"; 88081ad4dbaSCK Hu reg = <0 0x1400c000 0 0x1000>; 88181ad4dbaSCK Hu interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 88281ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 88381ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_OVL0>; 88481ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_OVL0>; 88581ad4dbaSCK Hu mediatek,larb = <&larb0>; 88681ad4dbaSCK Hu }; 88781ad4dbaSCK Hu 88881ad4dbaSCK Hu ovl1: ovl@1400d000 { 88981ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-ovl"; 89081ad4dbaSCK Hu reg = <0 0x1400d000 0 0x1000>; 89181ad4dbaSCK Hu interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; 89281ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 89381ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_OVL1>; 89481ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_OVL1>; 89581ad4dbaSCK Hu mediatek,larb = <&larb4>; 89681ad4dbaSCK Hu }; 89781ad4dbaSCK Hu 89881ad4dbaSCK Hu rdma0: rdma@1400e000 { 89981ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-rdma"; 90081ad4dbaSCK Hu reg = <0 0x1400e000 0 0x1000>; 90181ad4dbaSCK Hu interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 90281ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 90381ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_RDMA0>; 90481ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_RDMA0>; 90581ad4dbaSCK Hu mediatek,larb = <&larb0>; 90681ad4dbaSCK Hu }; 90781ad4dbaSCK Hu 90881ad4dbaSCK Hu rdma1: rdma@1400f000 { 90981ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-rdma"; 91081ad4dbaSCK Hu reg = <0 0x1400f000 0 0x1000>; 91181ad4dbaSCK Hu interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; 91281ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 91381ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_RDMA1>; 91481ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_RDMA1>; 91581ad4dbaSCK Hu mediatek,larb = <&larb4>; 91681ad4dbaSCK Hu }; 91781ad4dbaSCK Hu 91881ad4dbaSCK Hu rdma2: rdma@14010000 { 91981ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-rdma"; 92081ad4dbaSCK Hu reg = <0 0x14010000 0 0x1000>; 92181ad4dbaSCK Hu interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; 92281ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 92381ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_RDMA2>; 92481ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_RDMA2>; 92581ad4dbaSCK Hu mediatek,larb = <&larb4>; 92681ad4dbaSCK Hu }; 92781ad4dbaSCK Hu 92881ad4dbaSCK Hu wdma0: wdma@14011000 { 92981ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-wdma"; 93081ad4dbaSCK Hu reg = <0 0x14011000 0 0x1000>; 93181ad4dbaSCK Hu interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 93281ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 93381ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_WDMA0>; 93481ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_WDMA0>; 93581ad4dbaSCK Hu mediatek,larb = <&larb0>; 93681ad4dbaSCK Hu }; 93781ad4dbaSCK Hu 93881ad4dbaSCK Hu wdma1: wdma@14012000 { 93981ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-wdma"; 94081ad4dbaSCK Hu reg = <0 0x14012000 0 0x1000>; 94181ad4dbaSCK Hu interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; 94281ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 94381ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_WDMA1>; 94481ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_WDMA1>; 94581ad4dbaSCK Hu mediatek,larb = <&larb4>; 94681ad4dbaSCK Hu }; 94781ad4dbaSCK Hu 94881ad4dbaSCK Hu color0: color@14013000 { 94981ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-color"; 95081ad4dbaSCK Hu reg = <0 0x14013000 0 0x1000>; 95181ad4dbaSCK Hu interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; 95281ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 95381ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_COLOR0>; 95481ad4dbaSCK Hu }; 95581ad4dbaSCK Hu 95681ad4dbaSCK Hu color1: color@14014000 { 95781ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-color"; 95881ad4dbaSCK Hu reg = <0 0x14014000 0 0x1000>; 95981ad4dbaSCK Hu interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 96081ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 96181ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_COLOR1>; 96281ad4dbaSCK Hu }; 96381ad4dbaSCK Hu 96481ad4dbaSCK Hu aal@14015000 { 96581ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-aal"; 96681ad4dbaSCK Hu reg = <0 0x14015000 0 0x1000>; 96781ad4dbaSCK Hu interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 96881ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 96981ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_AAL>; 97081ad4dbaSCK Hu }; 97181ad4dbaSCK Hu 97281ad4dbaSCK Hu gamma@14016000 { 97381ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-gamma"; 97481ad4dbaSCK Hu reg = <0 0x14016000 0 0x1000>; 97581ad4dbaSCK Hu interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 97681ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 97781ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_GAMMA>; 97881ad4dbaSCK Hu }; 97981ad4dbaSCK Hu 98081ad4dbaSCK Hu merge@14017000 { 98181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-merge"; 98281ad4dbaSCK Hu reg = <0 0x14017000 0 0x1000>; 98381ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 98481ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_MERGE>; 98581ad4dbaSCK Hu }; 98681ad4dbaSCK Hu 98781ad4dbaSCK Hu split0: split@14018000 { 98881ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-split"; 98981ad4dbaSCK Hu reg = <0 0x14018000 0 0x1000>; 99081ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 99181ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_SPLIT0>; 99281ad4dbaSCK Hu }; 99381ad4dbaSCK Hu 99481ad4dbaSCK Hu split1: split@14019000 { 99581ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-split"; 99681ad4dbaSCK Hu reg = <0 0x14019000 0 0x1000>; 99781ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 99881ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_SPLIT1>; 99981ad4dbaSCK Hu }; 100081ad4dbaSCK Hu 100181ad4dbaSCK Hu ufoe@1401a000 { 100281ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-ufoe"; 100381ad4dbaSCK Hu reg = <0 0x1401a000 0 0x1000>; 100481ad4dbaSCK Hu interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 100581ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 100681ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_UFOE>; 100781ad4dbaSCK Hu }; 100881ad4dbaSCK Hu 100981ad4dbaSCK Hu dsi0: dsi@1401b000 { 101081ad4dbaSCK Hu compatible = "mediatek,mt8173-dsi"; 101181ad4dbaSCK Hu reg = <0 0x1401b000 0 0x1000>; 101281ad4dbaSCK Hu interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 101381ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 101481ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DSI0_ENGINE>, 101581ad4dbaSCK Hu <&mmsys CLK_MM_DSI0_DIGITAL>, 101681ad4dbaSCK Hu <&mipi_tx0>; 101781ad4dbaSCK Hu clock-names = "engine", "digital", "hs"; 101881ad4dbaSCK Hu phys = <&mipi_tx0>; 101981ad4dbaSCK Hu phy-names = "dphy"; 102081ad4dbaSCK Hu status = "disabled"; 102181ad4dbaSCK Hu }; 102281ad4dbaSCK Hu 102381ad4dbaSCK Hu dsi1: dsi@1401c000 { 102481ad4dbaSCK Hu compatible = "mediatek,mt8173-dsi"; 102581ad4dbaSCK Hu reg = <0 0x1401c000 0 0x1000>; 102681ad4dbaSCK Hu interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 102781ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 102881ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DSI1_ENGINE>, 102981ad4dbaSCK Hu <&mmsys CLK_MM_DSI1_DIGITAL>, 103081ad4dbaSCK Hu <&mipi_tx1>; 103181ad4dbaSCK Hu clock-names = "engine", "digital", "hs"; 103281ad4dbaSCK Hu phy = <&mipi_tx1>; 103381ad4dbaSCK Hu phy-names = "dphy"; 103481ad4dbaSCK Hu status = "disabled"; 103581ad4dbaSCK Hu }; 103681ad4dbaSCK Hu 103781ad4dbaSCK Hu dpi0: dpi@1401d000 { 103881ad4dbaSCK Hu compatible = "mediatek,mt8173-dpi"; 103981ad4dbaSCK Hu reg = <0 0x1401d000 0 0x1000>; 104081ad4dbaSCK Hu interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 104181ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 104281ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DPI_PIXEL>, 104381ad4dbaSCK Hu <&mmsys CLK_MM_DPI_ENGINE>, 104481ad4dbaSCK Hu <&apmixedsys CLK_APMIXED_TVDPLL>; 104581ad4dbaSCK Hu clock-names = "pixel", "engine", "pll"; 104681ad4dbaSCK Hu status = "disabled"; 1047a10b57f4SCK Hu 1048a10b57f4SCK Hu port { 1049a10b57f4SCK Hu dpi0_out: endpoint { 1050a10b57f4SCK Hu remote-endpoint = <&hdmi0_in>; 1051a10b57f4SCK Hu }; 1052a10b57f4SCK Hu }; 105381ad4dbaSCK Hu }; 105481ad4dbaSCK Hu 105561aee934SYH Huang pwm0: pwm@1401e000 { 105661aee934SYH Huang compatible = "mediatek,mt8173-disp-pwm", 105761aee934SYH Huang "mediatek,mt6595-disp-pwm"; 105861aee934SYH Huang reg = <0 0x1401e000 0 0x1000>; 105961aee934SYH Huang #pwm-cells = <2>; 106061aee934SYH Huang clocks = <&mmsys CLK_MM_DISP_PWM026M>, 106161aee934SYH Huang <&mmsys CLK_MM_DISP_PWM0MM>; 106261aee934SYH Huang clock-names = "main", "mm"; 106361aee934SYH Huang status = "disabled"; 106461aee934SYH Huang }; 106561aee934SYH Huang 106661aee934SYH Huang pwm1: pwm@1401f000 { 106761aee934SYH Huang compatible = "mediatek,mt8173-disp-pwm", 106861aee934SYH Huang "mediatek,mt6595-disp-pwm"; 106961aee934SYH Huang reg = <0 0x1401f000 0 0x1000>; 107061aee934SYH Huang #pwm-cells = <2>; 107161aee934SYH Huang clocks = <&mmsys CLK_MM_DISP_PWM126M>, 107261aee934SYH Huang <&mmsys CLK_MM_DISP_PWM1MM>; 107361aee934SYH Huang clock-names = "main", "mm"; 107461aee934SYH Huang status = "disabled"; 107561aee934SYH Huang }; 107661aee934SYH Huang 107781ad4dbaSCK Hu mutex: mutex@14020000 { 107881ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-mutex"; 107981ad4dbaSCK Hu reg = <0 0x14020000 0 0x1000>; 108081ad4dbaSCK Hu interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 108181ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 108281ad4dbaSCK Hu clocks = <&mmsys CLK_MM_MUTEX_32K>; 108381ad4dbaSCK Hu }; 108481ad4dbaSCK Hu 10855ff6b3a6SYong Wu larb0: larb@14021000 { 10865ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 10875ff6b3a6SYong Wu reg = <0 0x14021000 0 0x1000>; 10885ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 10895ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 10905ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_LARB0>, 10915ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_LARB0>; 10925ff6b3a6SYong Wu clock-names = "apb", "smi"; 10935ff6b3a6SYong Wu }; 10945ff6b3a6SYong Wu 10955ff6b3a6SYong Wu smi_common: smi@14022000 { 10965ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-common"; 10975ff6b3a6SYong Wu reg = <0 0x14022000 0 0x1000>; 10985ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 10995ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_COMMON>, 11005ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_COMMON>; 11015ff6b3a6SYong Wu clock-names = "apb", "smi"; 11025ff6b3a6SYong Wu }; 11035ff6b3a6SYong Wu 110481ad4dbaSCK Hu od@14023000 { 110581ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-od"; 110681ad4dbaSCK Hu reg = <0 0x14023000 0 0x1000>; 110781ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_OD>; 110881ad4dbaSCK Hu }; 110981ad4dbaSCK Hu 1110a10b57f4SCK Hu hdmi0: hdmi@14025000 { 1111a10b57f4SCK Hu compatible = "mediatek,mt8173-hdmi"; 1112a10b57f4SCK Hu reg = <0 0x14025000 0 0x400>; 1113a10b57f4SCK Hu interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>; 1114a10b57f4SCK Hu clocks = <&mmsys CLK_MM_HDMI_PIXEL>, 1115a10b57f4SCK Hu <&mmsys CLK_MM_HDMI_PLLCK>, 1116a10b57f4SCK Hu <&mmsys CLK_MM_HDMI_AUDIO>, 1117a10b57f4SCK Hu <&mmsys CLK_MM_HDMI_SPDIF>; 1118a10b57f4SCK Hu clock-names = "pixel", "pll", "bclk", "spdif"; 1119a10b57f4SCK Hu pinctrl-names = "default"; 1120a10b57f4SCK Hu pinctrl-0 = <&hdmi_pin>; 1121a10b57f4SCK Hu phys = <&hdmi_phy>; 1122a10b57f4SCK Hu phy-names = "hdmi"; 1123a10b57f4SCK Hu mediatek,syscon-hdmi = <&mmsys 0x900>; 1124a10b57f4SCK Hu assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; 1125a10b57f4SCK Hu assigned-clock-parents = <&hdmi_phy>; 1126a10b57f4SCK Hu status = "disabled"; 1127a10b57f4SCK Hu 1128a10b57f4SCK Hu ports { 1129a10b57f4SCK Hu #address-cells = <1>; 1130a10b57f4SCK Hu #size-cells = <0>; 1131a10b57f4SCK Hu 1132a10b57f4SCK Hu port@0 { 1133a10b57f4SCK Hu reg = <0>; 1134a10b57f4SCK Hu 1135a10b57f4SCK Hu hdmi0_in: endpoint { 1136a10b57f4SCK Hu remote-endpoint = <&dpi0_out>; 1137a10b57f4SCK Hu }; 1138a10b57f4SCK Hu }; 1139a10b57f4SCK Hu }; 1140a10b57f4SCK Hu }; 1141a10b57f4SCK Hu 11425ff6b3a6SYong Wu larb4: larb@14027000 { 11435ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 11445ff6b3a6SYong Wu reg = <0 0x14027000 0 0x1000>; 11455ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 11465ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 11475ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_LARB4>, 11485ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_LARB4>; 11495ff6b3a6SYong Wu clock-names = "apb", "smi"; 11505ff6b3a6SYong Wu }; 11515ff6b3a6SYong Wu 115267e56c56SJames Liao imgsys: clock-controller@15000000 { 115367e56c56SJames Liao compatible = "mediatek,mt8173-imgsys", "syscon"; 115467e56c56SJames Liao reg = <0 0x15000000 0 0x1000>; 115567e56c56SJames Liao #clock-cells = <1>; 115667e56c56SJames Liao }; 115767e56c56SJames Liao 11585ff6b3a6SYong Wu larb2: larb@15001000 { 11595ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 11605ff6b3a6SYong Wu reg = <0 0x15001000 0 0x1000>; 11615ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 11625ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>; 11635ff6b3a6SYong Wu clocks = <&imgsys CLK_IMG_LARB2_SMI>, 11645ff6b3a6SYong Wu <&imgsys CLK_IMG_LARB2_SMI>; 11655ff6b3a6SYong Wu clock-names = "apb", "smi"; 11665ff6b3a6SYong Wu }; 11675ff6b3a6SYong Wu 116867e56c56SJames Liao vdecsys: clock-controller@16000000 { 116967e56c56SJames Liao compatible = "mediatek,mt8173-vdecsys", "syscon"; 117067e56c56SJames Liao reg = <0 0x16000000 0 0x1000>; 117167e56c56SJames Liao #clock-cells = <1>; 117267e56c56SJames Liao }; 117367e56c56SJames Liao 117460eaae2bSTiffany Lin vcodec_dec: vcodec@16000000 { 117560eaae2bSTiffany Lin compatible = "mediatek,mt8173-vcodec-dec"; 117660eaae2bSTiffany Lin reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */ 117760eaae2bSTiffany Lin <0 0x16020000 0 0x1000>, /* VDEC_MISC */ 117860eaae2bSTiffany Lin <0 0x16021000 0 0x800>, /* VDEC_LD */ 117960eaae2bSTiffany Lin <0 0x16021800 0 0x800>, /* VDEC_TOP */ 118060eaae2bSTiffany Lin <0 0x16022000 0 0x1000>, /* VDEC_CM */ 118160eaae2bSTiffany Lin <0 0x16023000 0 0x1000>, /* VDEC_AD */ 118260eaae2bSTiffany Lin <0 0x16024000 0 0x1000>, /* VDEC_AV */ 118360eaae2bSTiffany Lin <0 0x16025000 0 0x1000>, /* VDEC_PP */ 118460eaae2bSTiffany Lin <0 0x16026800 0 0x800>, /* VDEC_HWD */ 118560eaae2bSTiffany Lin <0 0x16027000 0 0x800>, /* VDEC_HWQ */ 118660eaae2bSTiffany Lin <0 0x16027800 0 0x800>, /* VDEC_HWB */ 118760eaae2bSTiffany Lin <0 0x16028400 0 0x400>; /* VDEC_HWG */ 118860eaae2bSTiffany Lin interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; 118960eaae2bSTiffany Lin mediatek,larb = <&larb1>; 119060eaae2bSTiffany Lin iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, 119160eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_PP_EXT>, 119260eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, 119360eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, 119460eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, 119560eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, 119660eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, 119760eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; 119860eaae2bSTiffany Lin mediatek,vpu = <&vpu>; 119960eaae2bSTiffany Lin power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 120060eaae2bSTiffany Lin clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, 120160eaae2bSTiffany Lin <&topckgen CLK_TOP_UNIVPLL_D2>, 120260eaae2bSTiffany Lin <&topckgen CLK_TOP_CCI400_SEL>, 120360eaae2bSTiffany Lin <&topckgen CLK_TOP_VDEC_SEL>, 120460eaae2bSTiffany Lin <&topckgen CLK_TOP_VCODECPLL>, 120560eaae2bSTiffany Lin <&apmixedsys CLK_APMIXED_VENCPLL>, 120660eaae2bSTiffany Lin <&topckgen CLK_TOP_VENC_LT_SEL>, 120760eaae2bSTiffany Lin <&topckgen CLK_TOP_VCODECPLL_370P5>; 120860eaae2bSTiffany Lin clock-names = "vcodecpll", 120960eaae2bSTiffany Lin "univpll_d2", 121060eaae2bSTiffany Lin "clk_cci400_sel", 121160eaae2bSTiffany Lin "vdec_sel", 121260eaae2bSTiffany Lin "vdecpll", 121360eaae2bSTiffany Lin "vencpll", 121460eaae2bSTiffany Lin "venc_lt_sel", 121560eaae2bSTiffany Lin "vdec_bus_clk_src"; 121660eaae2bSTiffany Lin }; 121760eaae2bSTiffany Lin 12185ff6b3a6SYong Wu larb1: larb@16010000 { 12195ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 12205ff6b3a6SYong Wu reg = <0 0x16010000 0 0x1000>; 12215ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 12225ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 12235ff6b3a6SYong Wu clocks = <&vdecsys CLK_VDEC_CKEN>, 12245ff6b3a6SYong Wu <&vdecsys CLK_VDEC_LARB_CKEN>; 12255ff6b3a6SYong Wu clock-names = "apb", "smi"; 12265ff6b3a6SYong Wu }; 12275ff6b3a6SYong Wu 122867e56c56SJames Liao vencsys: clock-controller@18000000 { 122967e56c56SJames Liao compatible = "mediatek,mt8173-vencsys", "syscon"; 123067e56c56SJames Liao reg = <0 0x18000000 0 0x1000>; 123167e56c56SJames Liao #clock-cells = <1>; 123267e56c56SJames Liao }; 123367e56c56SJames Liao 12345ff6b3a6SYong Wu larb3: larb@18001000 { 12355ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 12365ff6b3a6SYong Wu reg = <0 0x18001000 0 0x1000>; 12375ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 12385ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 12395ff6b3a6SYong Wu clocks = <&vencsys CLK_VENC_CKE1>, 12405ff6b3a6SYong Wu <&vencsys CLK_VENC_CKE0>; 12415ff6b3a6SYong Wu clock-names = "apb", "smi"; 12425ff6b3a6SYong Wu }; 12435ff6b3a6SYong Wu 12448eb80252STiffany Lin vcodec_enc: vcodec@18002000 { 12458eb80252STiffany Lin compatible = "mediatek,mt8173-vcodec-enc"; 12468eb80252STiffany Lin reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */ 12478eb80252STiffany Lin <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ 12488eb80252STiffany Lin interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>, 12498eb80252STiffany Lin <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; 12508eb80252STiffany Lin mediatek,larb = <&larb3>, 12518eb80252STiffany Lin <&larb5>; 12528eb80252STiffany Lin iommus = <&iommu M4U_PORT_VENC_RCPU>, 12538eb80252STiffany Lin <&iommu M4U_PORT_VENC_REC>, 12548eb80252STiffany Lin <&iommu M4U_PORT_VENC_BSDMA>, 12558eb80252STiffany Lin <&iommu M4U_PORT_VENC_SV_COMV>, 12568eb80252STiffany Lin <&iommu M4U_PORT_VENC_RD_COMV>, 12578eb80252STiffany Lin <&iommu M4U_PORT_VENC_CUR_LUMA>, 12588eb80252STiffany Lin <&iommu M4U_PORT_VENC_CUR_CHROMA>, 12598eb80252STiffany Lin <&iommu M4U_PORT_VENC_REF_LUMA>, 12608eb80252STiffany Lin <&iommu M4U_PORT_VENC_REF_CHROMA>, 12618eb80252STiffany Lin <&iommu M4U_PORT_VENC_NBM_RDMA>, 12628eb80252STiffany Lin <&iommu M4U_PORT_VENC_NBM_WDMA>, 12638eb80252STiffany Lin <&iommu M4U_PORT_VENC_RCPU_SET2>, 12648eb80252STiffany Lin <&iommu M4U_PORT_VENC_REC_FRM_SET2>, 12658eb80252STiffany Lin <&iommu M4U_PORT_VENC_BSDMA_SET2>, 12668eb80252STiffany Lin <&iommu M4U_PORT_VENC_SV_COMA_SET2>, 12678eb80252STiffany Lin <&iommu M4U_PORT_VENC_RD_COMA_SET2>, 12688eb80252STiffany Lin <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, 12698eb80252STiffany Lin <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, 12708eb80252STiffany Lin <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, 12718eb80252STiffany Lin <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; 12728eb80252STiffany Lin mediatek,vpu = <&vpu>; 12738eb80252STiffany Lin clocks = <&topckgen CLK_TOP_VENCPLL_D2>, 12748eb80252STiffany Lin <&topckgen CLK_TOP_VENC_SEL>, 12758eb80252STiffany Lin <&topckgen CLK_TOP_UNIVPLL1_D2>, 12768eb80252STiffany Lin <&topckgen CLK_TOP_VENC_LT_SEL>; 12778eb80252STiffany Lin clock-names = "venc_sel_src", 12788eb80252STiffany Lin "venc_sel", 12798eb80252STiffany Lin "venc_lt_sel_src", 12808eb80252STiffany Lin "venc_lt_sel"; 12818eb80252STiffany Lin }; 12828eb80252STiffany Lin 128367e56c56SJames Liao vencltsys: clock-controller@19000000 { 128467e56c56SJames Liao compatible = "mediatek,mt8173-vencltsys", "syscon"; 128567e56c56SJames Liao reg = <0 0x19000000 0 0x1000>; 128667e56c56SJames Liao #clock-cells = <1>; 128767e56c56SJames Liao }; 12885ff6b3a6SYong Wu 12895ff6b3a6SYong Wu larb5: larb@19001000 { 12905ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 12915ff6b3a6SYong Wu reg = <0 0x19001000 0 0x1000>; 12925ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 12935ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; 12945ff6b3a6SYong Wu clocks = <&vencltsys CLK_VENCLT_CKE1>, 12955ff6b3a6SYong Wu <&vencltsys CLK_VENCLT_CKE0>; 12965ff6b3a6SYong Wu clock-names = "apb", "smi"; 12975ff6b3a6SYong Wu }; 1298b3a37248SEddie Huang }; 1299b3a37248SEddie Huang}; 1300b3a37248SEddie Huang 1301