1b3a37248SEddie Huang/* 2b3a37248SEddie Huang * Copyright (c) 2014 MediaTek Inc. 3b3a37248SEddie Huang * Author: Eddie Huang <eddie.huang@mediatek.com> 4b3a37248SEddie Huang * 5b3a37248SEddie Huang * This program is free software; you can redistribute it and/or modify 6b3a37248SEddie Huang * it under the terms of the GNU General Public License version 2 as 7b3a37248SEddie Huang * published by the Free Software Foundation. 8b3a37248SEddie Huang * 9b3a37248SEddie Huang * This program is distributed in the hope that it will be useful, 10b3a37248SEddie Huang * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11b3a37248SEddie Huang * GNU General Public License for more details. 12b3a37248SEddie Huang */ 13b3a37248SEddie Huang 14f2ce7014SSascha Hauer#include <dt-bindings/clock/mt8173-clk.h> 15b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/irq.h> 16b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/arm-gic.h> 175ff6b3a6SYong Wu#include <dt-bindings/memory/mt8173-larb-port.h> 18bfcce47aSChunfeng Yun#include <dt-bindings/phy/phy.h> 19c02e0e86SKoro Chen#include <dt-bindings/power/mt8173-power.h> 20967313e2SPhilipp Zabel#include <dt-bindings/reset/mt8173-resets.h> 21c2e66b8fSHoulong Wei#include <dt-bindings/gce/mt8173-gce.h> 2226af2884SMichael Kao#include <dt-bindings/thermal/thermal.h> 23359f9365SHongzhou Yang#include "mt8173-pinfunc.h" 24b3a37248SEddie Huang 25b3a37248SEddie Huang/ { 26b3a37248SEddie Huang compatible = "mediatek,mt8173"; 27b3a37248SEddie Huang interrupt-parent = <&sysirq>; 28b3a37248SEddie Huang #address-cells = <2>; 29b3a37248SEddie Huang #size-cells = <2>; 30b3a37248SEddie Huang 3181ad4dbaSCK Hu aliases { 3281ad4dbaSCK Hu ovl0 = &ovl0; 3381ad4dbaSCK Hu ovl1 = &ovl1; 3481ad4dbaSCK Hu rdma0 = &rdma0; 3581ad4dbaSCK Hu rdma1 = &rdma1; 3681ad4dbaSCK Hu rdma2 = &rdma2; 3781ad4dbaSCK Hu wdma0 = &wdma0; 3881ad4dbaSCK Hu wdma1 = &wdma1; 3981ad4dbaSCK Hu color0 = &color0; 4081ad4dbaSCK Hu color1 = &color1; 4181ad4dbaSCK Hu split0 = &split0; 4281ad4dbaSCK Hu split1 = &split1; 4381ad4dbaSCK Hu dpi0 = &dpi0; 4481ad4dbaSCK Hu dsi0 = &dsi0; 4581ad4dbaSCK Hu dsi1 = &dsi1; 46fff12573SHsin-Yi Wang mdp-rdma0 = &mdp_rdma0; 47fff12573SHsin-Yi Wang mdp-rdma1 = &mdp_rdma1; 48fff12573SHsin-Yi Wang mdp-rsz0 = &mdp_rsz0; 49fff12573SHsin-Yi Wang mdp-rsz1 = &mdp_rsz1; 50fff12573SHsin-Yi Wang mdp-rsz2 = &mdp_rsz2; 51fff12573SHsin-Yi Wang mdp-wdma0 = &mdp_wdma0; 52fff12573SHsin-Yi Wang mdp-wrot0 = &mdp_wrot0; 53fff12573SHsin-Yi Wang mdp-wrot1 = &mdp_wrot1; 540f5da28eSHsin-Yi Wang serial0 = &uart0; 550f5da28eSHsin-Yi Wang serial1 = &uart1; 560f5da28eSHsin-Yi Wang serial2 = &uart2; 570f5da28eSHsin-Yi Wang serial3 = &uart3; 5881ad4dbaSCK Hu }; 5981ad4dbaSCK Hu 606f117db4SKrzysztof Kozlowski cluster0_opp: opp-table-0 { 61da85a3afSAndrew-sh Cheng compatible = "operating-points-v2"; 62da85a3afSAndrew-sh Cheng opp-shared; 63da85a3afSAndrew-sh Cheng opp-507000000 { 64da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <507000000>; 65da85a3afSAndrew-sh Cheng opp-microvolt = <859000>; 66da85a3afSAndrew-sh Cheng }; 67da85a3afSAndrew-sh Cheng opp-702000000 { 68da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <702000000>; 69da85a3afSAndrew-sh Cheng opp-microvolt = <908000>; 70da85a3afSAndrew-sh Cheng }; 71da85a3afSAndrew-sh Cheng opp-1001000000 { 72da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1001000000>; 73da85a3afSAndrew-sh Cheng opp-microvolt = <983000>; 74da85a3afSAndrew-sh Cheng }; 75da85a3afSAndrew-sh Cheng opp-1105000000 { 76da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1105000000>; 77da85a3afSAndrew-sh Cheng opp-microvolt = <1009000>; 78da85a3afSAndrew-sh Cheng }; 79da85a3afSAndrew-sh Cheng opp-1209000000 { 80da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1209000000>; 81da85a3afSAndrew-sh Cheng opp-microvolt = <1034000>; 82da85a3afSAndrew-sh Cheng }; 83da85a3afSAndrew-sh Cheng opp-1300000000 { 84da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1300000000>; 85da85a3afSAndrew-sh Cheng opp-microvolt = <1057000>; 86da85a3afSAndrew-sh Cheng }; 87da85a3afSAndrew-sh Cheng opp-1508000000 { 88da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1508000000>; 89da85a3afSAndrew-sh Cheng opp-microvolt = <1109000>; 90da85a3afSAndrew-sh Cheng }; 91da85a3afSAndrew-sh Cheng opp-1703000000 { 92da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1703000000>; 93da85a3afSAndrew-sh Cheng opp-microvolt = <1125000>; 94da85a3afSAndrew-sh Cheng }; 95da85a3afSAndrew-sh Cheng }; 96da85a3afSAndrew-sh Cheng 976f117db4SKrzysztof Kozlowski cluster1_opp: opp-table-1 { 98da85a3afSAndrew-sh Cheng compatible = "operating-points-v2"; 99da85a3afSAndrew-sh Cheng opp-shared; 100da85a3afSAndrew-sh Cheng opp-507000000 { 101da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <507000000>; 102da85a3afSAndrew-sh Cheng opp-microvolt = <828000>; 103da85a3afSAndrew-sh Cheng }; 104da85a3afSAndrew-sh Cheng opp-702000000 { 105da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <702000000>; 106da85a3afSAndrew-sh Cheng opp-microvolt = <867000>; 107da85a3afSAndrew-sh Cheng }; 108da85a3afSAndrew-sh Cheng opp-1001000000 { 109da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1001000000>; 110da85a3afSAndrew-sh Cheng opp-microvolt = <927000>; 111da85a3afSAndrew-sh Cheng }; 112da85a3afSAndrew-sh Cheng opp-1209000000 { 113da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1209000000>; 114da85a3afSAndrew-sh Cheng opp-microvolt = <968000>; 115da85a3afSAndrew-sh Cheng }; 116da85a3afSAndrew-sh Cheng opp-1404000000 { 117da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1404000000>; 118da85a3afSAndrew-sh Cheng opp-microvolt = <1007000>; 119da85a3afSAndrew-sh Cheng }; 120da85a3afSAndrew-sh Cheng opp-1612000000 { 121da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1612000000>; 122da85a3afSAndrew-sh Cheng opp-microvolt = <1049000>; 123da85a3afSAndrew-sh Cheng }; 124da85a3afSAndrew-sh Cheng opp-1807000000 { 125da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1807000000>; 126da85a3afSAndrew-sh Cheng opp-microvolt = <1089000>; 127da85a3afSAndrew-sh Cheng }; 128da85a3afSAndrew-sh Cheng opp-2106000000 { 129da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <2106000000>; 130da85a3afSAndrew-sh Cheng opp-microvolt = <1125000>; 131da85a3afSAndrew-sh Cheng }; 132da85a3afSAndrew-sh Cheng }; 133da85a3afSAndrew-sh Cheng 134b3a37248SEddie Huang cpus { 135b3a37248SEddie Huang #address-cells = <1>; 136b3a37248SEddie Huang #size-cells = <0>; 137b3a37248SEddie Huang 138b3a37248SEddie Huang cpu-map { 139b3a37248SEddie Huang cluster0 { 140b3a37248SEddie Huang core0 { 141b3a37248SEddie Huang cpu = <&cpu0>; 142b3a37248SEddie Huang }; 143b3a37248SEddie Huang core1 { 144b3a37248SEddie Huang cpu = <&cpu1>; 145b3a37248SEddie Huang }; 146b3a37248SEddie Huang }; 147b3a37248SEddie Huang 148b3a37248SEddie Huang cluster1 { 149b3a37248SEddie Huang core0 { 150b3a37248SEddie Huang cpu = <&cpu2>; 151b3a37248SEddie Huang }; 152b3a37248SEddie Huang core1 { 153b3a37248SEddie Huang cpu = <&cpu3>; 154b3a37248SEddie Huang }; 155b3a37248SEddie Huang }; 156b3a37248SEddie Huang }; 157b3a37248SEddie Huang 158b3a37248SEddie Huang cpu0: cpu@0 { 159b3a37248SEddie Huang device_type = "cpu"; 160b3a37248SEddie Huang compatible = "arm,cortex-a53"; 161b3a37248SEddie Huang reg = <0x000>; 162ad4df7a5SHoward Chen enable-method = "psci"; 163ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 164acbf76eeSArnd Bergmann #cooling-cells = <2>; 16519f62c76Smichael.kao dynamic-power-coefficient = <263>; 166da85a3afSAndrew-sh Cheng clocks = <&infracfg CLK_INFRA_CA53SEL>, 167da85a3afSAndrew-sh Cheng <&apmixedsys CLK_APMIXED_MAINPLL>; 168da85a3afSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 169da85a3afSAndrew-sh Cheng operating-points-v2 = <&cluster0_opp>; 17079c528e9SHsin-Yi Wang capacity-dmips-mhz = <740>; 171b3a37248SEddie Huang }; 172b3a37248SEddie Huang 173b3a37248SEddie Huang cpu1: cpu@1 { 174b3a37248SEddie Huang device_type = "cpu"; 175b3a37248SEddie Huang compatible = "arm,cortex-a53"; 176b3a37248SEddie Huang reg = <0x001>; 177b3a37248SEddie Huang enable-method = "psci"; 178ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 179a06e5c05SViresh Kumar #cooling-cells = <2>; 18019f62c76Smichael.kao dynamic-power-coefficient = <263>; 181da85a3afSAndrew-sh Cheng clocks = <&infracfg CLK_INFRA_CA53SEL>, 182da85a3afSAndrew-sh Cheng <&apmixedsys CLK_APMIXED_MAINPLL>; 183da85a3afSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 184da85a3afSAndrew-sh Cheng operating-points-v2 = <&cluster0_opp>; 18579c528e9SHsin-Yi Wang capacity-dmips-mhz = <740>; 186b3a37248SEddie Huang }; 187b3a37248SEddie Huang 188b3a37248SEddie Huang cpu2: cpu@100 { 189b3a37248SEddie Huang device_type = "cpu"; 1905c6e116dSSeiya Wang compatible = "arm,cortex-a72"; 191b3a37248SEddie Huang reg = <0x100>; 192b3a37248SEddie Huang enable-method = "psci"; 193ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 194acbf76eeSArnd Bergmann #cooling-cells = <2>; 19519f62c76Smichael.kao dynamic-power-coefficient = <530>; 1965c6e116dSSeiya Wang clocks = <&infracfg CLK_INFRA_CA72SEL>, 197da85a3afSAndrew-sh Cheng <&apmixedsys CLK_APMIXED_MAINPLL>; 198da85a3afSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 199da85a3afSAndrew-sh Cheng operating-points-v2 = <&cluster1_opp>; 200f0e5405bSUlrich Hecht capacity-dmips-mhz = <1024>; 201b3a37248SEddie Huang }; 202b3a37248SEddie Huang 203b3a37248SEddie Huang cpu3: cpu@101 { 204b3a37248SEddie Huang device_type = "cpu"; 2055c6e116dSSeiya Wang compatible = "arm,cortex-a72"; 206b3a37248SEddie Huang reg = <0x101>; 207b3a37248SEddie Huang enable-method = "psci"; 208ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 209a06e5c05SViresh Kumar #cooling-cells = <2>; 21019f62c76Smichael.kao dynamic-power-coefficient = <530>; 2115c6e116dSSeiya Wang clocks = <&infracfg CLK_INFRA_CA72SEL>, 212da85a3afSAndrew-sh Cheng <&apmixedsys CLK_APMIXED_MAINPLL>; 213da85a3afSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 214da85a3afSAndrew-sh Cheng operating-points-v2 = <&cluster1_opp>; 215f0e5405bSUlrich Hecht capacity-dmips-mhz = <1024>; 216ad4df7a5SHoward Chen }; 217ad4df7a5SHoward Chen 218ad4df7a5SHoward Chen idle-states { 219a13f18f5SLorenzo Pieralisi entry-method = "psci"; 220ad4df7a5SHoward Chen 221ad4df7a5SHoward Chen CPU_SLEEP_0: cpu-sleep-0 { 222ad4df7a5SHoward Chen compatible = "arm,idle-state"; 223ad4df7a5SHoward Chen local-timer-stop; 224ad4df7a5SHoward Chen entry-latency-us = <639>; 225ad4df7a5SHoward Chen exit-latency-us = <680>; 226ad4df7a5SHoward Chen min-residency-us = <1088>; 227ad4df7a5SHoward Chen arm,psci-suspend-param = <0x0010000>; 228ad4df7a5SHoward Chen }; 229b3a37248SEddie Huang }; 230b3a37248SEddie Huang }; 231b3a37248SEddie Huang 232a4599f6eSSeiya Wang pmu_a53 { 233a4599f6eSSeiya Wang compatible = "arm,cortex-a53-pmu"; 234a4599f6eSSeiya Wang interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, 235a4599f6eSSeiya Wang <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>; 236a4599f6eSSeiya Wang interrupt-affinity = <&cpu0>, <&cpu1>; 237a4599f6eSSeiya Wang }; 238a4599f6eSSeiya Wang 239a4599f6eSSeiya Wang pmu_a72 { 240a4599f6eSSeiya Wang compatible = "arm,cortex-a72-pmu"; 241a4599f6eSSeiya Wang interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>, 242a4599f6eSSeiya Wang <GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>; 243a4599f6eSSeiya Wang interrupt-affinity = <&cpu2>, <&cpu3>; 244a4599f6eSSeiya Wang }; 245a4599f6eSSeiya Wang 246b3a37248SEddie Huang psci { 24705bdabe7SFan Chen compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 248b3a37248SEddie Huang method = "smc"; 249b3a37248SEddie Huang cpu_suspend = <0x84000001>; 250b3a37248SEddie Huang cpu_off = <0x84000002>; 251b3a37248SEddie Huang cpu_on = <0x84000003>; 252b3a37248SEddie Huang }; 253b3a37248SEddie Huang 25472b29215SHsin-Yi Wang clk26m: oscillator0 { 255f2ce7014SSascha Hauer compatible = "fixed-clock"; 256f2ce7014SSascha Hauer #clock-cells = <0>; 257f2ce7014SSascha Hauer clock-frequency = <26000000>; 258f2ce7014SSascha Hauer clock-output-names = "clk26m"; 259f2ce7014SSascha Hauer }; 260f2ce7014SSascha Hauer 26172b29215SHsin-Yi Wang clk32k: oscillator1 { 262f2ce7014SSascha Hauer compatible = "fixed-clock"; 263f2ce7014SSascha Hauer #clock-cells = <0>; 264f2ce7014SSascha Hauer clock-frequency = <32000>; 265f2ce7014SSascha Hauer clock-output-names = "clk32k"; 266f2ce7014SSascha Hauer }; 267f2ce7014SSascha Hauer 26872b29215SHsin-Yi Wang cpum_ck: oscillator2 { 26967e56c56SJames Liao compatible = "fixed-clock"; 27067e56c56SJames Liao #clock-cells = <0>; 27167e56c56SJames Liao clock-frequency = <0>; 27267e56c56SJames Liao clock-output-names = "cpum_ck"; 27367e56c56SJames Liao }; 27467e56c56SJames Liao 275962f5143Sdawei.chien@mediatek.com thermal-zones { 276624f1806SKrzysztof Kozlowski cpu_thermal: cpu-thermal { 277962f5143Sdawei.chien@mediatek.com polling-delay-passive = <1000>; /* milliseconds */ 278962f5143Sdawei.chien@mediatek.com polling-delay = <1000>; /* milliseconds */ 279962f5143Sdawei.chien@mediatek.com 280962f5143Sdawei.chien@mediatek.com thermal-sensors = <&thermal>; 281962f5143Sdawei.chien@mediatek.com sustainable-power = <1500>; /* milliwatts */ 282962f5143Sdawei.chien@mediatek.com 283962f5143Sdawei.chien@mediatek.com trips { 28472b29215SHsin-Yi Wang threshold: trip-point0 { 285962f5143Sdawei.chien@mediatek.com temperature = <68000>; 286962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 287962f5143Sdawei.chien@mediatek.com type = "passive"; 288962f5143Sdawei.chien@mediatek.com }; 289962f5143Sdawei.chien@mediatek.com 29072b29215SHsin-Yi Wang target: trip-point1 { 291962f5143Sdawei.chien@mediatek.com temperature = <85000>; 292962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 293962f5143Sdawei.chien@mediatek.com type = "passive"; 294962f5143Sdawei.chien@mediatek.com }; 295962f5143Sdawei.chien@mediatek.com 29672b29215SHsin-Yi Wang cpu_crit: cpu_crit0 { 297962f5143Sdawei.chien@mediatek.com temperature = <115000>; 298962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 299962f5143Sdawei.chien@mediatek.com type = "critical"; 300962f5143Sdawei.chien@mediatek.com }; 301962f5143Sdawei.chien@mediatek.com }; 302962f5143Sdawei.chien@mediatek.com 303962f5143Sdawei.chien@mediatek.com cooling-maps { 30472b29215SHsin-Yi Wang map0 { 305962f5143Sdawei.chien@mediatek.com trip = <&target>; 30626af2884SMichael Kao cooling-device = <&cpu0 THERMAL_NO_LIMIT 30726af2884SMichael Kao THERMAL_NO_LIMIT>, 30826af2884SMichael Kao <&cpu1 THERMAL_NO_LIMIT 30926af2884SMichael Kao THERMAL_NO_LIMIT>; 3107fcef92dSDaniel Kurtz contribution = <3072>; 311962f5143Sdawei.chien@mediatek.com }; 31272b29215SHsin-Yi Wang map1 { 313962f5143Sdawei.chien@mediatek.com trip = <&target>; 31426af2884SMichael Kao cooling-device = <&cpu2 THERMAL_NO_LIMIT 31526af2884SMichael Kao THERMAL_NO_LIMIT>, 31626af2884SMichael Kao <&cpu3 THERMAL_NO_LIMIT 31726af2884SMichael Kao THERMAL_NO_LIMIT>; 3187fcef92dSDaniel Kurtz contribution = <1024>; 319962f5143Sdawei.chien@mediatek.com }; 320962f5143Sdawei.chien@mediatek.com }; 321962f5143Sdawei.chien@mediatek.com }; 322962f5143Sdawei.chien@mediatek.com }; 323962f5143Sdawei.chien@mediatek.com 324404b2819SAndrew-CT Chen reserved-memory { 325404b2819SAndrew-CT Chen #address-cells = <2>; 326404b2819SAndrew-CT Chen #size-cells = <2>; 327404b2819SAndrew-CT Chen ranges; 32872b29215SHsin-Yi Wang vpu_dma_reserved: vpu_dma_mem_region@b7000000 { 329404b2819SAndrew-CT Chen compatible = "shared-dma-pool"; 330404b2819SAndrew-CT Chen reg = <0 0xb7000000 0 0x500000>; 331404b2819SAndrew-CT Chen alignment = <0x1000>; 332404b2819SAndrew-CT Chen no-map; 333404b2819SAndrew-CT Chen }; 334404b2819SAndrew-CT Chen }; 335404b2819SAndrew-CT Chen 336b3a37248SEddie Huang timer { 337b3a37248SEddie Huang compatible = "arm,armv8-timer"; 338b3a37248SEddie Huang interrupt-parent = <&gic>; 339b3a37248SEddie Huang interrupts = <GIC_PPI 13 340b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 341b3a37248SEddie Huang <GIC_PPI 14 342b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 343b3a37248SEddie Huang <GIC_PPI 11 344b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 345b3a37248SEddie Huang <GIC_PPI 10 346b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 347b5686273SHsin-Yi Wang arm,no-tick-in-suspend; 348b3a37248SEddie Huang }; 349b3a37248SEddie Huang 350b3a37248SEddie Huang soc { 351b3a37248SEddie Huang #address-cells = <2>; 352b3a37248SEddie Huang #size-cells = <2>; 353b3a37248SEddie Huang compatible = "simple-bus"; 354b3a37248SEddie Huang ranges; 355b3a37248SEddie Huang 356f2ce7014SSascha Hauer topckgen: clock-controller@10000000 { 357f2ce7014SSascha Hauer compatible = "mediatek,mt8173-topckgen"; 358f2ce7014SSascha Hauer reg = <0 0x10000000 0 0x1000>; 359f2ce7014SSascha Hauer #clock-cells = <1>; 360f2ce7014SSascha Hauer }; 361f2ce7014SSascha Hauer 362f2ce7014SSascha Hauer infracfg: power-controller@10001000 { 363f2ce7014SSascha Hauer compatible = "mediatek,mt8173-infracfg", "syscon"; 364f2ce7014SSascha Hauer reg = <0 0x10001000 0 0x1000>; 365f2ce7014SSascha Hauer #clock-cells = <1>; 366f2ce7014SSascha Hauer #reset-cells = <1>; 367f2ce7014SSascha Hauer }; 368f2ce7014SSascha Hauer 369f2ce7014SSascha Hauer pericfg: power-controller@10003000 { 370f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pericfg", "syscon"; 371f2ce7014SSascha Hauer reg = <0 0x10003000 0 0x1000>; 372f2ce7014SSascha Hauer #clock-cells = <1>; 373f2ce7014SSascha Hauer #reset-cells = <1>; 374f2ce7014SSascha Hauer }; 375f2ce7014SSascha Hauer 376f2ce7014SSascha Hauer syscfg_pctl_a: syscfg_pctl_a@10005000 { 377f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 378f2ce7014SSascha Hauer reg = <0 0x10005000 0 0x1000>; 379f2ce7014SSascha Hauer }; 380f2ce7014SSascha Hauer 38172b29215SHsin-Yi Wang pio: pinctrl@1000b000 { 382359f9365SHongzhou Yang compatible = "mediatek,mt8173-pinctrl"; 3836769b93cSYingjoe Chen reg = <0 0x1000b000 0 0x1000>; 384359f9365SHongzhou Yang mediatek,pctl-regmap = <&syscfg_pctl_a>; 385359f9365SHongzhou Yang pins-are-numbered; 386359f9365SHongzhou Yang gpio-controller; 387359f9365SHongzhou Yang #gpio-cells = <2>; 388359f9365SHongzhou Yang interrupt-controller; 389359f9365SHongzhou Yang #interrupt-cells = <2>; 390359f9365SHongzhou Yang interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 391359f9365SHongzhou Yang <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 392359f9365SHongzhou Yang <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 393091cf598SEddie Huang 394a10b57f4SCK Hu hdmi_pin: xxx { 395a10b57f4SCK Hu 396a10b57f4SCK Hu /*hdmi htplg pin*/ 397a10b57f4SCK Hu pins1 { 398a10b57f4SCK Hu pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>; 399a10b57f4SCK Hu input-enable; 400a10b57f4SCK Hu bias-pull-down; 401a10b57f4SCK Hu }; 402a10b57f4SCK Hu }; 403a10b57f4SCK Hu 404091cf598SEddie Huang i2c0_pins_a: i2c0 { 405091cf598SEddie Huang pins1 { 406091cf598SEddie Huang pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 407091cf598SEddie Huang <MT8173_PIN_46_SCL0__FUNC_SCL0>; 408091cf598SEddie Huang bias-disable; 409091cf598SEddie Huang }; 410359f9365SHongzhou Yang }; 411359f9365SHongzhou Yang 412091cf598SEddie Huang i2c1_pins_a: i2c1 { 413091cf598SEddie Huang pins1 { 414091cf598SEddie Huang pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 415091cf598SEddie Huang <MT8173_PIN_126_SCL1__FUNC_SCL1>; 416091cf598SEddie Huang bias-disable; 417091cf598SEddie Huang }; 418091cf598SEddie Huang }; 419091cf598SEddie Huang 420091cf598SEddie Huang i2c2_pins_a: i2c2 { 421091cf598SEddie Huang pins1 { 422091cf598SEddie Huang pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 423091cf598SEddie Huang <MT8173_PIN_44_SCL2__FUNC_SCL2>; 424091cf598SEddie Huang bias-disable; 425091cf598SEddie Huang }; 426091cf598SEddie Huang }; 427091cf598SEddie Huang 428091cf598SEddie Huang i2c3_pins_a: i2c3 { 429091cf598SEddie Huang pins1 { 430091cf598SEddie Huang pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 431091cf598SEddie Huang <MT8173_PIN_107_SCL3__FUNC_SCL3>; 432091cf598SEddie Huang bias-disable; 433091cf598SEddie Huang }; 434091cf598SEddie Huang }; 435091cf598SEddie Huang 436091cf598SEddie Huang i2c4_pins_a: i2c4 { 437091cf598SEddie Huang pins1 { 438091cf598SEddie Huang pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 439091cf598SEddie Huang <MT8173_PIN_134_SCL4__FUNC_SCL4>; 440091cf598SEddie Huang bias-disable; 441091cf598SEddie Huang }; 442091cf598SEddie Huang }; 443091cf598SEddie Huang 444091cf598SEddie Huang i2c6_pins_a: i2c6 { 445091cf598SEddie Huang pins1 { 446091cf598SEddie Huang pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 447091cf598SEddie Huang <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 448091cf598SEddie Huang bias-disable; 449091cf598SEddie Huang }; 450091cf598SEddie Huang }; 4516769b93cSYingjoe Chen }; 4526769b93cSYingjoe Chen 4538b656264SEnric Balletbo i Serra scpsys: syscon@10006000 { 4548b656264SEnric Balletbo i Serra compatible = "syscon", "simple-mfd"; 455c010ff53SSascha Hauer reg = <0 0x10006000 0 0x1000>; 4568b656264SEnric Balletbo i Serra #power-domain-cells = <1>; 4578b656264SEnric Balletbo i Serra 4588b656264SEnric Balletbo i Serra /* System Power Manager */ 4598b656264SEnric Balletbo i Serra spm: power-controller { 4608b656264SEnric Balletbo i Serra compatible = "mediatek,mt8173-power-controller"; 4618b656264SEnric Balletbo i Serra #address-cells = <1>; 4628b656264SEnric Balletbo i Serra #size-cells = <0>; 4638b656264SEnric Balletbo i Serra #power-domain-cells = <1>; 4648b656264SEnric Balletbo i Serra 4658b656264SEnric Balletbo i Serra /* power domains of the SoC */ 4668b656264SEnric Balletbo i Serra power-domain@MT8173_POWER_DOMAIN_VDEC { 4678b656264SEnric Balletbo i Serra reg = <MT8173_POWER_DOMAIN_VDEC>; 4688b656264SEnric Balletbo i Serra clocks = <&topckgen CLK_TOP_MM_SEL>; 4698b656264SEnric Balletbo i Serra clock-names = "mm"; 4708b656264SEnric Balletbo i Serra #power-domain-cells = <0>; 4718b656264SEnric Balletbo i Serra }; 4728b656264SEnric Balletbo i Serra power-domain@MT8173_POWER_DOMAIN_VENC { 4738b656264SEnric Balletbo i Serra reg = <MT8173_POWER_DOMAIN_VENC>; 4748b656264SEnric Balletbo i Serra clocks = <&topckgen CLK_TOP_MM_SEL>, 4758b656264SEnric Balletbo i Serra <&topckgen CLK_TOP_VENC_SEL>; 4768b656264SEnric Balletbo i Serra clock-names = "mm", "venc"; 4778b656264SEnric Balletbo i Serra #power-domain-cells = <0>; 4788b656264SEnric Balletbo i Serra }; 4798b656264SEnric Balletbo i Serra power-domain@MT8173_POWER_DOMAIN_ISP { 4808b656264SEnric Balletbo i Serra reg = <MT8173_POWER_DOMAIN_ISP>; 4818b656264SEnric Balletbo i Serra clocks = <&topckgen CLK_TOP_MM_SEL>; 4828b656264SEnric Balletbo i Serra clock-names = "mm"; 4838b656264SEnric Balletbo i Serra #power-domain-cells = <0>; 4848b656264SEnric Balletbo i Serra }; 4858b656264SEnric Balletbo i Serra power-domain@MT8173_POWER_DOMAIN_MM { 4868b656264SEnric Balletbo i Serra reg = <MT8173_POWER_DOMAIN_MM>; 4878b656264SEnric Balletbo i Serra clocks = <&topckgen CLK_TOP_MM_SEL>; 4888b656264SEnric Balletbo i Serra clock-names = "mm"; 4898b656264SEnric Balletbo i Serra #power-domain-cells = <0>; 4908b656264SEnric Balletbo i Serra mediatek,infracfg = <&infracfg>; 4918b656264SEnric Balletbo i Serra }; 4928b656264SEnric Balletbo i Serra power-domain@MT8173_POWER_DOMAIN_VENC_LT { 4938b656264SEnric Balletbo i Serra reg = <MT8173_POWER_DOMAIN_VENC_LT>; 4948b656264SEnric Balletbo i Serra clocks = <&topckgen CLK_TOP_MM_SEL>, 495e34573c9SJames Liao <&topckgen CLK_TOP_VENC_LT_SEL>; 4968b656264SEnric Balletbo i Serra clock-names = "mm", "venclt"; 4978b656264SEnric Balletbo i Serra #power-domain-cells = <0>; 4988b656264SEnric Balletbo i Serra }; 4998b656264SEnric Balletbo i Serra power-domain@MT8173_POWER_DOMAIN_AUDIO { 5008b656264SEnric Balletbo i Serra reg = <MT8173_POWER_DOMAIN_AUDIO>; 5018b656264SEnric Balletbo i Serra #power-domain-cells = <0>; 5028b656264SEnric Balletbo i Serra }; 5038b656264SEnric Balletbo i Serra power-domain@MT8173_POWER_DOMAIN_USB { 5048b656264SEnric Balletbo i Serra reg = <MT8173_POWER_DOMAIN_USB>; 5058b656264SEnric Balletbo i Serra #power-domain-cells = <0>; 5068b656264SEnric Balletbo i Serra }; 507109fd206SBilal Wasim mfg_async: power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC { 5088b656264SEnric Balletbo i Serra reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>; 5098b656264SEnric Balletbo i Serra clocks = <&clk26m>; 5108b656264SEnric Balletbo i Serra clock-names = "mfg"; 5118b656264SEnric Balletbo i Serra #address-cells = <1>; 5128b656264SEnric Balletbo i Serra #size-cells = <0>; 5138b656264SEnric Balletbo i Serra #power-domain-cells = <1>; 5148b656264SEnric Balletbo i Serra 5158b656264SEnric Balletbo i Serra power-domain@MT8173_POWER_DOMAIN_MFG_2D { 5168b656264SEnric Balletbo i Serra reg = <MT8173_POWER_DOMAIN_MFG_2D>; 5178b656264SEnric Balletbo i Serra #address-cells = <1>; 5188b656264SEnric Balletbo i Serra #size-cells = <0>; 5198b656264SEnric Balletbo i Serra #power-domain-cells = <1>; 5208b656264SEnric Balletbo i Serra 5218b656264SEnric Balletbo i Serra power-domain@MT8173_POWER_DOMAIN_MFG { 5228b656264SEnric Balletbo i Serra reg = <MT8173_POWER_DOMAIN_MFG>; 5238b656264SEnric Balletbo i Serra #power-domain-cells = <0>; 5248b656264SEnric Balletbo i Serra mediatek,infracfg = <&infracfg>; 5258b656264SEnric Balletbo i Serra }; 5268b656264SEnric Balletbo i Serra }; 5278b656264SEnric Balletbo i Serra }; 5288b656264SEnric Balletbo i Serra }; 529c010ff53SSascha Hauer }; 530c010ff53SSascha Hauer 53113421b3eSEddie Huang watchdog: watchdog@10007000 { 53213421b3eSEddie Huang compatible = "mediatek,mt8173-wdt", 53313421b3eSEddie Huang "mediatek,mt6589-wdt"; 53413421b3eSEddie Huang reg = <0 0x10007000 0 0x100>; 53513421b3eSEddie Huang }; 53613421b3eSEddie Huang 537b2c76e27SDaniel Kurtz timer: timer@10008000 { 538b2c76e27SDaniel Kurtz compatible = "mediatek,mt8173-timer", 539b2c76e27SDaniel Kurtz "mediatek,mt6577-timer"; 540b2c76e27SDaniel Kurtz reg = <0 0x10008000 0 0x1000>; 541b2c76e27SDaniel Kurtz interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 542b2c76e27SDaniel Kurtz clocks = <&infracfg CLK_INFRA_CLK_13M>, 543b2c76e27SDaniel Kurtz <&topckgen CLK_TOP_RTC_SEL>; 544b2c76e27SDaniel Kurtz }; 545b2c76e27SDaniel Kurtz 5466cf15fc2SSascha Hauer pwrap: pwrap@1000d000 { 5476cf15fc2SSascha Hauer compatible = "mediatek,mt8173-pwrap"; 5486cf15fc2SSascha Hauer reg = <0 0x1000d000 0 0x1000>; 5496cf15fc2SSascha Hauer reg-names = "pwrap"; 5506cf15fc2SSascha Hauer interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 5516cf15fc2SSascha Hauer resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 5526cf15fc2SSascha Hauer reset-names = "pwrap"; 5536cf15fc2SSascha Hauer clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 5546cf15fc2SSascha Hauer clock-names = "spi", "wrap"; 5556cf15fc2SSascha Hauer }; 5566cf15fc2SSascha Hauer 557a10b57f4SCK Hu cec: cec@10013000 { 558a10b57f4SCK Hu compatible = "mediatek,mt8173-cec"; 559a10b57f4SCK Hu reg = <0 0x10013000 0 0xbc>; 560a10b57f4SCK Hu interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; 561a10b57f4SCK Hu clocks = <&infracfg CLK_INFRA_CEC>; 562a10b57f4SCK Hu status = "disabled"; 563a10b57f4SCK Hu }; 564a10b57f4SCK Hu 565404b2819SAndrew-CT Chen vpu: vpu@10020000 { 566404b2819SAndrew-CT Chen compatible = "mediatek,mt8173-vpu"; 567404b2819SAndrew-CT Chen reg = <0 0x10020000 0 0x30000>, 568404b2819SAndrew-CT Chen <0 0x10050000 0 0x100>; 569404b2819SAndrew-CT Chen reg-names = "tcm", "cfg_reg"; 570404b2819SAndrew-CT Chen interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 571404b2819SAndrew-CT Chen clocks = <&topckgen CLK_TOP_SCP_SEL>; 572404b2819SAndrew-CT Chen clock-names = "main"; 573404b2819SAndrew-CT Chen memory-region = <&vpu_dma_reserved>; 574404b2819SAndrew-CT Chen }; 575404b2819SAndrew-CT Chen 576b3a37248SEddie Huang sysirq: intpol-controller@10200620 { 577b3a37248SEddie Huang compatible = "mediatek,mt8173-sysirq", 578b3a37248SEddie Huang "mediatek,mt6577-sysirq"; 579b3a37248SEddie Huang interrupt-controller; 580b3a37248SEddie Huang #interrupt-cells = <3>; 581b3a37248SEddie Huang interrupt-parent = <&gic>; 582b3a37248SEddie Huang reg = <0 0x10200620 0 0x20>; 583b3a37248SEddie Huang }; 584b3a37248SEddie Huang 5855ff6b3a6SYong Wu iommu: iommu@10205000 { 5865ff6b3a6SYong Wu compatible = "mediatek,mt8173-m4u"; 5875ff6b3a6SYong Wu reg = <0 0x10205000 0 0x1000>; 5885ff6b3a6SYong Wu interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 5895ff6b3a6SYong Wu clocks = <&infracfg CLK_INFRA_M4U>; 5905ff6b3a6SYong Wu clock-names = "bclk"; 59133c7874bSNícolas F. R. A. Prado mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, 59233c7874bSNícolas F. R. A. Prado <&larb3>, <&larb4>, <&larb5>; 5935ff6b3a6SYong Wu #iommu-cells = <1>; 5945ff6b3a6SYong Wu }; 5955ff6b3a6SYong Wu 59693e9f5eeSandrew-ct.chen@mediatek.com efuse: efuse@10206000 { 59793e9f5eeSandrew-ct.chen@mediatek.com compatible = "mediatek,mt8173-efuse"; 59893e9f5eeSandrew-ct.chen@mediatek.com reg = <0 0x10206000 0 0x1000>; 5996de18454Sdawei.chien@mediatek.com #address-cells = <1>; 6006de18454Sdawei.chien@mediatek.com #size-cells = <1>; 6016de18454Sdawei.chien@mediatek.com thermal_calibration: calib@528 { 6026de18454Sdawei.chien@mediatek.com reg = <0x528 0xc>; 6036de18454Sdawei.chien@mediatek.com }; 60493e9f5eeSandrew-ct.chen@mediatek.com }; 60593e9f5eeSandrew-ct.chen@mediatek.com 606f2ce7014SSascha Hauer apmixedsys: clock-controller@10209000 { 607f2ce7014SSascha Hauer compatible = "mediatek,mt8173-apmixedsys"; 608f2ce7014SSascha Hauer reg = <0 0x10209000 0 0x1000>; 609f2ce7014SSascha Hauer #clock-cells = <1>; 610f2ce7014SSascha Hauer }; 611f2ce7014SSascha Hauer 612a10b57f4SCK Hu hdmi_phy: hdmi-phy@10209100 { 613a10b57f4SCK Hu compatible = "mediatek,mt8173-hdmi-phy"; 614a10b57f4SCK Hu reg = <0 0x10209100 0 0x24>; 615a10b57f4SCK Hu clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; 616a10b57f4SCK Hu clock-names = "pll_ref"; 617a10b57f4SCK Hu clock-output-names = "hdmitx_dig_cts"; 618a10b57f4SCK Hu mediatek,ibias = <0xa>; 619a10b57f4SCK Hu mediatek,ibias_up = <0x1c>; 620a10b57f4SCK Hu #clock-cells = <0>; 621a10b57f4SCK Hu #phy-cells = <0>; 622a10b57f4SCK Hu status = "disabled"; 623a10b57f4SCK Hu }; 624a10b57f4SCK Hu 625c2e66b8fSHoulong Wei gce: mailbox@10212000 { 626c2e66b8fSHoulong Wei compatible = "mediatek,mt8173-gce"; 627c2e66b8fSHoulong Wei reg = <0 0x10212000 0 0x1000>; 628c2e66b8fSHoulong Wei interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 629c2e66b8fSHoulong Wei clocks = <&infracfg CLK_INFRA_GCE>; 630c2e66b8fSHoulong Wei clock-names = "gce"; 631eb4a01afSHsin-Yi Wang #mbox-cells = <2>; 632c2e66b8fSHoulong Wei }; 633c2e66b8fSHoulong Wei 634c61872d5SChunfeng Yun mipi_tx0: dsi-phy@10215000 { 63581ad4dbaSCK Hu compatible = "mediatek,mt8173-mipi-tx"; 63681ad4dbaSCK Hu reg = <0 0x10215000 0 0x1000>; 63781ad4dbaSCK Hu clocks = <&clk26m>; 63881ad4dbaSCK Hu clock-output-names = "mipi_tx0_pll"; 63981ad4dbaSCK Hu #clock-cells = <0>; 64081ad4dbaSCK Hu #phy-cells = <0>; 64181ad4dbaSCK Hu status = "disabled"; 64281ad4dbaSCK Hu }; 64381ad4dbaSCK Hu 644c61872d5SChunfeng Yun mipi_tx1: dsi-phy@10216000 { 64581ad4dbaSCK Hu compatible = "mediatek,mt8173-mipi-tx"; 64681ad4dbaSCK Hu reg = <0 0x10216000 0 0x1000>; 64781ad4dbaSCK Hu clocks = <&clk26m>; 64881ad4dbaSCK Hu clock-output-names = "mipi_tx1_pll"; 64981ad4dbaSCK Hu #clock-cells = <0>; 65081ad4dbaSCK Hu #phy-cells = <0>; 65181ad4dbaSCK Hu status = "disabled"; 65281ad4dbaSCK Hu }; 65381ad4dbaSCK Hu 65472b29215SHsin-Yi Wang gic: interrupt-controller@10221000 { 655b3a37248SEddie Huang compatible = "arm,gic-400"; 656b3a37248SEddie Huang #interrupt-cells = <3>; 657b3a37248SEddie Huang interrupt-parent = <&gic>; 658b3a37248SEddie Huang interrupt-controller; 659b3a37248SEddie Huang reg = <0 0x10221000 0 0x1000>, 660b3a37248SEddie Huang <0 0x10222000 0 0x2000>, 661b3a37248SEddie Huang <0 0x10224000 0 0x2000>, 662b3a37248SEddie Huang <0 0x10226000 0 0x2000>; 663b3a37248SEddie Huang interrupts = <GIC_PPI 9 664b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 665b3a37248SEddie Huang }; 666b3a37248SEddie Huang 667748c7d4dSSascha Hauer auxadc: auxadc@11001000 { 668748c7d4dSSascha Hauer compatible = "mediatek,mt8173-auxadc"; 669748c7d4dSSascha Hauer reg = <0 0x11001000 0 0x1000>; 670a3207d64SMatthias Brugger clocks = <&pericfg CLK_PERI_AUXADC>; 671a3207d64SMatthias Brugger clock-names = "main"; 672a3207d64SMatthias Brugger #io-channel-cells = <1>; 673748c7d4dSSascha Hauer }; 674748c7d4dSSascha Hauer 675b3a37248SEddie Huang uart0: serial@11002000 { 676b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 677b3a37248SEddie Huang "mediatek,mt6577-uart"; 678b3a37248SEddie Huang reg = <0 0x11002000 0 0x400>; 679b3a37248SEddie Huang interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 6800e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 6810e84faa1SSascha Hauer clock-names = "baud", "bus"; 682b3a37248SEddie Huang status = "disabled"; 683b3a37248SEddie Huang }; 684b3a37248SEddie Huang 685b3a37248SEddie Huang uart1: serial@11003000 { 686b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 687b3a37248SEddie Huang "mediatek,mt6577-uart"; 688b3a37248SEddie Huang reg = <0 0x11003000 0 0x400>; 689b3a37248SEddie Huang interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 6900e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 6910e84faa1SSascha Hauer clock-names = "baud", "bus"; 692b3a37248SEddie Huang status = "disabled"; 693b3a37248SEddie Huang }; 694b3a37248SEddie Huang 695b3a37248SEddie Huang uart2: serial@11004000 { 696b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 697b3a37248SEddie Huang "mediatek,mt6577-uart"; 698b3a37248SEddie Huang reg = <0 0x11004000 0 0x400>; 699b3a37248SEddie Huang interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 7000e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 7010e84faa1SSascha Hauer clock-names = "baud", "bus"; 702b3a37248SEddie Huang status = "disabled"; 703b3a37248SEddie Huang }; 704b3a37248SEddie Huang 705b3a37248SEddie Huang uart3: serial@11005000 { 706b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 707b3a37248SEddie Huang "mediatek,mt6577-uart"; 708b3a37248SEddie Huang reg = <0 0x11005000 0 0x400>; 709b3a37248SEddie Huang interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 7100e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 7110e84faa1SSascha Hauer clock-names = "baud", "bus"; 712b3a37248SEddie Huang status = "disabled"; 713b3a37248SEddie Huang }; 714091cf598SEddie Huang 715091cf598SEddie Huang i2c0: i2c@11007000 { 716091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 717091cf598SEddie Huang reg = <0 0x11007000 0 0x70>, 718091cf598SEddie Huang <0 0x11000100 0 0x80>; 719091cf598SEddie Huang interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 720091cf598SEddie Huang clock-div = <16>; 721091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C0>, 722091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 723091cf598SEddie Huang clock-names = "main", "dma"; 724091cf598SEddie Huang pinctrl-names = "default"; 725091cf598SEddie Huang pinctrl-0 = <&i2c0_pins_a>; 726091cf598SEddie Huang #address-cells = <1>; 727091cf598SEddie Huang #size-cells = <0>; 728091cf598SEddie Huang status = "disabled"; 729091cf598SEddie Huang }; 730091cf598SEddie Huang 731091cf598SEddie Huang i2c1: i2c@11008000 { 732091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 733091cf598SEddie Huang reg = <0 0x11008000 0 0x70>, 734091cf598SEddie Huang <0 0x11000180 0 0x80>; 735091cf598SEddie Huang interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 736091cf598SEddie Huang clock-div = <16>; 737091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C1>, 738091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 739091cf598SEddie Huang clock-names = "main", "dma"; 740091cf598SEddie Huang pinctrl-names = "default"; 741091cf598SEddie Huang pinctrl-0 = <&i2c1_pins_a>; 742091cf598SEddie Huang #address-cells = <1>; 743091cf598SEddie Huang #size-cells = <0>; 744091cf598SEddie Huang status = "disabled"; 745091cf598SEddie Huang }; 746091cf598SEddie Huang 747091cf598SEddie Huang i2c2: i2c@11009000 { 748091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 749091cf598SEddie Huang reg = <0 0x11009000 0 0x70>, 750091cf598SEddie Huang <0 0x11000200 0 0x80>; 751091cf598SEddie Huang interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 752091cf598SEddie Huang clock-div = <16>; 753091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C2>, 754091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 755091cf598SEddie Huang clock-names = "main", "dma"; 756091cf598SEddie Huang pinctrl-names = "default"; 757091cf598SEddie Huang pinctrl-0 = <&i2c2_pins_a>; 758091cf598SEddie Huang #address-cells = <1>; 759091cf598SEddie Huang #size-cells = <0>; 760091cf598SEddie Huang status = "disabled"; 761091cf598SEddie Huang }; 762091cf598SEddie Huang 763b0c936f5SLeilk Liu spi: spi@1100a000 { 764b0c936f5SLeilk Liu compatible = "mediatek,mt8173-spi"; 765b0c936f5SLeilk Liu #address-cells = <1>; 766b0c936f5SLeilk Liu #size-cells = <0>; 767b0c936f5SLeilk Liu reg = <0 0x1100a000 0 0x1000>; 768b0c936f5SLeilk Liu interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 769b0c936f5SLeilk Liu clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 770b0c936f5SLeilk Liu <&topckgen CLK_TOP_SPI_SEL>, 771b0c936f5SLeilk Liu <&pericfg CLK_PERI_SPI0>; 772b0c936f5SLeilk Liu clock-names = "parent-clk", "sel-clk", "spi-clk"; 773b0c936f5SLeilk Liu status = "disabled"; 774b0c936f5SLeilk Liu }; 775b0c936f5SLeilk Liu 776748c7d4dSSascha Hauer thermal: thermal@1100b000 { 777748c7d4dSSascha Hauer #thermal-sensor-cells = <0>; 778748c7d4dSSascha Hauer compatible = "mediatek,mt8173-thermal"; 779748c7d4dSSascha Hauer reg = <0 0x1100b000 0 0x1000>; 780748c7d4dSSascha Hauer interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 781748c7d4dSSascha Hauer clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 782748c7d4dSSascha Hauer clock-names = "therm", "auxadc"; 783748c7d4dSSascha Hauer resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 784748c7d4dSSascha Hauer mediatek,auxadc = <&auxadc>; 785748c7d4dSSascha Hauer mediatek,apmixedsys = <&apmixedsys>; 7866de18454Sdawei.chien@mediatek.com nvmem-cells = <&thermal_calibration>; 7876de18454Sdawei.chien@mediatek.com nvmem-cell-names = "calibration-data"; 788748c7d4dSSascha Hauer }; 789748c7d4dSSascha Hauer 79086cb8a88SBayi Cheng nor_flash: spi@1100d000 { 79186cb8a88SBayi Cheng compatible = "mediatek,mt8173-nor"; 79286cb8a88SBayi Cheng reg = <0 0x1100d000 0 0xe0>; 79386cb8a88SBayi Cheng clocks = <&pericfg CLK_PERI_SPI>, 79486cb8a88SBayi Cheng <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 79586cb8a88SBayi Cheng clock-names = "spi", "sf"; 79686cb8a88SBayi Cheng #address-cells = <1>; 79786cb8a88SBayi Cheng #size-cells = <0>; 79886cb8a88SBayi Cheng status = "disabled"; 79986cb8a88SBayi Cheng }; 80086cb8a88SBayi Cheng 8011ee35c05SYingjoe Chen i2c3: i2c@11010000 { 802091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 803091cf598SEddie Huang reg = <0 0x11010000 0 0x70>, 804091cf598SEddie Huang <0 0x11000280 0 0x80>; 805091cf598SEddie Huang interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 806091cf598SEddie Huang clock-div = <16>; 807091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C3>, 808091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 809091cf598SEddie Huang clock-names = "main", "dma"; 810091cf598SEddie Huang pinctrl-names = "default"; 811091cf598SEddie Huang pinctrl-0 = <&i2c3_pins_a>; 812091cf598SEddie Huang #address-cells = <1>; 813091cf598SEddie Huang #size-cells = <0>; 814091cf598SEddie Huang status = "disabled"; 815091cf598SEddie Huang }; 816091cf598SEddie Huang 8171ee35c05SYingjoe Chen i2c4: i2c@11011000 { 818091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 819091cf598SEddie Huang reg = <0 0x11011000 0 0x70>, 820091cf598SEddie Huang <0 0x11000300 0 0x80>; 821091cf598SEddie Huang interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 822091cf598SEddie Huang clock-div = <16>; 823091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C4>, 824091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 825091cf598SEddie Huang clock-names = "main", "dma"; 826091cf598SEddie Huang pinctrl-names = "default"; 827091cf598SEddie Huang pinctrl-0 = <&i2c4_pins_a>; 828091cf598SEddie Huang #address-cells = <1>; 829091cf598SEddie Huang #size-cells = <0>; 830091cf598SEddie Huang status = "disabled"; 831091cf598SEddie Huang }; 832091cf598SEddie Huang 833a10b57f4SCK Hu hdmiddc0: i2c@11012000 { 834a10b57f4SCK Hu compatible = "mediatek,mt8173-hdmi-ddc"; 835a10b57f4SCK Hu interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 836a10b57f4SCK Hu reg = <0 0x11012000 0 0x1C>; 837a10b57f4SCK Hu clocks = <&pericfg CLK_PERI_I2C5>; 838a10b57f4SCK Hu clock-names = "ddc-i2c"; 839a10b57f4SCK Hu }; 840a10b57f4SCK Hu 8411ee35c05SYingjoe Chen i2c6: i2c@11013000 { 842091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 843091cf598SEddie Huang reg = <0 0x11013000 0 0x70>, 844091cf598SEddie Huang <0 0x11000080 0 0x80>; 845091cf598SEddie Huang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 846091cf598SEddie Huang clock-div = <16>; 847091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C6>, 848091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 849091cf598SEddie Huang clock-names = "main", "dma"; 850091cf598SEddie Huang pinctrl-names = "default"; 851091cf598SEddie Huang pinctrl-0 = <&i2c6_pins_a>; 852091cf598SEddie Huang #address-cells = <1>; 853091cf598SEddie Huang #size-cells = <0>; 854091cf598SEddie Huang status = "disabled"; 855091cf598SEddie Huang }; 856c02e0e86SKoro Chen 857c02e0e86SKoro Chen afe: audio-controller@11220000 { 858c02e0e86SKoro Chen compatible = "mediatek,mt8173-afe-pcm"; 859c02e0e86SKoro Chen reg = <0 0x11220000 0 0x1000>; 860c02e0e86SKoro Chen interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 8618b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_AUDIO>; 862c02e0e86SKoro Chen clocks = <&infracfg CLK_INFRA_AUDIO>, 863c02e0e86SKoro Chen <&topckgen CLK_TOP_AUDIO_SEL>, 864c02e0e86SKoro Chen <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 865c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL1_DIV0>, 866c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL2_DIV0>, 867c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S0_M_SEL>, 868c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S1_M_SEL>, 869c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S2_M_SEL>, 870c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S3_M_SEL>, 871c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S3_B_SEL>; 872c02e0e86SKoro Chen clock-names = "infra_sys_audio_clk", 873c02e0e86SKoro Chen "top_pdn_audio", 874c02e0e86SKoro Chen "top_pdn_aud_intbus", 875c02e0e86SKoro Chen "bck0", 876c02e0e86SKoro Chen "bck1", 877c02e0e86SKoro Chen "i2s0_m", 878c02e0e86SKoro Chen "i2s1_m", 879c02e0e86SKoro Chen "i2s2_m", 880c02e0e86SKoro Chen "i2s3_m", 881c02e0e86SKoro Chen "i2s3_b"; 882c02e0e86SKoro Chen assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 883c02e0e86SKoro Chen <&topckgen CLK_TOP_AUD_2_SEL>; 884c02e0e86SKoro Chen assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 885c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL2>; 886c02e0e86SKoro Chen }; 8879719fa5aSEddie Huang 8889719fa5aSEddie Huang mmc0: mmc@11230000 { 889689362b3SChaotian Jing compatible = "mediatek,mt8173-mmc"; 8909719fa5aSEddie Huang reg = <0 0x11230000 0 0x1000>; 8919719fa5aSEddie Huang interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 8929719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_0>, 8939719fa5aSEddie Huang <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 8949719fa5aSEddie Huang clock-names = "source", "hclk"; 8959719fa5aSEddie Huang status = "disabled"; 8969719fa5aSEddie Huang }; 8979719fa5aSEddie Huang 8989719fa5aSEddie Huang mmc1: mmc@11240000 { 899689362b3SChaotian Jing compatible = "mediatek,mt8173-mmc"; 9009719fa5aSEddie Huang reg = <0 0x11240000 0 0x1000>; 9019719fa5aSEddie Huang interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 9029719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_1>, 9039719fa5aSEddie Huang <&topckgen CLK_TOP_AXI_SEL>; 9049719fa5aSEddie Huang clock-names = "source", "hclk"; 9059719fa5aSEddie Huang status = "disabled"; 9069719fa5aSEddie Huang }; 9079719fa5aSEddie Huang 9089719fa5aSEddie Huang mmc2: mmc@11250000 { 909689362b3SChaotian Jing compatible = "mediatek,mt8173-mmc"; 9109719fa5aSEddie Huang reg = <0 0x11250000 0 0x1000>; 9119719fa5aSEddie Huang interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 9129719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_2>, 9139719fa5aSEddie Huang <&topckgen CLK_TOP_AXI_SEL>; 9149719fa5aSEddie Huang clock-names = "source", "hclk"; 9159719fa5aSEddie Huang status = "disabled"; 9169719fa5aSEddie Huang }; 9179719fa5aSEddie Huang 9189719fa5aSEddie Huang mmc3: mmc@11260000 { 919689362b3SChaotian Jing compatible = "mediatek,mt8173-mmc"; 9209719fa5aSEddie Huang reg = <0 0x11260000 0 0x1000>; 9219719fa5aSEddie Huang interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 9229719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_3>, 9239719fa5aSEddie Huang <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 9249719fa5aSEddie Huang clock-names = "source", "hclk"; 9259719fa5aSEddie Huang status = "disabled"; 9269719fa5aSEddie Huang }; 92767e56c56SJames Liao 928c0891284SChunfeng Yun ssusb: usb@11271000 { 929c61872d5SChunfeng Yun compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3"; 930c0891284SChunfeng Yun reg = <0 0x11271000 0 0x3000>, 931bfcce47aSChunfeng Yun <0 0x11280700 0 0x0100>; 932c0891284SChunfeng Yun reg-names = "mac", "ippc"; 933c0891284SChunfeng Yun interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>; 934ebf61c63Schunfeng.yun@mediatek.com phys = <&u2port0 PHY_TYPE_USB2>, 935ebf61c63Schunfeng.yun@mediatek.com <&u3port0 PHY_TYPE_USB3>, 936ebf61c63Schunfeng.yun@mediatek.com <&u2port1 PHY_TYPE_USB2>; 9378b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_USB>; 938cf1fcd45SChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 939cf1fcd45SChunfeng Yun clock-names = "sys_ck", "ref_ck"; 940cf1fcd45SChunfeng Yun mediatek,syscon-wakeup = <&pericfg 0x400 1>; 941c0891284SChunfeng Yun #address-cells = <2>; 942c0891284SChunfeng Yun #size-cells = <2>; 943c0891284SChunfeng Yun ranges; 944c0891284SChunfeng Yun status = "disabled"; 945c0891284SChunfeng Yun 946c61872d5SChunfeng Yun usb_host: usb@11270000 { 947c61872d5SChunfeng Yun compatible = "mediatek,mt8173-xhci", 948c61872d5SChunfeng Yun "mediatek,mtk-xhci"; 949c0891284SChunfeng Yun reg = <0 0x11270000 0 0x1000>; 950c0891284SChunfeng Yun reg-names = "mac"; 951c0891284SChunfeng Yun interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 9528b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_USB>; 953cb6efc7bSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 954cb6efc7bSChunfeng Yun clock-names = "sys_ck", "ref_ck"; 955c0891284SChunfeng Yun status = "disabled"; 956c0891284SChunfeng Yun }; 957bfcce47aSChunfeng Yun }; 958bfcce47aSChunfeng Yun 959c61872d5SChunfeng Yun u3phy: t-phy@11290000 { 960bfcce47aSChunfeng Yun compatible = "mediatek,mt8173-u3phy"; 961bfcce47aSChunfeng Yun reg = <0 0x11290000 0 0x800>; 962bfcce47aSChunfeng Yun #address-cells = <2>; 963bfcce47aSChunfeng Yun #size-cells = <2>; 964bfcce47aSChunfeng Yun ranges; 965bfcce47aSChunfeng Yun status = "okay"; 966bfcce47aSChunfeng Yun 967ebf61c63Schunfeng.yun@mediatek.com u2port0: usb-phy@11290800 { 968ebf61c63Schunfeng.yun@mediatek.com reg = <0 0x11290800 0 0x100>; 96910f84a7aSchunfeng.yun@mediatek.com clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 97010f84a7aSchunfeng.yun@mediatek.com clock-names = "ref"; 971bfcce47aSChunfeng Yun #phy-cells = <1>; 972bfcce47aSChunfeng Yun status = "okay"; 973bfcce47aSChunfeng Yun }; 974bfcce47aSChunfeng Yun 975ebf61c63Schunfeng.yun@mediatek.com u3port0: usb-phy@11290900 { 976ebf61c63Schunfeng.yun@mediatek.com reg = <0 0x11290900 0 0x700>; 97710f84a7aSchunfeng.yun@mediatek.com clocks = <&clk26m>; 97810f84a7aSchunfeng.yun@mediatek.com clock-names = "ref"; 979ebf61c63Schunfeng.yun@mediatek.com #phy-cells = <1>; 980ebf61c63Schunfeng.yun@mediatek.com status = "okay"; 981ebf61c63Schunfeng.yun@mediatek.com }; 982ebf61c63Schunfeng.yun@mediatek.com 983ebf61c63Schunfeng.yun@mediatek.com u2port1: usb-phy@11291000 { 984ebf61c63Schunfeng.yun@mediatek.com reg = <0 0x11291000 0 0x100>; 98510f84a7aSchunfeng.yun@mediatek.com clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 98610f84a7aSchunfeng.yun@mediatek.com clock-names = "ref"; 987bfcce47aSChunfeng Yun #phy-cells = <1>; 988bfcce47aSChunfeng Yun status = "okay"; 989bfcce47aSChunfeng Yun }; 990bfcce47aSChunfeng Yun }; 991bfcce47aSChunfeng Yun 992ae167ae2SEnric Balletbo i Serra mmsys: syscon@14000000 { 99367e56c56SJames Liao compatible = "mediatek,mt8173-mmsys", "syscon"; 99467e56c56SJames Liao reg = <0 0x14000000 0 0x1000>; 9958b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 996fc6634acSBibby Hsieh assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; 997fc6634acSBibby Hsieh assigned-clock-rates = <400000000>; 99867e56c56SJames Liao #clock-cells = <1>; 9997fdb1bc3SEnric Balletbo i Serra #reset-cells = <1>; 1000eb4a01afSHsin-Yi Wang mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 1001eb4a01afSHsin-Yi Wang <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 1002eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 100367e56c56SJames Liao }; 100467e56c56SJames Liao 1005989b292aSMinghsiu Tsai mdp_rdma0: rdma@14001000 { 10068127881fSDaniel Kurtz compatible = "mediatek,mt8173-mdp-rdma", 10078127881fSDaniel Kurtz "mediatek,mt8173-mdp"; 1008989b292aSMinghsiu Tsai reg = <0 0x14001000 0 0x1000>; 1009989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RDMA0>, 1010989b292aSMinghsiu Tsai <&mmsys CLK_MM_MUTEX_32K>; 10118b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1012989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_RDMA0>; 10138127881fSDaniel Kurtz mediatek,vpu = <&vpu>; 1014989b292aSMinghsiu Tsai }; 1015989b292aSMinghsiu Tsai 1016989b292aSMinghsiu Tsai mdp_rdma1: rdma@14002000 { 1017989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rdma"; 1018989b292aSMinghsiu Tsai reg = <0 0x14002000 0 0x1000>; 1019989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RDMA1>, 1020989b292aSMinghsiu Tsai <&mmsys CLK_MM_MUTEX_32K>; 10218b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1022989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_RDMA1>; 1023989b292aSMinghsiu Tsai }; 1024989b292aSMinghsiu Tsai 1025989b292aSMinghsiu Tsai mdp_rsz0: rsz@14003000 { 1026989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rsz"; 1027989b292aSMinghsiu Tsai reg = <0 0x14003000 0 0x1000>; 1028989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RSZ0>; 10298b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1030989b292aSMinghsiu Tsai }; 1031989b292aSMinghsiu Tsai 1032989b292aSMinghsiu Tsai mdp_rsz1: rsz@14004000 { 1033989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rsz"; 1034989b292aSMinghsiu Tsai reg = <0 0x14004000 0 0x1000>; 1035989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RSZ1>; 10368b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1037989b292aSMinghsiu Tsai }; 1038989b292aSMinghsiu Tsai 1039989b292aSMinghsiu Tsai mdp_rsz2: rsz@14005000 { 1040989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rsz"; 1041989b292aSMinghsiu Tsai reg = <0 0x14005000 0 0x1000>; 1042989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RSZ2>; 10438b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1044989b292aSMinghsiu Tsai }; 1045989b292aSMinghsiu Tsai 1046989b292aSMinghsiu Tsai mdp_wdma0: wdma@14006000 { 1047989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-wdma"; 1048989b292aSMinghsiu Tsai reg = <0 0x14006000 0 0x1000>; 1049989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_WDMA>; 10508b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1051989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_WDMA>; 1052989b292aSMinghsiu Tsai }; 1053989b292aSMinghsiu Tsai 1054989b292aSMinghsiu Tsai mdp_wrot0: wrot@14007000 { 1055989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-wrot"; 1056989b292aSMinghsiu Tsai reg = <0 0x14007000 0 0x1000>; 1057989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_WROT0>; 10588b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1059989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_WROT0>; 1060989b292aSMinghsiu Tsai }; 1061989b292aSMinghsiu Tsai 1062989b292aSMinghsiu Tsai mdp_wrot1: wrot@14008000 { 1063989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-wrot"; 1064989b292aSMinghsiu Tsai reg = <0 0x14008000 0 0x1000>; 1065989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_WROT1>; 10668b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1067989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_WROT1>; 1068989b292aSMinghsiu Tsai }; 1069989b292aSMinghsiu Tsai 107081ad4dbaSCK Hu ovl0: ovl@1400c000 { 107181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-ovl"; 107281ad4dbaSCK Hu reg = <0 0x1400c000 0 0x1000>; 107381ad4dbaSCK Hu interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 10748b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 107581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_OVL0>; 107681ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_OVL0>; 1077eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 107881ad4dbaSCK Hu }; 107981ad4dbaSCK Hu 108081ad4dbaSCK Hu ovl1: ovl@1400d000 { 108181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-ovl"; 108281ad4dbaSCK Hu reg = <0 0x1400d000 0 0x1000>; 108381ad4dbaSCK Hu interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; 10848b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 108581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_OVL1>; 108681ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_OVL1>; 1087eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 108881ad4dbaSCK Hu }; 108981ad4dbaSCK Hu 109081ad4dbaSCK Hu rdma0: rdma@1400e000 { 109181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-rdma"; 109281ad4dbaSCK Hu reg = <0 0x1400e000 0 0x1000>; 109381ad4dbaSCK Hu interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 10948b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 109581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_RDMA0>; 109681ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_RDMA0>; 1097eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 109881ad4dbaSCK Hu }; 109981ad4dbaSCK Hu 110081ad4dbaSCK Hu rdma1: rdma@1400f000 { 110181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-rdma"; 110281ad4dbaSCK Hu reg = <0 0x1400f000 0 0x1000>; 110381ad4dbaSCK Hu interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; 11048b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 110581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_RDMA1>; 110681ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_RDMA1>; 1107eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; 110881ad4dbaSCK Hu }; 110981ad4dbaSCK Hu 111081ad4dbaSCK Hu rdma2: rdma@14010000 { 111181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-rdma"; 111281ad4dbaSCK Hu reg = <0 0x14010000 0 0x1000>; 111381ad4dbaSCK Hu interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; 11148b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 111581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_RDMA2>; 111681ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_RDMA2>; 1117eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; 111881ad4dbaSCK Hu }; 111981ad4dbaSCK Hu 112081ad4dbaSCK Hu wdma0: wdma@14011000 { 112181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-wdma"; 112281ad4dbaSCK Hu reg = <0 0x14011000 0 0x1000>; 112381ad4dbaSCK Hu interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 11248b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 112581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_WDMA0>; 112681ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_WDMA0>; 1127eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 112881ad4dbaSCK Hu }; 112981ad4dbaSCK Hu 113081ad4dbaSCK Hu wdma1: wdma@14012000 { 113181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-wdma"; 113281ad4dbaSCK Hu reg = <0 0x14012000 0 0x1000>; 113381ad4dbaSCK Hu interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; 11348b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 113581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_WDMA1>; 113681ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_WDMA1>; 1137eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; 113881ad4dbaSCK Hu }; 113981ad4dbaSCK Hu 114081ad4dbaSCK Hu color0: color@14013000 { 114181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-color"; 114281ad4dbaSCK Hu reg = <0 0x14013000 0 0x1000>; 114381ad4dbaSCK Hu interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; 11448b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 114581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1146eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>; 114781ad4dbaSCK Hu }; 114881ad4dbaSCK Hu 114981ad4dbaSCK Hu color1: color@14014000 { 115081ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-color"; 115181ad4dbaSCK Hu reg = <0 0x14014000 0 0x1000>; 115281ad4dbaSCK Hu interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 11538b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 115481ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_COLOR1>; 1155eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; 115681ad4dbaSCK Hu }; 115781ad4dbaSCK Hu 115881ad4dbaSCK Hu aal@14015000 { 115981ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-aal"; 116081ad4dbaSCK Hu reg = <0 0x14015000 0 0x1000>; 116181ad4dbaSCK Hu interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 11628b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 116381ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_AAL>; 1164eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; 116581ad4dbaSCK Hu }; 116681ad4dbaSCK Hu 116781ad4dbaSCK Hu gamma@14016000 { 116881ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-gamma"; 116981ad4dbaSCK Hu reg = <0 0x14016000 0 0x1000>; 117081ad4dbaSCK Hu interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 11718b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 117281ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_GAMMA>; 1173eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; 117481ad4dbaSCK Hu }; 117581ad4dbaSCK Hu 117681ad4dbaSCK Hu merge@14017000 { 117781ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-merge"; 117881ad4dbaSCK Hu reg = <0 0x14017000 0 0x1000>; 11798b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 118081ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_MERGE>; 118181ad4dbaSCK Hu }; 118281ad4dbaSCK Hu 118381ad4dbaSCK Hu split0: split@14018000 { 118481ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-split"; 118581ad4dbaSCK Hu reg = <0 0x14018000 0 0x1000>; 11868b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 118781ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_SPLIT0>; 118881ad4dbaSCK Hu }; 118981ad4dbaSCK Hu 119081ad4dbaSCK Hu split1: split@14019000 { 119181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-split"; 119281ad4dbaSCK Hu reg = <0 0x14019000 0 0x1000>; 11938b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 119481ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_SPLIT1>; 119581ad4dbaSCK Hu }; 119681ad4dbaSCK Hu 119781ad4dbaSCK Hu ufoe@1401a000 { 119881ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-ufoe"; 119981ad4dbaSCK Hu reg = <0 0x1401a000 0 0x1000>; 120081ad4dbaSCK Hu interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 12018b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 120281ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_UFOE>; 1203ab0c1e34SAngeloGioacchino Del Regno mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>; 120481ad4dbaSCK Hu }; 120581ad4dbaSCK Hu 120681ad4dbaSCK Hu dsi0: dsi@1401b000 { 120781ad4dbaSCK Hu compatible = "mediatek,mt8173-dsi"; 120881ad4dbaSCK Hu reg = <0 0x1401b000 0 0x1000>; 120981ad4dbaSCK Hu interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 12108b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 121181ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DSI0_ENGINE>, 121281ad4dbaSCK Hu <&mmsys CLK_MM_DSI0_DIGITAL>, 121381ad4dbaSCK Hu <&mipi_tx0>; 121481ad4dbaSCK Hu clock-names = "engine", "digital", "hs"; 12157fdb1bc3SEnric Balletbo i Serra resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>; 121681ad4dbaSCK Hu phys = <&mipi_tx0>; 121781ad4dbaSCK Hu phy-names = "dphy"; 121881ad4dbaSCK Hu status = "disabled"; 121981ad4dbaSCK Hu }; 122081ad4dbaSCK Hu 122181ad4dbaSCK Hu dsi1: dsi@1401c000 { 122281ad4dbaSCK Hu compatible = "mediatek,mt8173-dsi"; 122381ad4dbaSCK Hu reg = <0 0x1401c000 0 0x1000>; 122481ad4dbaSCK Hu interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 12258b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 122681ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DSI1_ENGINE>, 122781ad4dbaSCK Hu <&mmsys CLK_MM_DSI1_DIGITAL>, 122881ad4dbaSCK Hu <&mipi_tx1>; 122981ad4dbaSCK Hu clock-names = "engine", "digital", "hs"; 1230e4e5d030SChunfeng Yun phys = <&mipi_tx1>; 123181ad4dbaSCK Hu phy-names = "dphy"; 123281ad4dbaSCK Hu status = "disabled"; 123381ad4dbaSCK Hu }; 123481ad4dbaSCK Hu 123581ad4dbaSCK Hu dpi0: dpi@1401d000 { 123681ad4dbaSCK Hu compatible = "mediatek,mt8173-dpi"; 123781ad4dbaSCK Hu reg = <0 0x1401d000 0 0x1000>; 123881ad4dbaSCK Hu interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 12398b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 124081ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DPI_PIXEL>, 124181ad4dbaSCK Hu <&mmsys CLK_MM_DPI_ENGINE>, 124281ad4dbaSCK Hu <&apmixedsys CLK_APMIXED_TVDPLL>; 124381ad4dbaSCK Hu clock-names = "pixel", "engine", "pll"; 124481ad4dbaSCK Hu status = "disabled"; 1245a10b57f4SCK Hu 1246a10b57f4SCK Hu port { 1247a10b57f4SCK Hu dpi0_out: endpoint { 1248a10b57f4SCK Hu remote-endpoint = <&hdmi0_in>; 1249a10b57f4SCK Hu }; 1250a10b57f4SCK Hu }; 125181ad4dbaSCK Hu }; 125281ad4dbaSCK Hu 125361aee934SYH Huang pwm0: pwm@1401e000 { 125461aee934SYH Huang compatible = "mediatek,mt8173-disp-pwm", 125561aee934SYH Huang "mediatek,mt6595-disp-pwm"; 125661aee934SYH Huang reg = <0 0x1401e000 0 0x1000>; 125761aee934SYH Huang #pwm-cells = <2>; 125861aee934SYH Huang clocks = <&mmsys CLK_MM_DISP_PWM026M>, 125961aee934SYH Huang <&mmsys CLK_MM_DISP_PWM0MM>; 126061aee934SYH Huang clock-names = "main", "mm"; 126161aee934SYH Huang status = "disabled"; 126261aee934SYH Huang }; 126361aee934SYH Huang 126461aee934SYH Huang pwm1: pwm@1401f000 { 126561aee934SYH Huang compatible = "mediatek,mt8173-disp-pwm", 126661aee934SYH Huang "mediatek,mt6595-disp-pwm"; 126761aee934SYH Huang reg = <0 0x1401f000 0 0x1000>; 126861aee934SYH Huang #pwm-cells = <2>; 126961aee934SYH Huang clocks = <&mmsys CLK_MM_DISP_PWM126M>, 127061aee934SYH Huang <&mmsys CLK_MM_DISP_PWM1MM>; 127161aee934SYH Huang clock-names = "main", "mm"; 127261aee934SYH Huang status = "disabled"; 127361aee934SYH Huang }; 127461aee934SYH Huang 127581ad4dbaSCK Hu mutex: mutex@14020000 { 127681ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-mutex"; 127781ad4dbaSCK Hu reg = <0 0x14020000 0 0x1000>; 127881ad4dbaSCK Hu interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 12798b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 128081ad4dbaSCK Hu clocks = <&mmsys CLK_MM_MUTEX_32K>; 1281eb4a01afSHsin-Yi Wang mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>, 1282eb4a01afSHsin-Yi Wang <CMDQ_EVENT_MUTEX1_STREAM_EOF>; 128381ad4dbaSCK Hu }; 128481ad4dbaSCK Hu 12855ff6b3a6SYong Wu larb0: larb@14021000 { 12865ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 12875ff6b3a6SYong Wu reg = <0 0x14021000 0 0x1000>; 12885ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 12898b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 12905ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_LARB0>, 12915ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_LARB0>; 12925ff6b3a6SYong Wu clock-names = "apb", "smi"; 12935ff6b3a6SYong Wu }; 12945ff6b3a6SYong Wu 12955ff6b3a6SYong Wu smi_common: smi@14022000 { 12965ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-common"; 12975ff6b3a6SYong Wu reg = <0 0x14022000 0 0x1000>; 12988b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 12995ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_COMMON>, 13005ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_COMMON>; 13015ff6b3a6SYong Wu clock-names = "apb", "smi"; 13025ff6b3a6SYong Wu }; 13035ff6b3a6SYong Wu 130481ad4dbaSCK Hu od@14023000 { 130581ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-od"; 130681ad4dbaSCK Hu reg = <0 0x14023000 0 0x1000>; 130781ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_OD>; 1308ab0c1e34SAngeloGioacchino Del Regno mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>; 130981ad4dbaSCK Hu }; 131081ad4dbaSCK Hu 1311a10b57f4SCK Hu hdmi0: hdmi@14025000 { 1312a10b57f4SCK Hu compatible = "mediatek,mt8173-hdmi"; 1313a10b57f4SCK Hu reg = <0 0x14025000 0 0x400>; 1314a10b57f4SCK Hu interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>; 1315a10b57f4SCK Hu clocks = <&mmsys CLK_MM_HDMI_PIXEL>, 1316a10b57f4SCK Hu <&mmsys CLK_MM_HDMI_PLLCK>, 1317a10b57f4SCK Hu <&mmsys CLK_MM_HDMI_AUDIO>, 1318a10b57f4SCK Hu <&mmsys CLK_MM_HDMI_SPDIF>; 1319a10b57f4SCK Hu clock-names = "pixel", "pll", "bclk", "spdif"; 1320a10b57f4SCK Hu pinctrl-names = "default"; 1321a10b57f4SCK Hu pinctrl-0 = <&hdmi_pin>; 1322a10b57f4SCK Hu phys = <&hdmi_phy>; 1323a10b57f4SCK Hu phy-names = "hdmi"; 1324a10b57f4SCK Hu mediatek,syscon-hdmi = <&mmsys 0x900>; 1325a10b57f4SCK Hu assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; 1326a10b57f4SCK Hu assigned-clock-parents = <&hdmi_phy>; 1327a10b57f4SCK Hu status = "disabled"; 1328a10b57f4SCK Hu 1329a10b57f4SCK Hu ports { 1330a10b57f4SCK Hu #address-cells = <1>; 1331a10b57f4SCK Hu #size-cells = <0>; 1332a10b57f4SCK Hu 1333a10b57f4SCK Hu port@0 { 1334a10b57f4SCK Hu reg = <0>; 1335a10b57f4SCK Hu 1336a10b57f4SCK Hu hdmi0_in: endpoint { 1337a10b57f4SCK Hu remote-endpoint = <&dpi0_out>; 1338a10b57f4SCK Hu }; 1339a10b57f4SCK Hu }; 1340a10b57f4SCK Hu }; 1341a10b57f4SCK Hu }; 1342a10b57f4SCK Hu 13435ff6b3a6SYong Wu larb4: larb@14027000 { 13445ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 13455ff6b3a6SYong Wu reg = <0 0x14027000 0 0x1000>; 13465ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 13478b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 13485ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_LARB4>, 13495ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_LARB4>; 13505ff6b3a6SYong Wu clock-names = "apb", "smi"; 13515ff6b3a6SYong Wu }; 13525ff6b3a6SYong Wu 135367e56c56SJames Liao imgsys: clock-controller@15000000 { 135467e56c56SJames Liao compatible = "mediatek,mt8173-imgsys", "syscon"; 135567e56c56SJames Liao reg = <0 0x15000000 0 0x1000>; 135667e56c56SJames Liao #clock-cells = <1>; 135767e56c56SJames Liao }; 135867e56c56SJames Liao 13595ff6b3a6SYong Wu larb2: larb@15001000 { 13605ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 13615ff6b3a6SYong Wu reg = <0 0x15001000 0 0x1000>; 13625ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 13638b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_ISP>; 13645ff6b3a6SYong Wu clocks = <&imgsys CLK_IMG_LARB2_SMI>, 13655ff6b3a6SYong Wu <&imgsys CLK_IMG_LARB2_SMI>; 13665ff6b3a6SYong Wu clock-names = "apb", "smi"; 13675ff6b3a6SYong Wu }; 13685ff6b3a6SYong Wu 136967e56c56SJames Liao vdecsys: clock-controller@16000000 { 137067e56c56SJames Liao compatible = "mediatek,mt8173-vdecsys", "syscon"; 137167e56c56SJames Liao reg = <0 0x16000000 0 0x1000>; 137267e56c56SJames Liao #clock-cells = <1>; 137367e56c56SJames Liao }; 137467e56c56SJames Liao 137560eaae2bSTiffany Lin vcodec_dec: vcodec@16000000 { 137660eaae2bSTiffany Lin compatible = "mediatek,mt8173-vcodec-dec"; 137760eaae2bSTiffany Lin reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */ 137860eaae2bSTiffany Lin <0 0x16020000 0 0x1000>, /* VDEC_MISC */ 137960eaae2bSTiffany Lin <0 0x16021000 0 0x800>, /* VDEC_LD */ 138060eaae2bSTiffany Lin <0 0x16021800 0 0x800>, /* VDEC_TOP */ 138160eaae2bSTiffany Lin <0 0x16022000 0 0x1000>, /* VDEC_CM */ 138260eaae2bSTiffany Lin <0 0x16023000 0 0x1000>, /* VDEC_AD */ 138360eaae2bSTiffany Lin <0 0x16024000 0 0x1000>, /* VDEC_AV */ 138460eaae2bSTiffany Lin <0 0x16025000 0 0x1000>, /* VDEC_PP */ 138560eaae2bSTiffany Lin <0 0x16026800 0 0x800>, /* VDEC_HWD */ 138660eaae2bSTiffany Lin <0 0x16027000 0 0x800>, /* VDEC_HWQ */ 138760eaae2bSTiffany Lin <0 0x16027800 0 0x800>, /* VDEC_HWB */ 138860eaae2bSTiffany Lin <0 0x16028400 0 0x400>; /* VDEC_HWG */ 138960eaae2bSTiffany Lin interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; 139060eaae2bSTiffany Lin iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, 139160eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_PP_EXT>, 139260eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, 139360eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, 139460eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, 139560eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, 139660eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, 139760eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; 139860eaae2bSTiffany Lin mediatek,vpu = <&vpu>; 13998b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>; 140060eaae2bSTiffany Lin clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, 140160eaae2bSTiffany Lin <&topckgen CLK_TOP_UNIVPLL_D2>, 140260eaae2bSTiffany Lin <&topckgen CLK_TOP_CCI400_SEL>, 140360eaae2bSTiffany Lin <&topckgen CLK_TOP_VDEC_SEL>, 140460eaae2bSTiffany Lin <&topckgen CLK_TOP_VCODECPLL>, 140560eaae2bSTiffany Lin <&apmixedsys CLK_APMIXED_VENCPLL>, 140660eaae2bSTiffany Lin <&topckgen CLK_TOP_VENC_LT_SEL>, 140760eaae2bSTiffany Lin <&topckgen CLK_TOP_VCODECPLL_370P5>; 140860eaae2bSTiffany Lin clock-names = "vcodecpll", 140960eaae2bSTiffany Lin "univpll_d2", 141060eaae2bSTiffany Lin "clk_cci400_sel", 141160eaae2bSTiffany Lin "vdec_sel", 141260eaae2bSTiffany Lin "vdecpll", 141360eaae2bSTiffany Lin "vencpll", 141460eaae2bSTiffany Lin "venc_lt_sel", 141560eaae2bSTiffany Lin "vdec_bus_clk_src"; 1416fbbad028SYunfei Dong assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>, 1417fbbad028SYunfei Dong <&topckgen CLK_TOP_CCI400_SEL>, 1418fbbad028SYunfei Dong <&topckgen CLK_TOP_VDEC_SEL>, 1419fbbad028SYunfei Dong <&apmixedsys CLK_APMIXED_VCODECPLL>, 1420fbbad028SYunfei Dong <&apmixedsys CLK_APMIXED_VENCPLL>; 1421fbbad028SYunfei Dong assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>, 1422fbbad028SYunfei Dong <&topckgen CLK_TOP_UNIVPLL_D2>, 1423fbbad028SYunfei Dong <&topckgen CLK_TOP_VCODECPLL>; 1424fbbad028SYunfei Dong assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>; 142560eaae2bSTiffany Lin }; 142660eaae2bSTiffany Lin 14275ff6b3a6SYong Wu larb1: larb@16010000 { 14285ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 14295ff6b3a6SYong Wu reg = <0 0x16010000 0 0x1000>; 14305ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 14318b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>; 14325ff6b3a6SYong Wu clocks = <&vdecsys CLK_VDEC_CKEN>, 14335ff6b3a6SYong Wu <&vdecsys CLK_VDEC_LARB_CKEN>; 14345ff6b3a6SYong Wu clock-names = "apb", "smi"; 14355ff6b3a6SYong Wu }; 14365ff6b3a6SYong Wu 143767e56c56SJames Liao vencsys: clock-controller@18000000 { 143867e56c56SJames Liao compatible = "mediatek,mt8173-vencsys", "syscon"; 143967e56c56SJames Liao reg = <0 0x18000000 0 0x1000>; 144067e56c56SJames Liao #clock-cells = <1>; 144167e56c56SJames Liao }; 144267e56c56SJames Liao 14435ff6b3a6SYong Wu larb3: larb@18001000 { 14445ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 14455ff6b3a6SYong Wu reg = <0 0x18001000 0 0x1000>; 14465ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 14478b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_VENC>; 14485ff6b3a6SYong Wu clocks = <&vencsys CLK_VENC_CKE1>, 14495ff6b3a6SYong Wu <&vencsys CLK_VENC_CKE0>; 14505ff6b3a6SYong Wu clock-names = "apb", "smi"; 14515ff6b3a6SYong Wu }; 14525ff6b3a6SYong Wu 1453e6f73028SIrui Wang vcodec_enc_avc: vcodec@18002000 { 14548eb80252STiffany Lin compatible = "mediatek,mt8173-vcodec-enc"; 1455e6f73028SIrui Wang reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */ 1456e6f73028SIrui Wang interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; 14578eb80252STiffany Lin iommus = <&iommu M4U_PORT_VENC_RCPU>, 14588eb80252STiffany Lin <&iommu M4U_PORT_VENC_REC>, 14598eb80252STiffany Lin <&iommu M4U_PORT_VENC_BSDMA>, 14608eb80252STiffany Lin <&iommu M4U_PORT_VENC_SV_COMV>, 14618eb80252STiffany Lin <&iommu M4U_PORT_VENC_RD_COMV>, 14628eb80252STiffany Lin <&iommu M4U_PORT_VENC_CUR_LUMA>, 14638eb80252STiffany Lin <&iommu M4U_PORT_VENC_CUR_CHROMA>, 14648eb80252STiffany Lin <&iommu M4U_PORT_VENC_REF_LUMA>, 14658eb80252STiffany Lin <&iommu M4U_PORT_VENC_REF_CHROMA>, 14668eb80252STiffany Lin <&iommu M4U_PORT_VENC_NBM_RDMA>, 1467e6f73028SIrui Wang <&iommu M4U_PORT_VENC_NBM_WDMA>; 14688eb80252STiffany Lin mediatek,vpu = <&vpu>; 1469e6f73028SIrui Wang clocks = <&topckgen CLK_TOP_VENC_SEL>; 1470e6f73028SIrui Wang clock-names = "venc_sel"; 1471e6f73028SIrui Wang assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; 1472e6f73028SIrui Wang assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>; 1473*dab2782bSAllen-KH Cheng power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 14748eb80252STiffany Lin }; 14758eb80252STiffany Lin 14761180beb0SHsin-Yi Wang jpegdec: jpegdec@18004000 { 14771180beb0SHsin-Yi Wang compatible = "mediatek,mt8173-jpgdec"; 14781180beb0SHsin-Yi Wang reg = <0 0x18004000 0 0x1000>; 14791180beb0SHsin-Yi Wang interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW>; 14801180beb0SHsin-Yi Wang clocks = <&vencsys CLK_VENC_CKE0>, 14811180beb0SHsin-Yi Wang <&vencsys CLK_VENC_CKE3>; 14821180beb0SHsin-Yi Wang clock-names = "jpgdec-smi", 14831180beb0SHsin-Yi Wang "jpgdec"; 14848b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_VENC>; 14851180beb0SHsin-Yi Wang iommus = <&iommu M4U_PORT_JPGDEC_WDMA>, 14861180beb0SHsin-Yi Wang <&iommu M4U_PORT_JPGDEC_BSDMA>; 14871180beb0SHsin-Yi Wang }; 14881180beb0SHsin-Yi Wang 148967e56c56SJames Liao vencltsys: clock-controller@19000000 { 149067e56c56SJames Liao compatible = "mediatek,mt8173-vencltsys", "syscon"; 149167e56c56SJames Liao reg = <0 0x19000000 0 0x1000>; 149267e56c56SJames Liao #clock-cells = <1>; 149367e56c56SJames Liao }; 14945ff6b3a6SYong Wu 14955ff6b3a6SYong Wu larb5: larb@19001000 { 14965ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 14975ff6b3a6SYong Wu reg = <0 0x19001000 0 0x1000>; 14985ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 14998b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>; 15005ff6b3a6SYong Wu clocks = <&vencltsys CLK_VENCLT_CKE1>, 15015ff6b3a6SYong Wu <&vencltsys CLK_VENCLT_CKE0>; 15025ff6b3a6SYong Wu clock-names = "apb", "smi"; 15035ff6b3a6SYong Wu }; 1504e6f73028SIrui Wang 1505e6f73028SIrui Wang vcodec_enc_vp8: vcodec@19002000 { 1506e6f73028SIrui Wang compatible = "mediatek,mt8173-vcodec-enc-vp8"; 1507e6f73028SIrui Wang reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ 1508e6f73028SIrui Wang interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; 1509e6f73028SIrui Wang iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>, 1510e6f73028SIrui Wang <&iommu M4U_PORT_VENC_REC_FRM_SET2>, 1511e6f73028SIrui Wang <&iommu M4U_PORT_VENC_BSDMA_SET2>, 1512e6f73028SIrui Wang <&iommu M4U_PORT_VENC_SV_COMA_SET2>, 1513e6f73028SIrui Wang <&iommu M4U_PORT_VENC_RD_COMA_SET2>, 1514e6f73028SIrui Wang <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, 1515e6f73028SIrui Wang <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, 1516e6f73028SIrui Wang <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, 1517e6f73028SIrui Wang <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; 1518e6f73028SIrui Wang mediatek,vpu = <&vpu>; 1519e6f73028SIrui Wang clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; 1520e6f73028SIrui Wang clock-names = "venc_lt_sel"; 1521e6f73028SIrui Wang assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; 1522e6f73028SIrui Wang assigned-clock-parents = 1523e6f73028SIrui Wang <&topckgen CLK_TOP_VCODECPLL_370P5>; 1524*dab2782bSAllen-KH Cheng power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; 1525e6f73028SIrui Wang }; 1526b3a37248SEddie Huang }; 1527b3a37248SEddie Huang}; 1528