1b3a37248SEddie Huang/* 2b3a37248SEddie Huang * Copyright (c) 2014 MediaTek Inc. 3b3a37248SEddie Huang * Author: Eddie Huang <eddie.huang@mediatek.com> 4b3a37248SEddie Huang * 5b3a37248SEddie Huang * This program is free software; you can redistribute it and/or modify 6b3a37248SEddie Huang * it under the terms of the GNU General Public License version 2 as 7b3a37248SEddie Huang * published by the Free Software Foundation. 8b3a37248SEddie Huang * 9b3a37248SEddie Huang * This program is distributed in the hope that it will be useful, 10b3a37248SEddie Huang * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11b3a37248SEddie Huang * GNU General Public License for more details. 12b3a37248SEddie Huang */ 13b3a37248SEddie Huang 14f2ce7014SSascha Hauer#include <dt-bindings/clock/mt8173-clk.h> 15b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/irq.h> 16b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/arm-gic.h> 175ff6b3a6SYong Wu#include <dt-bindings/memory/mt8173-larb-port.h> 18bfcce47aSChunfeng Yun#include <dt-bindings/phy/phy.h> 19c02e0e86SKoro Chen#include <dt-bindings/power/mt8173-power.h> 20967313e2SPhilipp Zabel#include <dt-bindings/reset/mt8173-resets.h> 21359f9365SHongzhou Yang#include "mt8173-pinfunc.h" 22b3a37248SEddie Huang 23b3a37248SEddie Huang/ { 24b3a37248SEddie Huang compatible = "mediatek,mt8173"; 25b3a37248SEddie Huang interrupt-parent = <&sysirq>; 26b3a37248SEddie Huang #address-cells = <2>; 27b3a37248SEddie Huang #size-cells = <2>; 28b3a37248SEddie Huang 2981ad4dbaSCK Hu aliases { 3081ad4dbaSCK Hu ovl0 = &ovl0; 3181ad4dbaSCK Hu ovl1 = &ovl1; 3281ad4dbaSCK Hu rdma0 = &rdma0; 3381ad4dbaSCK Hu rdma1 = &rdma1; 3481ad4dbaSCK Hu rdma2 = &rdma2; 3581ad4dbaSCK Hu wdma0 = &wdma0; 3681ad4dbaSCK Hu wdma1 = &wdma1; 3781ad4dbaSCK Hu color0 = &color0; 3881ad4dbaSCK Hu color1 = &color1; 3981ad4dbaSCK Hu split0 = &split0; 4081ad4dbaSCK Hu split1 = &split1; 4181ad4dbaSCK Hu dpi0 = &dpi0; 4281ad4dbaSCK Hu dsi0 = &dsi0; 4381ad4dbaSCK Hu dsi1 = &dsi1; 44989b292aSMinghsiu Tsai mdp_rdma0 = &mdp_rdma0; 45989b292aSMinghsiu Tsai mdp_rdma1 = &mdp_rdma1; 46989b292aSMinghsiu Tsai mdp_rsz0 = &mdp_rsz0; 47989b292aSMinghsiu Tsai mdp_rsz1 = &mdp_rsz1; 48989b292aSMinghsiu Tsai mdp_rsz2 = &mdp_rsz2; 49989b292aSMinghsiu Tsai mdp_wdma0 = &mdp_wdma0; 50989b292aSMinghsiu Tsai mdp_wrot0 = &mdp_wrot0; 51989b292aSMinghsiu Tsai mdp_wrot1 = &mdp_wrot1; 5281ad4dbaSCK Hu }; 5381ad4dbaSCK Hu 54da85a3afSAndrew-sh Cheng cluster0_opp: opp_table0 { 55da85a3afSAndrew-sh Cheng compatible = "operating-points-v2"; 56da85a3afSAndrew-sh Cheng opp-shared; 57da85a3afSAndrew-sh Cheng opp-507000000 { 58da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <507000000>; 59da85a3afSAndrew-sh Cheng opp-microvolt = <859000>; 60da85a3afSAndrew-sh Cheng }; 61da85a3afSAndrew-sh Cheng opp-702000000 { 62da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <702000000>; 63da85a3afSAndrew-sh Cheng opp-microvolt = <908000>; 64da85a3afSAndrew-sh Cheng }; 65da85a3afSAndrew-sh Cheng opp-1001000000 { 66da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1001000000>; 67da85a3afSAndrew-sh Cheng opp-microvolt = <983000>; 68da85a3afSAndrew-sh Cheng }; 69da85a3afSAndrew-sh Cheng opp-1105000000 { 70da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1105000000>; 71da85a3afSAndrew-sh Cheng opp-microvolt = <1009000>; 72da85a3afSAndrew-sh Cheng }; 73da85a3afSAndrew-sh Cheng opp-1209000000 { 74da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1209000000>; 75da85a3afSAndrew-sh Cheng opp-microvolt = <1034000>; 76da85a3afSAndrew-sh Cheng }; 77da85a3afSAndrew-sh Cheng opp-1300000000 { 78da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1300000000>; 79da85a3afSAndrew-sh Cheng opp-microvolt = <1057000>; 80da85a3afSAndrew-sh Cheng }; 81da85a3afSAndrew-sh Cheng opp-1508000000 { 82da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1508000000>; 83da85a3afSAndrew-sh Cheng opp-microvolt = <1109000>; 84da85a3afSAndrew-sh Cheng }; 85da85a3afSAndrew-sh Cheng opp-1703000000 { 86da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1703000000>; 87da85a3afSAndrew-sh Cheng opp-microvolt = <1125000>; 88da85a3afSAndrew-sh Cheng }; 89da85a3afSAndrew-sh Cheng }; 90da85a3afSAndrew-sh Cheng 91da85a3afSAndrew-sh Cheng cluster1_opp: opp_table1 { 92da85a3afSAndrew-sh Cheng compatible = "operating-points-v2"; 93da85a3afSAndrew-sh Cheng opp-shared; 94da85a3afSAndrew-sh Cheng opp-507000000 { 95da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <507000000>; 96da85a3afSAndrew-sh Cheng opp-microvolt = <828000>; 97da85a3afSAndrew-sh Cheng }; 98da85a3afSAndrew-sh Cheng opp-702000000 { 99da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <702000000>; 100da85a3afSAndrew-sh Cheng opp-microvolt = <867000>; 101da85a3afSAndrew-sh Cheng }; 102da85a3afSAndrew-sh Cheng opp-1001000000 { 103da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1001000000>; 104da85a3afSAndrew-sh Cheng opp-microvolt = <927000>; 105da85a3afSAndrew-sh Cheng }; 106da85a3afSAndrew-sh Cheng opp-1209000000 { 107da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1209000000>; 108da85a3afSAndrew-sh Cheng opp-microvolt = <968000>; 109da85a3afSAndrew-sh Cheng }; 110da85a3afSAndrew-sh Cheng opp-1404000000 { 111da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1404000000>; 112da85a3afSAndrew-sh Cheng opp-microvolt = <1007000>; 113da85a3afSAndrew-sh Cheng }; 114da85a3afSAndrew-sh Cheng opp-1612000000 { 115da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1612000000>; 116da85a3afSAndrew-sh Cheng opp-microvolt = <1049000>; 117da85a3afSAndrew-sh Cheng }; 118da85a3afSAndrew-sh Cheng opp-1807000000 { 119da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1807000000>; 120da85a3afSAndrew-sh Cheng opp-microvolt = <1089000>; 121da85a3afSAndrew-sh Cheng }; 122da85a3afSAndrew-sh Cheng opp-2106000000 { 123da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <2106000000>; 124da85a3afSAndrew-sh Cheng opp-microvolt = <1125000>; 125da85a3afSAndrew-sh Cheng }; 126da85a3afSAndrew-sh Cheng }; 127da85a3afSAndrew-sh Cheng 128b3a37248SEddie Huang cpus { 129b3a37248SEddie Huang #address-cells = <1>; 130b3a37248SEddie Huang #size-cells = <0>; 131b3a37248SEddie Huang 132b3a37248SEddie Huang cpu-map { 133b3a37248SEddie Huang cluster0 { 134b3a37248SEddie Huang core0 { 135b3a37248SEddie Huang cpu = <&cpu0>; 136b3a37248SEddie Huang }; 137b3a37248SEddie Huang core1 { 138b3a37248SEddie Huang cpu = <&cpu1>; 139b3a37248SEddie Huang }; 140b3a37248SEddie Huang }; 141b3a37248SEddie Huang 142b3a37248SEddie Huang cluster1 { 143b3a37248SEddie Huang core0 { 144b3a37248SEddie Huang cpu = <&cpu2>; 145b3a37248SEddie Huang }; 146b3a37248SEddie Huang core1 { 147b3a37248SEddie Huang cpu = <&cpu3>; 148b3a37248SEddie Huang }; 149b3a37248SEddie Huang }; 150b3a37248SEddie Huang }; 151b3a37248SEddie Huang 152b3a37248SEddie Huang cpu0: cpu@0 { 153b3a37248SEddie Huang device_type = "cpu"; 154b3a37248SEddie Huang compatible = "arm,cortex-a53"; 155b3a37248SEddie Huang reg = <0x000>; 156ad4df7a5SHoward Chen enable-method = "psci"; 157ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 158da85a3afSAndrew-sh Cheng clocks = <&infracfg CLK_INFRA_CA53SEL>, 159da85a3afSAndrew-sh Cheng <&apmixedsys CLK_APMIXED_MAINPLL>; 160da85a3afSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 161da85a3afSAndrew-sh Cheng operating-points-v2 = <&cluster0_opp>; 162b3a37248SEddie Huang }; 163b3a37248SEddie Huang 164b3a37248SEddie Huang cpu1: cpu@1 { 165b3a37248SEddie Huang device_type = "cpu"; 166b3a37248SEddie Huang compatible = "arm,cortex-a53"; 167b3a37248SEddie Huang reg = <0x001>; 168b3a37248SEddie Huang enable-method = "psci"; 169ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 170da85a3afSAndrew-sh Cheng clocks = <&infracfg CLK_INFRA_CA53SEL>, 171da85a3afSAndrew-sh Cheng <&apmixedsys CLK_APMIXED_MAINPLL>; 172da85a3afSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 173da85a3afSAndrew-sh Cheng operating-points-v2 = <&cluster0_opp>; 174b3a37248SEddie Huang }; 175b3a37248SEddie Huang 176b3a37248SEddie Huang cpu2: cpu@100 { 177b3a37248SEddie Huang device_type = "cpu"; 178b3a37248SEddie Huang compatible = "arm,cortex-a57"; 179b3a37248SEddie Huang reg = <0x100>; 180b3a37248SEddie Huang enable-method = "psci"; 181ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 182da85a3afSAndrew-sh Cheng clocks = <&infracfg CLK_INFRA_CA57SEL>, 183da85a3afSAndrew-sh Cheng <&apmixedsys CLK_APMIXED_MAINPLL>; 184da85a3afSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 185da85a3afSAndrew-sh Cheng operating-points-v2 = <&cluster1_opp>; 186b3a37248SEddie Huang }; 187b3a37248SEddie Huang 188b3a37248SEddie Huang cpu3: cpu@101 { 189b3a37248SEddie Huang device_type = "cpu"; 190b3a37248SEddie Huang compatible = "arm,cortex-a57"; 191b3a37248SEddie Huang reg = <0x101>; 192b3a37248SEddie Huang enable-method = "psci"; 193ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 194da85a3afSAndrew-sh Cheng clocks = <&infracfg CLK_INFRA_CA57SEL>, 195da85a3afSAndrew-sh Cheng <&apmixedsys CLK_APMIXED_MAINPLL>; 196da85a3afSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 197da85a3afSAndrew-sh Cheng operating-points-v2 = <&cluster1_opp>; 198ad4df7a5SHoward Chen }; 199ad4df7a5SHoward Chen 200ad4df7a5SHoward Chen idle-states { 201a13f18f5SLorenzo Pieralisi entry-method = "psci"; 202ad4df7a5SHoward Chen 203ad4df7a5SHoward Chen CPU_SLEEP_0: cpu-sleep-0 { 204ad4df7a5SHoward Chen compatible = "arm,idle-state"; 205ad4df7a5SHoward Chen local-timer-stop; 206ad4df7a5SHoward Chen entry-latency-us = <639>; 207ad4df7a5SHoward Chen exit-latency-us = <680>; 208ad4df7a5SHoward Chen min-residency-us = <1088>; 209ad4df7a5SHoward Chen arm,psci-suspend-param = <0x0010000>; 210ad4df7a5SHoward Chen }; 211b3a37248SEddie Huang }; 212b3a37248SEddie Huang }; 213b3a37248SEddie Huang 214b3a37248SEddie Huang psci { 21505bdabe7SFan Chen compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 216b3a37248SEddie Huang method = "smc"; 217b3a37248SEddie Huang cpu_suspend = <0x84000001>; 218b3a37248SEddie Huang cpu_off = <0x84000002>; 219b3a37248SEddie Huang cpu_on = <0x84000003>; 220b3a37248SEddie Huang }; 221b3a37248SEddie Huang 222f2ce7014SSascha Hauer clk26m: oscillator@0 { 223f2ce7014SSascha Hauer compatible = "fixed-clock"; 224f2ce7014SSascha Hauer #clock-cells = <0>; 225f2ce7014SSascha Hauer clock-frequency = <26000000>; 226f2ce7014SSascha Hauer clock-output-names = "clk26m"; 227f2ce7014SSascha Hauer }; 228f2ce7014SSascha Hauer 229f2ce7014SSascha Hauer clk32k: oscillator@1 { 230f2ce7014SSascha Hauer compatible = "fixed-clock"; 231f2ce7014SSascha Hauer #clock-cells = <0>; 232f2ce7014SSascha Hauer clock-frequency = <32000>; 233f2ce7014SSascha Hauer clock-output-names = "clk32k"; 234f2ce7014SSascha Hauer }; 235f2ce7014SSascha Hauer 23667e56c56SJames Liao cpum_ck: oscillator@2 { 23767e56c56SJames Liao compatible = "fixed-clock"; 23867e56c56SJames Liao #clock-cells = <0>; 23967e56c56SJames Liao clock-frequency = <0>; 24067e56c56SJames Liao clock-output-names = "cpum_ck"; 24167e56c56SJames Liao }; 24267e56c56SJames Liao 243962f5143Sdawei.chien@mediatek.com thermal-zones { 244962f5143Sdawei.chien@mediatek.com cpu_thermal: cpu_thermal { 245962f5143Sdawei.chien@mediatek.com polling-delay-passive = <1000>; /* milliseconds */ 246962f5143Sdawei.chien@mediatek.com polling-delay = <1000>; /* milliseconds */ 247962f5143Sdawei.chien@mediatek.com 248962f5143Sdawei.chien@mediatek.com thermal-sensors = <&thermal>; 249962f5143Sdawei.chien@mediatek.com sustainable-power = <1500>; /* milliwatts */ 250962f5143Sdawei.chien@mediatek.com 251962f5143Sdawei.chien@mediatek.com trips { 252962f5143Sdawei.chien@mediatek.com threshold: trip-point@0 { 253962f5143Sdawei.chien@mediatek.com temperature = <68000>; 254962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 255962f5143Sdawei.chien@mediatek.com type = "passive"; 256962f5143Sdawei.chien@mediatek.com }; 257962f5143Sdawei.chien@mediatek.com 258962f5143Sdawei.chien@mediatek.com target: trip-point@1 { 259962f5143Sdawei.chien@mediatek.com temperature = <85000>; 260962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 261962f5143Sdawei.chien@mediatek.com type = "passive"; 262962f5143Sdawei.chien@mediatek.com }; 263962f5143Sdawei.chien@mediatek.com 264962f5143Sdawei.chien@mediatek.com cpu_crit: cpu_crit@0 { 265962f5143Sdawei.chien@mediatek.com temperature = <115000>; 266962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 267962f5143Sdawei.chien@mediatek.com type = "critical"; 268962f5143Sdawei.chien@mediatek.com }; 269962f5143Sdawei.chien@mediatek.com }; 270962f5143Sdawei.chien@mediatek.com 271962f5143Sdawei.chien@mediatek.com cooling-maps { 272962f5143Sdawei.chien@mediatek.com map@0 { 273962f5143Sdawei.chien@mediatek.com trip = <&target>; 274962f5143Sdawei.chien@mediatek.com cooling-device = <&cpu0 0 0>; 2757fcef92dSDaniel Kurtz contribution = <3072>; 276962f5143Sdawei.chien@mediatek.com }; 277962f5143Sdawei.chien@mediatek.com map@1 { 278962f5143Sdawei.chien@mediatek.com trip = <&target>; 279962f5143Sdawei.chien@mediatek.com cooling-device = <&cpu2 0 0>; 2807fcef92dSDaniel Kurtz contribution = <1024>; 281962f5143Sdawei.chien@mediatek.com }; 282962f5143Sdawei.chien@mediatek.com }; 283962f5143Sdawei.chien@mediatek.com }; 284962f5143Sdawei.chien@mediatek.com }; 285962f5143Sdawei.chien@mediatek.com 286404b2819SAndrew-CT Chen reserved-memory { 287404b2819SAndrew-CT Chen #address-cells = <2>; 288404b2819SAndrew-CT Chen #size-cells = <2>; 289404b2819SAndrew-CT Chen ranges; 290404b2819SAndrew-CT Chen vpu_dma_reserved: vpu_dma_mem_region { 291404b2819SAndrew-CT Chen compatible = "shared-dma-pool"; 292404b2819SAndrew-CT Chen reg = <0 0xb7000000 0 0x500000>; 293404b2819SAndrew-CT Chen alignment = <0x1000>; 294404b2819SAndrew-CT Chen no-map; 295404b2819SAndrew-CT Chen }; 296404b2819SAndrew-CT Chen }; 297404b2819SAndrew-CT Chen 298b3a37248SEddie Huang timer { 299b3a37248SEddie Huang compatible = "arm,armv8-timer"; 300b3a37248SEddie Huang interrupt-parent = <&gic>; 301b3a37248SEddie Huang interrupts = <GIC_PPI 13 302b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 303b3a37248SEddie Huang <GIC_PPI 14 304b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 305b3a37248SEddie Huang <GIC_PPI 11 306b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 307b3a37248SEddie Huang <GIC_PPI 10 308b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 309b3a37248SEddie Huang }; 310b3a37248SEddie Huang 311b3a37248SEddie Huang soc { 312b3a37248SEddie Huang #address-cells = <2>; 313b3a37248SEddie Huang #size-cells = <2>; 314b3a37248SEddie Huang compatible = "simple-bus"; 315b3a37248SEddie Huang ranges; 316b3a37248SEddie Huang 317f2ce7014SSascha Hauer topckgen: clock-controller@10000000 { 318f2ce7014SSascha Hauer compatible = "mediatek,mt8173-topckgen"; 319f2ce7014SSascha Hauer reg = <0 0x10000000 0 0x1000>; 320f2ce7014SSascha Hauer #clock-cells = <1>; 321f2ce7014SSascha Hauer }; 322f2ce7014SSascha Hauer 323f2ce7014SSascha Hauer infracfg: power-controller@10001000 { 324f2ce7014SSascha Hauer compatible = "mediatek,mt8173-infracfg", "syscon"; 325f2ce7014SSascha Hauer reg = <0 0x10001000 0 0x1000>; 326f2ce7014SSascha Hauer #clock-cells = <1>; 327f2ce7014SSascha Hauer #reset-cells = <1>; 328f2ce7014SSascha Hauer }; 329f2ce7014SSascha Hauer 330f2ce7014SSascha Hauer pericfg: power-controller@10003000 { 331f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pericfg", "syscon"; 332f2ce7014SSascha Hauer reg = <0 0x10003000 0 0x1000>; 333f2ce7014SSascha Hauer #clock-cells = <1>; 334f2ce7014SSascha Hauer #reset-cells = <1>; 335f2ce7014SSascha Hauer }; 336f2ce7014SSascha Hauer 337f2ce7014SSascha Hauer syscfg_pctl_a: syscfg_pctl_a@10005000 { 338f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 339f2ce7014SSascha Hauer reg = <0 0x10005000 0 0x1000>; 340f2ce7014SSascha Hauer }; 341f2ce7014SSascha Hauer 342f2ce7014SSascha Hauer pio: pinctrl@0x10005000 { 343359f9365SHongzhou Yang compatible = "mediatek,mt8173-pinctrl"; 3446769b93cSYingjoe Chen reg = <0 0x1000b000 0 0x1000>; 345359f9365SHongzhou Yang mediatek,pctl-regmap = <&syscfg_pctl_a>; 346359f9365SHongzhou Yang pins-are-numbered; 347359f9365SHongzhou Yang gpio-controller; 348359f9365SHongzhou Yang #gpio-cells = <2>; 349359f9365SHongzhou Yang interrupt-controller; 350359f9365SHongzhou Yang #interrupt-cells = <2>; 351359f9365SHongzhou Yang interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 352359f9365SHongzhou Yang <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 353359f9365SHongzhou Yang <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 354091cf598SEddie Huang 355a10b57f4SCK Hu hdmi_pin: xxx { 356a10b57f4SCK Hu 357a10b57f4SCK Hu /*hdmi htplg pin*/ 358a10b57f4SCK Hu pins1 { 359a10b57f4SCK Hu pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>; 360a10b57f4SCK Hu input-enable; 361a10b57f4SCK Hu bias-pull-down; 362a10b57f4SCK Hu }; 363a10b57f4SCK Hu }; 364a10b57f4SCK Hu 365091cf598SEddie Huang i2c0_pins_a: i2c0 { 366091cf598SEddie Huang pins1 { 367091cf598SEddie Huang pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 368091cf598SEddie Huang <MT8173_PIN_46_SCL0__FUNC_SCL0>; 369091cf598SEddie Huang bias-disable; 370091cf598SEddie Huang }; 371359f9365SHongzhou Yang }; 372359f9365SHongzhou Yang 373091cf598SEddie Huang i2c1_pins_a: i2c1 { 374091cf598SEddie Huang pins1 { 375091cf598SEddie Huang pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 376091cf598SEddie Huang <MT8173_PIN_126_SCL1__FUNC_SCL1>; 377091cf598SEddie Huang bias-disable; 378091cf598SEddie Huang }; 379091cf598SEddie Huang }; 380091cf598SEddie Huang 381091cf598SEddie Huang i2c2_pins_a: i2c2 { 382091cf598SEddie Huang pins1 { 383091cf598SEddie Huang pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 384091cf598SEddie Huang <MT8173_PIN_44_SCL2__FUNC_SCL2>; 385091cf598SEddie Huang bias-disable; 386091cf598SEddie Huang }; 387091cf598SEddie Huang }; 388091cf598SEddie Huang 389091cf598SEddie Huang i2c3_pins_a: i2c3 { 390091cf598SEddie Huang pins1 { 391091cf598SEddie Huang pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 392091cf598SEddie Huang <MT8173_PIN_107_SCL3__FUNC_SCL3>; 393091cf598SEddie Huang bias-disable; 394091cf598SEddie Huang }; 395091cf598SEddie Huang }; 396091cf598SEddie Huang 397091cf598SEddie Huang i2c4_pins_a: i2c4 { 398091cf598SEddie Huang pins1 { 399091cf598SEddie Huang pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 400091cf598SEddie Huang <MT8173_PIN_134_SCL4__FUNC_SCL4>; 401091cf598SEddie Huang bias-disable; 402091cf598SEddie Huang }; 403091cf598SEddie Huang }; 404091cf598SEddie Huang 405091cf598SEddie Huang i2c6_pins_a: i2c6 { 406091cf598SEddie Huang pins1 { 407091cf598SEddie Huang pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 408091cf598SEddie Huang <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 409091cf598SEddie Huang bias-disable; 410091cf598SEddie Huang }; 411091cf598SEddie Huang }; 4126769b93cSYingjoe Chen }; 4136769b93cSYingjoe Chen 414c010ff53SSascha Hauer scpsys: scpsys@10006000 { 415c010ff53SSascha Hauer compatible = "mediatek,mt8173-scpsys"; 416c010ff53SSascha Hauer #power-domain-cells = <1>; 417c010ff53SSascha Hauer reg = <0 0x10006000 0 0x1000>; 418c010ff53SSascha Hauer clocks = <&clk26m>, 419e34573c9SJames Liao <&topckgen CLK_TOP_MM_SEL>, 420e34573c9SJames Liao <&topckgen CLK_TOP_VENC_SEL>, 421e34573c9SJames Liao <&topckgen CLK_TOP_VENC_LT_SEL>; 422e34573c9SJames Liao clock-names = "mfg", "mm", "venc", "venc_lt"; 423c010ff53SSascha Hauer infracfg = <&infracfg>; 424c010ff53SSascha Hauer }; 425c010ff53SSascha Hauer 42613421b3eSEddie Huang watchdog: watchdog@10007000 { 42713421b3eSEddie Huang compatible = "mediatek,mt8173-wdt", 42813421b3eSEddie Huang "mediatek,mt6589-wdt"; 42913421b3eSEddie Huang reg = <0 0x10007000 0 0x100>; 43013421b3eSEddie Huang }; 43113421b3eSEddie Huang 432b2c76e27SDaniel Kurtz timer: timer@10008000 { 433b2c76e27SDaniel Kurtz compatible = "mediatek,mt8173-timer", 434b2c76e27SDaniel Kurtz "mediatek,mt6577-timer"; 435b2c76e27SDaniel Kurtz reg = <0 0x10008000 0 0x1000>; 436b2c76e27SDaniel Kurtz interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 437b2c76e27SDaniel Kurtz clocks = <&infracfg CLK_INFRA_CLK_13M>, 438b2c76e27SDaniel Kurtz <&topckgen CLK_TOP_RTC_SEL>; 439b2c76e27SDaniel Kurtz }; 440b2c76e27SDaniel Kurtz 4416cf15fc2SSascha Hauer pwrap: pwrap@1000d000 { 4426cf15fc2SSascha Hauer compatible = "mediatek,mt8173-pwrap"; 4436cf15fc2SSascha Hauer reg = <0 0x1000d000 0 0x1000>; 4446cf15fc2SSascha Hauer reg-names = "pwrap"; 4456cf15fc2SSascha Hauer interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 4466cf15fc2SSascha Hauer resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 4476cf15fc2SSascha Hauer reset-names = "pwrap"; 4486cf15fc2SSascha Hauer clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 4496cf15fc2SSascha Hauer clock-names = "spi", "wrap"; 4506cf15fc2SSascha Hauer }; 4516cf15fc2SSascha Hauer 452a10b57f4SCK Hu cec: cec@10013000 { 453a10b57f4SCK Hu compatible = "mediatek,mt8173-cec"; 454a10b57f4SCK Hu reg = <0 0x10013000 0 0xbc>; 455a10b57f4SCK Hu interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; 456a10b57f4SCK Hu clocks = <&infracfg CLK_INFRA_CEC>; 457a10b57f4SCK Hu status = "disabled"; 458a10b57f4SCK Hu }; 459a10b57f4SCK Hu 460404b2819SAndrew-CT Chen vpu: vpu@10020000 { 461404b2819SAndrew-CT Chen compatible = "mediatek,mt8173-vpu"; 462404b2819SAndrew-CT Chen reg = <0 0x10020000 0 0x30000>, 463404b2819SAndrew-CT Chen <0 0x10050000 0 0x100>; 464404b2819SAndrew-CT Chen reg-names = "tcm", "cfg_reg"; 465404b2819SAndrew-CT Chen interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 466404b2819SAndrew-CT Chen clocks = <&topckgen CLK_TOP_SCP_SEL>; 467404b2819SAndrew-CT Chen clock-names = "main"; 468404b2819SAndrew-CT Chen memory-region = <&vpu_dma_reserved>; 469404b2819SAndrew-CT Chen }; 470404b2819SAndrew-CT Chen 471b3a37248SEddie Huang sysirq: intpol-controller@10200620 { 472b3a37248SEddie Huang compatible = "mediatek,mt8173-sysirq", 473b3a37248SEddie Huang "mediatek,mt6577-sysirq"; 474b3a37248SEddie Huang interrupt-controller; 475b3a37248SEddie Huang #interrupt-cells = <3>; 476b3a37248SEddie Huang interrupt-parent = <&gic>; 477b3a37248SEddie Huang reg = <0 0x10200620 0 0x20>; 478b3a37248SEddie Huang }; 479b3a37248SEddie Huang 4805ff6b3a6SYong Wu iommu: iommu@10205000 { 4815ff6b3a6SYong Wu compatible = "mediatek,mt8173-m4u"; 4825ff6b3a6SYong Wu reg = <0 0x10205000 0 0x1000>; 4835ff6b3a6SYong Wu interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 4845ff6b3a6SYong Wu clocks = <&infracfg CLK_INFRA_M4U>; 4855ff6b3a6SYong Wu clock-names = "bclk"; 4865ff6b3a6SYong Wu mediatek,larbs = <&larb0 &larb1 &larb2 4875ff6b3a6SYong Wu &larb3 &larb4 &larb5>; 4885ff6b3a6SYong Wu #iommu-cells = <1>; 4895ff6b3a6SYong Wu }; 4905ff6b3a6SYong Wu 49193e9f5eeSandrew-ct.chen@mediatek.com efuse: efuse@10206000 { 49293e9f5eeSandrew-ct.chen@mediatek.com compatible = "mediatek,mt8173-efuse"; 49393e9f5eeSandrew-ct.chen@mediatek.com reg = <0 0x10206000 0 0x1000>; 4946de18454Sdawei.chien@mediatek.com #address-cells = <1>; 4956de18454Sdawei.chien@mediatek.com #size-cells = <1>; 4966de18454Sdawei.chien@mediatek.com thermal_calibration: calib@528 { 4976de18454Sdawei.chien@mediatek.com reg = <0x528 0xc>; 4986de18454Sdawei.chien@mediatek.com }; 49993e9f5eeSandrew-ct.chen@mediatek.com }; 50093e9f5eeSandrew-ct.chen@mediatek.com 501f2ce7014SSascha Hauer apmixedsys: clock-controller@10209000 { 502f2ce7014SSascha Hauer compatible = "mediatek,mt8173-apmixedsys"; 503f2ce7014SSascha Hauer reg = <0 0x10209000 0 0x1000>; 504f2ce7014SSascha Hauer #clock-cells = <1>; 505f2ce7014SSascha Hauer }; 506f2ce7014SSascha Hauer 507a10b57f4SCK Hu hdmi_phy: hdmi-phy@10209100 { 508a10b57f4SCK Hu compatible = "mediatek,mt8173-hdmi-phy"; 509a10b57f4SCK Hu reg = <0 0x10209100 0 0x24>; 510a10b57f4SCK Hu clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; 511a10b57f4SCK Hu clock-names = "pll_ref"; 512a10b57f4SCK Hu clock-output-names = "hdmitx_dig_cts"; 513a10b57f4SCK Hu mediatek,ibias = <0xa>; 514a10b57f4SCK Hu mediatek,ibias_up = <0x1c>; 515a10b57f4SCK Hu #clock-cells = <0>; 516a10b57f4SCK Hu #phy-cells = <0>; 517a10b57f4SCK Hu status = "disabled"; 518a10b57f4SCK Hu }; 519a10b57f4SCK Hu 52081ad4dbaSCK Hu mipi_tx0: mipi-dphy@10215000 { 52181ad4dbaSCK Hu compatible = "mediatek,mt8173-mipi-tx"; 52281ad4dbaSCK Hu reg = <0 0x10215000 0 0x1000>; 52381ad4dbaSCK Hu clocks = <&clk26m>; 52481ad4dbaSCK Hu clock-output-names = "mipi_tx0_pll"; 52581ad4dbaSCK Hu #clock-cells = <0>; 52681ad4dbaSCK Hu #phy-cells = <0>; 52781ad4dbaSCK Hu status = "disabled"; 52881ad4dbaSCK Hu }; 52981ad4dbaSCK Hu 53081ad4dbaSCK Hu mipi_tx1: mipi-dphy@10216000 { 53181ad4dbaSCK Hu compatible = "mediatek,mt8173-mipi-tx"; 53281ad4dbaSCK Hu reg = <0 0x10216000 0 0x1000>; 53381ad4dbaSCK Hu clocks = <&clk26m>; 53481ad4dbaSCK Hu clock-output-names = "mipi_tx1_pll"; 53581ad4dbaSCK Hu #clock-cells = <0>; 53681ad4dbaSCK Hu #phy-cells = <0>; 53781ad4dbaSCK Hu status = "disabled"; 53881ad4dbaSCK Hu }; 53981ad4dbaSCK Hu 540b3a37248SEddie Huang gic: interrupt-controller@10220000 { 541b3a37248SEddie Huang compatible = "arm,gic-400"; 542b3a37248SEddie Huang #interrupt-cells = <3>; 543b3a37248SEddie Huang interrupt-parent = <&gic>; 544b3a37248SEddie Huang interrupt-controller; 545b3a37248SEddie Huang reg = <0 0x10221000 0 0x1000>, 546b3a37248SEddie Huang <0 0x10222000 0 0x2000>, 547b3a37248SEddie Huang <0 0x10224000 0 0x2000>, 548b3a37248SEddie Huang <0 0x10226000 0 0x2000>; 549b3a37248SEddie Huang interrupts = <GIC_PPI 9 550b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 551b3a37248SEddie Huang }; 552b3a37248SEddie Huang 553748c7d4dSSascha Hauer auxadc: auxadc@11001000 { 554748c7d4dSSascha Hauer compatible = "mediatek,mt8173-auxadc"; 555748c7d4dSSascha Hauer reg = <0 0x11001000 0 0x1000>; 556a3207d64SMatthias Brugger clocks = <&pericfg CLK_PERI_AUXADC>; 557a3207d64SMatthias Brugger clock-names = "main"; 558a3207d64SMatthias Brugger #io-channel-cells = <1>; 559748c7d4dSSascha Hauer }; 560748c7d4dSSascha Hauer 561b3a37248SEddie Huang uart0: serial@11002000 { 562b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 563b3a37248SEddie Huang "mediatek,mt6577-uart"; 564b3a37248SEddie Huang reg = <0 0x11002000 0 0x400>; 565b3a37248SEddie Huang interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 5660e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 5670e84faa1SSascha Hauer clock-names = "baud", "bus"; 568b3a37248SEddie Huang status = "disabled"; 569b3a37248SEddie Huang }; 570b3a37248SEddie Huang 571b3a37248SEddie Huang uart1: serial@11003000 { 572b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 573b3a37248SEddie Huang "mediatek,mt6577-uart"; 574b3a37248SEddie Huang reg = <0 0x11003000 0 0x400>; 575b3a37248SEddie Huang interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 5760e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 5770e84faa1SSascha Hauer clock-names = "baud", "bus"; 578b3a37248SEddie Huang status = "disabled"; 579b3a37248SEddie Huang }; 580b3a37248SEddie Huang 581b3a37248SEddie Huang uart2: serial@11004000 { 582b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 583b3a37248SEddie Huang "mediatek,mt6577-uart"; 584b3a37248SEddie Huang reg = <0 0x11004000 0 0x400>; 585b3a37248SEddie Huang interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 5860e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 5870e84faa1SSascha Hauer clock-names = "baud", "bus"; 588b3a37248SEddie Huang status = "disabled"; 589b3a37248SEddie Huang }; 590b3a37248SEddie Huang 591b3a37248SEddie Huang uart3: serial@11005000 { 592b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 593b3a37248SEddie Huang "mediatek,mt6577-uart"; 594b3a37248SEddie Huang reg = <0 0x11005000 0 0x400>; 595b3a37248SEddie Huang interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 5960e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 5970e84faa1SSascha Hauer clock-names = "baud", "bus"; 598b3a37248SEddie Huang status = "disabled"; 599b3a37248SEddie Huang }; 600091cf598SEddie Huang 601091cf598SEddie Huang i2c0: i2c@11007000 { 602091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 603091cf598SEddie Huang reg = <0 0x11007000 0 0x70>, 604091cf598SEddie Huang <0 0x11000100 0 0x80>; 605091cf598SEddie Huang interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 606091cf598SEddie Huang clock-div = <16>; 607091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C0>, 608091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 609091cf598SEddie Huang clock-names = "main", "dma"; 610091cf598SEddie Huang pinctrl-names = "default"; 611091cf598SEddie Huang pinctrl-0 = <&i2c0_pins_a>; 612091cf598SEddie Huang #address-cells = <1>; 613091cf598SEddie Huang #size-cells = <0>; 614091cf598SEddie Huang status = "disabled"; 615091cf598SEddie Huang }; 616091cf598SEddie Huang 617091cf598SEddie Huang i2c1: i2c@11008000 { 618091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 619091cf598SEddie Huang reg = <0 0x11008000 0 0x70>, 620091cf598SEddie Huang <0 0x11000180 0 0x80>; 621091cf598SEddie Huang interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 622091cf598SEddie Huang clock-div = <16>; 623091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C1>, 624091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 625091cf598SEddie Huang clock-names = "main", "dma"; 626091cf598SEddie Huang pinctrl-names = "default"; 627091cf598SEddie Huang pinctrl-0 = <&i2c1_pins_a>; 628091cf598SEddie Huang #address-cells = <1>; 629091cf598SEddie Huang #size-cells = <0>; 630091cf598SEddie Huang status = "disabled"; 631091cf598SEddie Huang }; 632091cf598SEddie Huang 633091cf598SEddie Huang i2c2: i2c@11009000 { 634091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 635091cf598SEddie Huang reg = <0 0x11009000 0 0x70>, 636091cf598SEddie Huang <0 0x11000200 0 0x80>; 637091cf598SEddie Huang interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 638091cf598SEddie Huang clock-div = <16>; 639091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C2>, 640091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 641091cf598SEddie Huang clock-names = "main", "dma"; 642091cf598SEddie Huang pinctrl-names = "default"; 643091cf598SEddie Huang pinctrl-0 = <&i2c2_pins_a>; 644091cf598SEddie Huang #address-cells = <1>; 645091cf598SEddie Huang #size-cells = <0>; 646091cf598SEddie Huang status = "disabled"; 647091cf598SEddie Huang }; 648091cf598SEddie Huang 649b0c936f5SLeilk Liu spi: spi@1100a000 { 650b0c936f5SLeilk Liu compatible = "mediatek,mt8173-spi"; 651b0c936f5SLeilk Liu #address-cells = <1>; 652b0c936f5SLeilk Liu #size-cells = <0>; 653b0c936f5SLeilk Liu reg = <0 0x1100a000 0 0x1000>; 654b0c936f5SLeilk Liu interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 655b0c936f5SLeilk Liu clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 656b0c936f5SLeilk Liu <&topckgen CLK_TOP_SPI_SEL>, 657b0c936f5SLeilk Liu <&pericfg CLK_PERI_SPI0>; 658b0c936f5SLeilk Liu clock-names = "parent-clk", "sel-clk", "spi-clk"; 659b0c936f5SLeilk Liu status = "disabled"; 660b0c936f5SLeilk Liu }; 661b0c936f5SLeilk Liu 662748c7d4dSSascha Hauer thermal: thermal@1100b000 { 663748c7d4dSSascha Hauer #thermal-sensor-cells = <0>; 664748c7d4dSSascha Hauer compatible = "mediatek,mt8173-thermal"; 665748c7d4dSSascha Hauer reg = <0 0x1100b000 0 0x1000>; 666748c7d4dSSascha Hauer interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 667748c7d4dSSascha Hauer clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 668748c7d4dSSascha Hauer clock-names = "therm", "auxadc"; 669748c7d4dSSascha Hauer resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 670748c7d4dSSascha Hauer mediatek,auxadc = <&auxadc>; 671748c7d4dSSascha Hauer mediatek,apmixedsys = <&apmixedsys>; 6726de18454Sdawei.chien@mediatek.com nvmem-cells = <&thermal_calibration>; 6736de18454Sdawei.chien@mediatek.com nvmem-cell-names = "calibration-data"; 674748c7d4dSSascha Hauer }; 675748c7d4dSSascha Hauer 67686cb8a88SBayi Cheng nor_flash: spi@1100d000 { 67786cb8a88SBayi Cheng compatible = "mediatek,mt8173-nor"; 67886cb8a88SBayi Cheng reg = <0 0x1100d000 0 0xe0>; 67986cb8a88SBayi Cheng clocks = <&pericfg CLK_PERI_SPI>, 68086cb8a88SBayi Cheng <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 68186cb8a88SBayi Cheng clock-names = "spi", "sf"; 68286cb8a88SBayi Cheng #address-cells = <1>; 68386cb8a88SBayi Cheng #size-cells = <0>; 68486cb8a88SBayi Cheng status = "disabled"; 68586cb8a88SBayi Cheng }; 68686cb8a88SBayi Cheng 6871ee35c05SYingjoe Chen i2c3: i2c@11010000 { 688091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 689091cf598SEddie Huang reg = <0 0x11010000 0 0x70>, 690091cf598SEddie Huang <0 0x11000280 0 0x80>; 691091cf598SEddie Huang interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 692091cf598SEddie Huang clock-div = <16>; 693091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C3>, 694091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 695091cf598SEddie Huang clock-names = "main", "dma"; 696091cf598SEddie Huang pinctrl-names = "default"; 697091cf598SEddie Huang pinctrl-0 = <&i2c3_pins_a>; 698091cf598SEddie Huang #address-cells = <1>; 699091cf598SEddie Huang #size-cells = <0>; 700091cf598SEddie Huang status = "disabled"; 701091cf598SEddie Huang }; 702091cf598SEddie Huang 7031ee35c05SYingjoe Chen i2c4: i2c@11011000 { 704091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 705091cf598SEddie Huang reg = <0 0x11011000 0 0x70>, 706091cf598SEddie Huang <0 0x11000300 0 0x80>; 707091cf598SEddie Huang interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 708091cf598SEddie Huang clock-div = <16>; 709091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C4>, 710091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 711091cf598SEddie Huang clock-names = "main", "dma"; 712091cf598SEddie Huang pinctrl-names = "default"; 713091cf598SEddie Huang pinctrl-0 = <&i2c4_pins_a>; 714091cf598SEddie Huang #address-cells = <1>; 715091cf598SEddie Huang #size-cells = <0>; 716091cf598SEddie Huang status = "disabled"; 717091cf598SEddie Huang }; 718091cf598SEddie Huang 719a10b57f4SCK Hu hdmiddc0: i2c@11012000 { 720a10b57f4SCK Hu compatible = "mediatek,mt8173-hdmi-ddc"; 721a10b57f4SCK Hu interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 722a10b57f4SCK Hu reg = <0 0x11012000 0 0x1C>; 723a10b57f4SCK Hu clocks = <&pericfg CLK_PERI_I2C5>; 724a10b57f4SCK Hu clock-names = "ddc-i2c"; 725a10b57f4SCK Hu }; 726a10b57f4SCK Hu 7271ee35c05SYingjoe Chen i2c6: i2c@11013000 { 728091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 729091cf598SEddie Huang reg = <0 0x11013000 0 0x70>, 730091cf598SEddie Huang <0 0x11000080 0 0x80>; 731091cf598SEddie Huang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 732091cf598SEddie Huang clock-div = <16>; 733091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C6>, 734091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 735091cf598SEddie Huang clock-names = "main", "dma"; 736091cf598SEddie Huang pinctrl-names = "default"; 737091cf598SEddie Huang pinctrl-0 = <&i2c6_pins_a>; 738091cf598SEddie Huang #address-cells = <1>; 739091cf598SEddie Huang #size-cells = <0>; 740091cf598SEddie Huang status = "disabled"; 741091cf598SEddie Huang }; 742c02e0e86SKoro Chen 743c02e0e86SKoro Chen afe: audio-controller@11220000 { 744c02e0e86SKoro Chen compatible = "mediatek,mt8173-afe-pcm"; 745c02e0e86SKoro Chen reg = <0 0x11220000 0 0x1000>; 746c02e0e86SKoro Chen interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 747c02e0e86SKoro Chen power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; 748c02e0e86SKoro Chen clocks = <&infracfg CLK_INFRA_AUDIO>, 749c02e0e86SKoro Chen <&topckgen CLK_TOP_AUDIO_SEL>, 750c02e0e86SKoro Chen <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 751c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL1_DIV0>, 752c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL2_DIV0>, 753c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S0_M_SEL>, 754c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S1_M_SEL>, 755c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S2_M_SEL>, 756c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S3_M_SEL>, 757c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S3_B_SEL>; 758c02e0e86SKoro Chen clock-names = "infra_sys_audio_clk", 759c02e0e86SKoro Chen "top_pdn_audio", 760c02e0e86SKoro Chen "top_pdn_aud_intbus", 761c02e0e86SKoro Chen "bck0", 762c02e0e86SKoro Chen "bck1", 763c02e0e86SKoro Chen "i2s0_m", 764c02e0e86SKoro Chen "i2s1_m", 765c02e0e86SKoro Chen "i2s2_m", 766c02e0e86SKoro Chen "i2s3_m", 767c02e0e86SKoro Chen "i2s3_b"; 768c02e0e86SKoro Chen assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 769c02e0e86SKoro Chen <&topckgen CLK_TOP_AUD_2_SEL>; 770c02e0e86SKoro Chen assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 771c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL2>; 772c02e0e86SKoro Chen }; 7739719fa5aSEddie Huang 7749719fa5aSEddie Huang mmc0: mmc@11230000 { 775689362b3SChaotian Jing compatible = "mediatek,mt8173-mmc"; 7769719fa5aSEddie Huang reg = <0 0x11230000 0 0x1000>; 7779719fa5aSEddie Huang interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 7789719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_0>, 7799719fa5aSEddie Huang <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 7809719fa5aSEddie Huang clock-names = "source", "hclk"; 7819719fa5aSEddie Huang status = "disabled"; 7829719fa5aSEddie Huang }; 7839719fa5aSEddie Huang 7849719fa5aSEddie Huang mmc1: mmc@11240000 { 785689362b3SChaotian Jing compatible = "mediatek,mt8173-mmc"; 7869719fa5aSEddie Huang reg = <0 0x11240000 0 0x1000>; 7879719fa5aSEddie Huang interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 7889719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_1>, 7899719fa5aSEddie Huang <&topckgen CLK_TOP_AXI_SEL>; 7909719fa5aSEddie Huang clock-names = "source", "hclk"; 7919719fa5aSEddie Huang status = "disabled"; 7929719fa5aSEddie Huang }; 7939719fa5aSEddie Huang 7949719fa5aSEddie Huang mmc2: mmc@11250000 { 795689362b3SChaotian Jing compatible = "mediatek,mt8173-mmc"; 7969719fa5aSEddie Huang reg = <0 0x11250000 0 0x1000>; 7979719fa5aSEddie Huang interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 7989719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_2>, 7999719fa5aSEddie Huang <&topckgen CLK_TOP_AXI_SEL>; 8009719fa5aSEddie Huang clock-names = "source", "hclk"; 8019719fa5aSEddie Huang status = "disabled"; 8029719fa5aSEddie Huang }; 8039719fa5aSEddie Huang 8049719fa5aSEddie Huang mmc3: mmc@11260000 { 805689362b3SChaotian Jing compatible = "mediatek,mt8173-mmc"; 8069719fa5aSEddie Huang reg = <0 0x11260000 0 0x1000>; 8079719fa5aSEddie Huang interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 8089719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_3>, 8099719fa5aSEddie Huang <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 8109719fa5aSEddie Huang clock-names = "source", "hclk"; 8119719fa5aSEddie Huang status = "disabled"; 8129719fa5aSEddie Huang }; 81367e56c56SJames Liao 814c0891284SChunfeng Yun ssusb: usb@11271000 { 815c0891284SChunfeng Yun compatible = "mediatek,mt8173-mtu3"; 816c0891284SChunfeng Yun reg = <0 0x11271000 0 0x3000>, 817bfcce47aSChunfeng Yun <0 0x11280700 0 0x0100>; 818c0891284SChunfeng Yun reg-names = "mac", "ippc"; 819c0891284SChunfeng Yun interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>; 820ebf61c63Schunfeng.yun@mediatek.com phys = <&u2port0 PHY_TYPE_USB2>, 821ebf61c63Schunfeng.yun@mediatek.com <&u3port0 PHY_TYPE_USB3>, 822ebf61c63Schunfeng.yun@mediatek.com <&u2port1 PHY_TYPE_USB2>; 823bfcce47aSChunfeng Yun power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 824bfcce47aSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>, 825cb6efc7bSChunfeng Yun <&clk26m>, 826bfcce47aSChunfeng Yun <&pericfg CLK_PERI_USB0>, 827bfcce47aSChunfeng Yun <&pericfg CLK_PERI_USB1>; 828bfcce47aSChunfeng Yun clock-names = "sys_ck", 829cb6efc7bSChunfeng Yun "ref_ck", 830bfcce47aSChunfeng Yun "wakeup_deb_p0", 831bfcce47aSChunfeng Yun "wakeup_deb_p1"; 832bfcce47aSChunfeng Yun mediatek,syscon-wakeup = <&pericfg>; 833c0891284SChunfeng Yun #address-cells = <2>; 834c0891284SChunfeng Yun #size-cells = <2>; 835c0891284SChunfeng Yun ranges; 836c0891284SChunfeng Yun status = "disabled"; 837c0891284SChunfeng Yun 838c0891284SChunfeng Yun usb_host: xhci@11270000 { 839c0891284SChunfeng Yun compatible = "mediatek,mt8173-xhci"; 840c0891284SChunfeng Yun reg = <0 0x11270000 0 0x1000>; 841c0891284SChunfeng Yun reg-names = "mac"; 842c0891284SChunfeng Yun interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 843c0891284SChunfeng Yun power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 844cb6efc7bSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 845cb6efc7bSChunfeng Yun clock-names = "sys_ck", "ref_ck"; 846c0891284SChunfeng Yun status = "disabled"; 847c0891284SChunfeng Yun }; 848bfcce47aSChunfeng Yun }; 849bfcce47aSChunfeng Yun 850bfcce47aSChunfeng Yun u3phy: usb-phy@11290000 { 851bfcce47aSChunfeng Yun compatible = "mediatek,mt8173-u3phy"; 852bfcce47aSChunfeng Yun reg = <0 0x11290000 0 0x800>; 853bfcce47aSChunfeng Yun #address-cells = <2>; 854bfcce47aSChunfeng Yun #size-cells = <2>; 855bfcce47aSChunfeng Yun ranges; 856bfcce47aSChunfeng Yun status = "okay"; 857bfcce47aSChunfeng Yun 858ebf61c63Schunfeng.yun@mediatek.com u2port0: usb-phy@11290800 { 859ebf61c63Schunfeng.yun@mediatek.com reg = <0 0x11290800 0 0x100>; 86010f84a7aSchunfeng.yun@mediatek.com clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 86110f84a7aSchunfeng.yun@mediatek.com clock-names = "ref"; 862bfcce47aSChunfeng Yun #phy-cells = <1>; 863bfcce47aSChunfeng Yun status = "okay"; 864bfcce47aSChunfeng Yun }; 865bfcce47aSChunfeng Yun 866ebf61c63Schunfeng.yun@mediatek.com u3port0: usb-phy@11290900 { 867ebf61c63Schunfeng.yun@mediatek.com reg = <0 0x11290900 0 0x700>; 86810f84a7aSchunfeng.yun@mediatek.com clocks = <&clk26m>; 86910f84a7aSchunfeng.yun@mediatek.com clock-names = "ref"; 870ebf61c63Schunfeng.yun@mediatek.com #phy-cells = <1>; 871ebf61c63Schunfeng.yun@mediatek.com status = "okay"; 872ebf61c63Schunfeng.yun@mediatek.com }; 873ebf61c63Schunfeng.yun@mediatek.com 874ebf61c63Schunfeng.yun@mediatek.com u2port1: usb-phy@11291000 { 875ebf61c63Schunfeng.yun@mediatek.com reg = <0 0x11291000 0 0x100>; 87610f84a7aSchunfeng.yun@mediatek.com clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 87710f84a7aSchunfeng.yun@mediatek.com clock-names = "ref"; 878bfcce47aSChunfeng Yun #phy-cells = <1>; 879bfcce47aSChunfeng Yun status = "okay"; 880bfcce47aSChunfeng Yun }; 881bfcce47aSChunfeng Yun }; 882bfcce47aSChunfeng Yun 88367e56c56SJames Liao mmsys: clock-controller@14000000 { 88467e56c56SJames Liao compatible = "mediatek,mt8173-mmsys", "syscon"; 88567e56c56SJames Liao reg = <0 0x14000000 0 0x1000>; 88681ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 887fc6634acSBibby Hsieh assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; 888fc6634acSBibby Hsieh assigned-clock-rates = <400000000>; 88967e56c56SJames Liao #clock-cells = <1>; 89067e56c56SJames Liao }; 89167e56c56SJames Liao 892989b292aSMinghsiu Tsai mdp_rdma0: rdma@14001000 { 8938127881fSDaniel Kurtz compatible = "mediatek,mt8173-mdp-rdma", 8948127881fSDaniel Kurtz "mediatek,mt8173-mdp"; 895989b292aSMinghsiu Tsai reg = <0 0x14001000 0 0x1000>; 896989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RDMA0>, 897989b292aSMinghsiu Tsai <&mmsys CLK_MM_MUTEX_32K>; 898989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 899989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_RDMA0>; 900989b292aSMinghsiu Tsai mediatek,larb = <&larb0>; 9018127881fSDaniel Kurtz mediatek,vpu = <&vpu>; 902989b292aSMinghsiu Tsai }; 903989b292aSMinghsiu Tsai 904989b292aSMinghsiu Tsai mdp_rdma1: rdma@14002000 { 905989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rdma"; 906989b292aSMinghsiu Tsai reg = <0 0x14002000 0 0x1000>; 907989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RDMA1>, 908989b292aSMinghsiu Tsai <&mmsys CLK_MM_MUTEX_32K>; 909989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 910989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_RDMA1>; 911989b292aSMinghsiu Tsai mediatek,larb = <&larb4>; 912989b292aSMinghsiu Tsai }; 913989b292aSMinghsiu Tsai 914989b292aSMinghsiu Tsai mdp_rsz0: rsz@14003000 { 915989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rsz"; 916989b292aSMinghsiu Tsai reg = <0 0x14003000 0 0x1000>; 917989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RSZ0>; 918989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 919989b292aSMinghsiu Tsai }; 920989b292aSMinghsiu Tsai 921989b292aSMinghsiu Tsai mdp_rsz1: rsz@14004000 { 922989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rsz"; 923989b292aSMinghsiu Tsai reg = <0 0x14004000 0 0x1000>; 924989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RSZ1>; 925989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 926989b292aSMinghsiu Tsai }; 927989b292aSMinghsiu Tsai 928989b292aSMinghsiu Tsai mdp_rsz2: rsz@14005000 { 929989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rsz"; 930989b292aSMinghsiu Tsai reg = <0 0x14005000 0 0x1000>; 931989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RSZ2>; 932989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 933989b292aSMinghsiu Tsai }; 934989b292aSMinghsiu Tsai 935989b292aSMinghsiu Tsai mdp_wdma0: wdma@14006000 { 936989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-wdma"; 937989b292aSMinghsiu Tsai reg = <0 0x14006000 0 0x1000>; 938989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_WDMA>; 939989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 940989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_WDMA>; 941989b292aSMinghsiu Tsai mediatek,larb = <&larb0>; 942989b292aSMinghsiu Tsai }; 943989b292aSMinghsiu Tsai 944989b292aSMinghsiu Tsai mdp_wrot0: wrot@14007000 { 945989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-wrot"; 946989b292aSMinghsiu Tsai reg = <0 0x14007000 0 0x1000>; 947989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_WROT0>; 948989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 949989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_WROT0>; 950989b292aSMinghsiu Tsai mediatek,larb = <&larb0>; 951989b292aSMinghsiu Tsai }; 952989b292aSMinghsiu Tsai 953989b292aSMinghsiu Tsai mdp_wrot1: wrot@14008000 { 954989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-wrot"; 955989b292aSMinghsiu Tsai reg = <0 0x14008000 0 0x1000>; 956989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_WROT1>; 957989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 958989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_WROT1>; 959989b292aSMinghsiu Tsai mediatek,larb = <&larb4>; 960989b292aSMinghsiu Tsai }; 961989b292aSMinghsiu Tsai 96281ad4dbaSCK Hu ovl0: ovl@1400c000 { 96381ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-ovl"; 96481ad4dbaSCK Hu reg = <0 0x1400c000 0 0x1000>; 96581ad4dbaSCK Hu interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 96681ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 96781ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_OVL0>; 96881ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_OVL0>; 96981ad4dbaSCK Hu mediatek,larb = <&larb0>; 97081ad4dbaSCK Hu }; 97181ad4dbaSCK Hu 97281ad4dbaSCK Hu ovl1: ovl@1400d000 { 97381ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-ovl"; 97481ad4dbaSCK Hu reg = <0 0x1400d000 0 0x1000>; 97581ad4dbaSCK Hu interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; 97681ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 97781ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_OVL1>; 97881ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_OVL1>; 97981ad4dbaSCK Hu mediatek,larb = <&larb4>; 98081ad4dbaSCK Hu }; 98181ad4dbaSCK Hu 98281ad4dbaSCK Hu rdma0: rdma@1400e000 { 98381ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-rdma"; 98481ad4dbaSCK Hu reg = <0 0x1400e000 0 0x1000>; 98581ad4dbaSCK Hu interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 98681ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 98781ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_RDMA0>; 98881ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_RDMA0>; 98981ad4dbaSCK Hu mediatek,larb = <&larb0>; 99081ad4dbaSCK Hu }; 99181ad4dbaSCK Hu 99281ad4dbaSCK Hu rdma1: rdma@1400f000 { 99381ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-rdma"; 99481ad4dbaSCK Hu reg = <0 0x1400f000 0 0x1000>; 99581ad4dbaSCK Hu interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; 99681ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 99781ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_RDMA1>; 99881ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_RDMA1>; 99981ad4dbaSCK Hu mediatek,larb = <&larb4>; 100081ad4dbaSCK Hu }; 100181ad4dbaSCK Hu 100281ad4dbaSCK Hu rdma2: rdma@14010000 { 100381ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-rdma"; 100481ad4dbaSCK Hu reg = <0 0x14010000 0 0x1000>; 100581ad4dbaSCK Hu interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; 100681ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 100781ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_RDMA2>; 100881ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_RDMA2>; 100981ad4dbaSCK Hu mediatek,larb = <&larb4>; 101081ad4dbaSCK Hu }; 101181ad4dbaSCK Hu 101281ad4dbaSCK Hu wdma0: wdma@14011000 { 101381ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-wdma"; 101481ad4dbaSCK Hu reg = <0 0x14011000 0 0x1000>; 101581ad4dbaSCK Hu interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 101681ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 101781ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_WDMA0>; 101881ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_WDMA0>; 101981ad4dbaSCK Hu mediatek,larb = <&larb0>; 102081ad4dbaSCK Hu }; 102181ad4dbaSCK Hu 102281ad4dbaSCK Hu wdma1: wdma@14012000 { 102381ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-wdma"; 102481ad4dbaSCK Hu reg = <0 0x14012000 0 0x1000>; 102581ad4dbaSCK Hu interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; 102681ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 102781ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_WDMA1>; 102881ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_WDMA1>; 102981ad4dbaSCK Hu mediatek,larb = <&larb4>; 103081ad4dbaSCK Hu }; 103181ad4dbaSCK Hu 103281ad4dbaSCK Hu color0: color@14013000 { 103381ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-color"; 103481ad4dbaSCK Hu reg = <0 0x14013000 0 0x1000>; 103581ad4dbaSCK Hu interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; 103681ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 103781ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_COLOR0>; 103881ad4dbaSCK Hu }; 103981ad4dbaSCK Hu 104081ad4dbaSCK Hu color1: color@14014000 { 104181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-color"; 104281ad4dbaSCK Hu reg = <0 0x14014000 0 0x1000>; 104381ad4dbaSCK Hu interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 104481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 104581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_COLOR1>; 104681ad4dbaSCK Hu }; 104781ad4dbaSCK Hu 104881ad4dbaSCK Hu aal@14015000 { 104981ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-aal"; 105081ad4dbaSCK Hu reg = <0 0x14015000 0 0x1000>; 105181ad4dbaSCK Hu interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 105281ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 105381ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_AAL>; 105481ad4dbaSCK Hu }; 105581ad4dbaSCK Hu 105681ad4dbaSCK Hu gamma@14016000 { 105781ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-gamma"; 105881ad4dbaSCK Hu reg = <0 0x14016000 0 0x1000>; 105981ad4dbaSCK Hu interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 106081ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 106181ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_GAMMA>; 106281ad4dbaSCK Hu }; 106381ad4dbaSCK Hu 106481ad4dbaSCK Hu merge@14017000 { 106581ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-merge"; 106681ad4dbaSCK Hu reg = <0 0x14017000 0 0x1000>; 106781ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 106881ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_MERGE>; 106981ad4dbaSCK Hu }; 107081ad4dbaSCK Hu 107181ad4dbaSCK Hu split0: split@14018000 { 107281ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-split"; 107381ad4dbaSCK Hu reg = <0 0x14018000 0 0x1000>; 107481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 107581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_SPLIT0>; 107681ad4dbaSCK Hu }; 107781ad4dbaSCK Hu 107881ad4dbaSCK Hu split1: split@14019000 { 107981ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-split"; 108081ad4dbaSCK Hu reg = <0 0x14019000 0 0x1000>; 108181ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 108281ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_SPLIT1>; 108381ad4dbaSCK Hu }; 108481ad4dbaSCK Hu 108581ad4dbaSCK Hu ufoe@1401a000 { 108681ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-ufoe"; 108781ad4dbaSCK Hu reg = <0 0x1401a000 0 0x1000>; 108881ad4dbaSCK Hu interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 108981ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 109081ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_UFOE>; 109181ad4dbaSCK Hu }; 109281ad4dbaSCK Hu 109381ad4dbaSCK Hu dsi0: dsi@1401b000 { 109481ad4dbaSCK Hu compatible = "mediatek,mt8173-dsi"; 109581ad4dbaSCK Hu reg = <0 0x1401b000 0 0x1000>; 109681ad4dbaSCK Hu interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 109781ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 109881ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DSI0_ENGINE>, 109981ad4dbaSCK Hu <&mmsys CLK_MM_DSI0_DIGITAL>, 110081ad4dbaSCK Hu <&mipi_tx0>; 110181ad4dbaSCK Hu clock-names = "engine", "digital", "hs"; 110281ad4dbaSCK Hu phys = <&mipi_tx0>; 110381ad4dbaSCK Hu phy-names = "dphy"; 110481ad4dbaSCK Hu status = "disabled"; 110581ad4dbaSCK Hu }; 110681ad4dbaSCK Hu 110781ad4dbaSCK Hu dsi1: dsi@1401c000 { 110881ad4dbaSCK Hu compatible = "mediatek,mt8173-dsi"; 110981ad4dbaSCK Hu reg = <0 0x1401c000 0 0x1000>; 111081ad4dbaSCK Hu interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 111181ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 111281ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DSI1_ENGINE>, 111381ad4dbaSCK Hu <&mmsys CLK_MM_DSI1_DIGITAL>, 111481ad4dbaSCK Hu <&mipi_tx1>; 111581ad4dbaSCK Hu clock-names = "engine", "digital", "hs"; 111681ad4dbaSCK Hu phy = <&mipi_tx1>; 111781ad4dbaSCK Hu phy-names = "dphy"; 111881ad4dbaSCK Hu status = "disabled"; 111981ad4dbaSCK Hu }; 112081ad4dbaSCK Hu 112181ad4dbaSCK Hu dpi0: dpi@1401d000 { 112281ad4dbaSCK Hu compatible = "mediatek,mt8173-dpi"; 112381ad4dbaSCK Hu reg = <0 0x1401d000 0 0x1000>; 112481ad4dbaSCK Hu interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 112581ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 112681ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DPI_PIXEL>, 112781ad4dbaSCK Hu <&mmsys CLK_MM_DPI_ENGINE>, 112881ad4dbaSCK Hu <&apmixedsys CLK_APMIXED_TVDPLL>; 112981ad4dbaSCK Hu clock-names = "pixel", "engine", "pll"; 113081ad4dbaSCK Hu status = "disabled"; 1131a10b57f4SCK Hu 1132a10b57f4SCK Hu port { 1133a10b57f4SCK Hu dpi0_out: endpoint { 1134a10b57f4SCK Hu remote-endpoint = <&hdmi0_in>; 1135a10b57f4SCK Hu }; 1136a10b57f4SCK Hu }; 113781ad4dbaSCK Hu }; 113881ad4dbaSCK Hu 113961aee934SYH Huang pwm0: pwm@1401e000 { 114061aee934SYH Huang compatible = "mediatek,mt8173-disp-pwm", 114161aee934SYH Huang "mediatek,mt6595-disp-pwm"; 114261aee934SYH Huang reg = <0 0x1401e000 0 0x1000>; 114361aee934SYH Huang #pwm-cells = <2>; 114461aee934SYH Huang clocks = <&mmsys CLK_MM_DISP_PWM026M>, 114561aee934SYH Huang <&mmsys CLK_MM_DISP_PWM0MM>; 114661aee934SYH Huang clock-names = "main", "mm"; 114761aee934SYH Huang status = "disabled"; 114861aee934SYH Huang }; 114961aee934SYH Huang 115061aee934SYH Huang pwm1: pwm@1401f000 { 115161aee934SYH Huang compatible = "mediatek,mt8173-disp-pwm", 115261aee934SYH Huang "mediatek,mt6595-disp-pwm"; 115361aee934SYH Huang reg = <0 0x1401f000 0 0x1000>; 115461aee934SYH Huang #pwm-cells = <2>; 115561aee934SYH Huang clocks = <&mmsys CLK_MM_DISP_PWM126M>, 115661aee934SYH Huang <&mmsys CLK_MM_DISP_PWM1MM>; 115761aee934SYH Huang clock-names = "main", "mm"; 115861aee934SYH Huang status = "disabled"; 115961aee934SYH Huang }; 116061aee934SYH Huang 116181ad4dbaSCK Hu mutex: mutex@14020000 { 116281ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-mutex"; 116381ad4dbaSCK Hu reg = <0 0x14020000 0 0x1000>; 116481ad4dbaSCK Hu interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 116581ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 116681ad4dbaSCK Hu clocks = <&mmsys CLK_MM_MUTEX_32K>; 116781ad4dbaSCK Hu }; 116881ad4dbaSCK Hu 11695ff6b3a6SYong Wu larb0: larb@14021000 { 11705ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 11715ff6b3a6SYong Wu reg = <0 0x14021000 0 0x1000>; 11725ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 11735ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 11745ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_LARB0>, 11755ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_LARB0>; 11765ff6b3a6SYong Wu clock-names = "apb", "smi"; 11775ff6b3a6SYong Wu }; 11785ff6b3a6SYong Wu 11795ff6b3a6SYong Wu smi_common: smi@14022000 { 11805ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-common"; 11815ff6b3a6SYong Wu reg = <0 0x14022000 0 0x1000>; 11825ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 11835ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_COMMON>, 11845ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_COMMON>; 11855ff6b3a6SYong Wu clock-names = "apb", "smi"; 11865ff6b3a6SYong Wu }; 11875ff6b3a6SYong Wu 118881ad4dbaSCK Hu od@14023000 { 118981ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-od"; 119081ad4dbaSCK Hu reg = <0 0x14023000 0 0x1000>; 119181ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_OD>; 119281ad4dbaSCK Hu }; 119381ad4dbaSCK Hu 1194a10b57f4SCK Hu hdmi0: hdmi@14025000 { 1195a10b57f4SCK Hu compatible = "mediatek,mt8173-hdmi"; 1196a10b57f4SCK Hu reg = <0 0x14025000 0 0x400>; 1197a10b57f4SCK Hu interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>; 1198a10b57f4SCK Hu clocks = <&mmsys CLK_MM_HDMI_PIXEL>, 1199a10b57f4SCK Hu <&mmsys CLK_MM_HDMI_PLLCK>, 1200a10b57f4SCK Hu <&mmsys CLK_MM_HDMI_AUDIO>, 1201a10b57f4SCK Hu <&mmsys CLK_MM_HDMI_SPDIF>; 1202a10b57f4SCK Hu clock-names = "pixel", "pll", "bclk", "spdif"; 1203a10b57f4SCK Hu pinctrl-names = "default"; 1204a10b57f4SCK Hu pinctrl-0 = <&hdmi_pin>; 1205a10b57f4SCK Hu phys = <&hdmi_phy>; 1206a10b57f4SCK Hu phy-names = "hdmi"; 1207a10b57f4SCK Hu mediatek,syscon-hdmi = <&mmsys 0x900>; 1208a10b57f4SCK Hu assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; 1209a10b57f4SCK Hu assigned-clock-parents = <&hdmi_phy>; 1210a10b57f4SCK Hu status = "disabled"; 1211a10b57f4SCK Hu 1212a10b57f4SCK Hu ports { 1213a10b57f4SCK Hu #address-cells = <1>; 1214a10b57f4SCK Hu #size-cells = <0>; 1215a10b57f4SCK Hu 1216a10b57f4SCK Hu port@0 { 1217a10b57f4SCK Hu reg = <0>; 1218a10b57f4SCK Hu 1219a10b57f4SCK Hu hdmi0_in: endpoint { 1220a10b57f4SCK Hu remote-endpoint = <&dpi0_out>; 1221a10b57f4SCK Hu }; 1222a10b57f4SCK Hu }; 1223a10b57f4SCK Hu }; 1224a10b57f4SCK Hu }; 1225a10b57f4SCK Hu 12265ff6b3a6SYong Wu larb4: larb@14027000 { 12275ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 12285ff6b3a6SYong Wu reg = <0 0x14027000 0 0x1000>; 12295ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 12305ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 12315ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_LARB4>, 12325ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_LARB4>; 12335ff6b3a6SYong Wu clock-names = "apb", "smi"; 12345ff6b3a6SYong Wu }; 12355ff6b3a6SYong Wu 123667e56c56SJames Liao imgsys: clock-controller@15000000 { 123767e56c56SJames Liao compatible = "mediatek,mt8173-imgsys", "syscon"; 123867e56c56SJames Liao reg = <0 0x15000000 0 0x1000>; 123967e56c56SJames Liao #clock-cells = <1>; 124067e56c56SJames Liao }; 124167e56c56SJames Liao 12425ff6b3a6SYong Wu larb2: larb@15001000 { 12435ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 12445ff6b3a6SYong Wu reg = <0 0x15001000 0 0x1000>; 12455ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 12465ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>; 12475ff6b3a6SYong Wu clocks = <&imgsys CLK_IMG_LARB2_SMI>, 12485ff6b3a6SYong Wu <&imgsys CLK_IMG_LARB2_SMI>; 12495ff6b3a6SYong Wu clock-names = "apb", "smi"; 12505ff6b3a6SYong Wu }; 12515ff6b3a6SYong Wu 125267e56c56SJames Liao vdecsys: clock-controller@16000000 { 125367e56c56SJames Liao compatible = "mediatek,mt8173-vdecsys", "syscon"; 125467e56c56SJames Liao reg = <0 0x16000000 0 0x1000>; 125567e56c56SJames Liao #clock-cells = <1>; 125667e56c56SJames Liao }; 125767e56c56SJames Liao 125860eaae2bSTiffany Lin vcodec_dec: vcodec@16000000 { 125960eaae2bSTiffany Lin compatible = "mediatek,mt8173-vcodec-dec"; 126060eaae2bSTiffany Lin reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */ 126160eaae2bSTiffany Lin <0 0x16020000 0 0x1000>, /* VDEC_MISC */ 126260eaae2bSTiffany Lin <0 0x16021000 0 0x800>, /* VDEC_LD */ 126360eaae2bSTiffany Lin <0 0x16021800 0 0x800>, /* VDEC_TOP */ 126460eaae2bSTiffany Lin <0 0x16022000 0 0x1000>, /* VDEC_CM */ 126560eaae2bSTiffany Lin <0 0x16023000 0 0x1000>, /* VDEC_AD */ 126660eaae2bSTiffany Lin <0 0x16024000 0 0x1000>, /* VDEC_AV */ 126760eaae2bSTiffany Lin <0 0x16025000 0 0x1000>, /* VDEC_PP */ 126860eaae2bSTiffany Lin <0 0x16026800 0 0x800>, /* VDEC_HWD */ 126960eaae2bSTiffany Lin <0 0x16027000 0 0x800>, /* VDEC_HWQ */ 127060eaae2bSTiffany Lin <0 0x16027800 0 0x800>, /* VDEC_HWB */ 127160eaae2bSTiffany Lin <0 0x16028400 0 0x400>; /* VDEC_HWG */ 127260eaae2bSTiffany Lin interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; 127360eaae2bSTiffany Lin mediatek,larb = <&larb1>; 127460eaae2bSTiffany Lin iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, 127560eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_PP_EXT>, 127660eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, 127760eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, 127860eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, 127960eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, 128060eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, 128160eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; 128260eaae2bSTiffany Lin mediatek,vpu = <&vpu>; 128360eaae2bSTiffany Lin power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 128460eaae2bSTiffany Lin clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, 128560eaae2bSTiffany Lin <&topckgen CLK_TOP_UNIVPLL_D2>, 128660eaae2bSTiffany Lin <&topckgen CLK_TOP_CCI400_SEL>, 128760eaae2bSTiffany Lin <&topckgen CLK_TOP_VDEC_SEL>, 128860eaae2bSTiffany Lin <&topckgen CLK_TOP_VCODECPLL>, 128960eaae2bSTiffany Lin <&apmixedsys CLK_APMIXED_VENCPLL>, 129060eaae2bSTiffany Lin <&topckgen CLK_TOP_VENC_LT_SEL>, 129160eaae2bSTiffany Lin <&topckgen CLK_TOP_VCODECPLL_370P5>; 129260eaae2bSTiffany Lin clock-names = "vcodecpll", 129360eaae2bSTiffany Lin "univpll_d2", 129460eaae2bSTiffany Lin "clk_cci400_sel", 129560eaae2bSTiffany Lin "vdec_sel", 129660eaae2bSTiffany Lin "vdecpll", 129760eaae2bSTiffany Lin "vencpll", 129860eaae2bSTiffany Lin "venc_lt_sel", 129960eaae2bSTiffany Lin "vdec_bus_clk_src"; 130060eaae2bSTiffany Lin }; 130160eaae2bSTiffany Lin 13025ff6b3a6SYong Wu larb1: larb@16010000 { 13035ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 13045ff6b3a6SYong Wu reg = <0 0x16010000 0 0x1000>; 13055ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 13065ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 13075ff6b3a6SYong Wu clocks = <&vdecsys CLK_VDEC_CKEN>, 13085ff6b3a6SYong Wu <&vdecsys CLK_VDEC_LARB_CKEN>; 13095ff6b3a6SYong Wu clock-names = "apb", "smi"; 13105ff6b3a6SYong Wu }; 13115ff6b3a6SYong Wu 131267e56c56SJames Liao vencsys: clock-controller@18000000 { 131367e56c56SJames Liao compatible = "mediatek,mt8173-vencsys", "syscon"; 131467e56c56SJames Liao reg = <0 0x18000000 0 0x1000>; 131567e56c56SJames Liao #clock-cells = <1>; 131667e56c56SJames Liao }; 131767e56c56SJames Liao 13185ff6b3a6SYong Wu larb3: larb@18001000 { 13195ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 13205ff6b3a6SYong Wu reg = <0 0x18001000 0 0x1000>; 13215ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 13225ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 13235ff6b3a6SYong Wu clocks = <&vencsys CLK_VENC_CKE1>, 13245ff6b3a6SYong Wu <&vencsys CLK_VENC_CKE0>; 13255ff6b3a6SYong Wu clock-names = "apb", "smi"; 13265ff6b3a6SYong Wu }; 13275ff6b3a6SYong Wu 13288eb80252STiffany Lin vcodec_enc: vcodec@18002000 { 13298eb80252STiffany Lin compatible = "mediatek,mt8173-vcodec-enc"; 13308eb80252STiffany Lin reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */ 13318eb80252STiffany Lin <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ 13328eb80252STiffany Lin interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>, 13338eb80252STiffany Lin <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; 13348eb80252STiffany Lin mediatek,larb = <&larb3>, 13358eb80252STiffany Lin <&larb5>; 13368eb80252STiffany Lin iommus = <&iommu M4U_PORT_VENC_RCPU>, 13378eb80252STiffany Lin <&iommu M4U_PORT_VENC_REC>, 13388eb80252STiffany Lin <&iommu M4U_PORT_VENC_BSDMA>, 13398eb80252STiffany Lin <&iommu M4U_PORT_VENC_SV_COMV>, 13408eb80252STiffany Lin <&iommu M4U_PORT_VENC_RD_COMV>, 13418eb80252STiffany Lin <&iommu M4U_PORT_VENC_CUR_LUMA>, 13428eb80252STiffany Lin <&iommu M4U_PORT_VENC_CUR_CHROMA>, 13438eb80252STiffany Lin <&iommu M4U_PORT_VENC_REF_LUMA>, 13448eb80252STiffany Lin <&iommu M4U_PORT_VENC_REF_CHROMA>, 13458eb80252STiffany Lin <&iommu M4U_PORT_VENC_NBM_RDMA>, 13468eb80252STiffany Lin <&iommu M4U_PORT_VENC_NBM_WDMA>, 13478eb80252STiffany Lin <&iommu M4U_PORT_VENC_RCPU_SET2>, 13488eb80252STiffany Lin <&iommu M4U_PORT_VENC_REC_FRM_SET2>, 13498eb80252STiffany Lin <&iommu M4U_PORT_VENC_BSDMA_SET2>, 13508eb80252STiffany Lin <&iommu M4U_PORT_VENC_SV_COMA_SET2>, 13518eb80252STiffany Lin <&iommu M4U_PORT_VENC_RD_COMA_SET2>, 13528eb80252STiffany Lin <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, 13538eb80252STiffany Lin <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, 13548eb80252STiffany Lin <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, 13558eb80252STiffany Lin <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; 13568eb80252STiffany Lin mediatek,vpu = <&vpu>; 13578eb80252STiffany Lin clocks = <&topckgen CLK_TOP_VENCPLL_D2>, 13588eb80252STiffany Lin <&topckgen CLK_TOP_VENC_SEL>, 13598eb80252STiffany Lin <&topckgen CLK_TOP_UNIVPLL1_D2>, 13608eb80252STiffany Lin <&topckgen CLK_TOP_VENC_LT_SEL>; 13618eb80252STiffany Lin clock-names = "venc_sel_src", 13628eb80252STiffany Lin "venc_sel", 13638eb80252STiffany Lin "venc_lt_sel_src", 13648eb80252STiffany Lin "venc_lt_sel"; 13658eb80252STiffany Lin }; 13668eb80252STiffany Lin 136767e56c56SJames Liao vencltsys: clock-controller@19000000 { 136867e56c56SJames Liao compatible = "mediatek,mt8173-vencltsys", "syscon"; 136967e56c56SJames Liao reg = <0 0x19000000 0 0x1000>; 137067e56c56SJames Liao #clock-cells = <1>; 137167e56c56SJames Liao }; 13725ff6b3a6SYong Wu 13735ff6b3a6SYong Wu larb5: larb@19001000 { 13745ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 13755ff6b3a6SYong Wu reg = <0 0x19001000 0 0x1000>; 13765ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 13775ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; 13785ff6b3a6SYong Wu clocks = <&vencltsys CLK_VENCLT_CKE1>, 13795ff6b3a6SYong Wu <&vencltsys CLK_VENCLT_CKE0>; 13805ff6b3a6SYong Wu clock-names = "apb", "smi"; 13815ff6b3a6SYong Wu }; 1382b3a37248SEddie Huang }; 1383b3a37248SEddie Huang}; 1384b3a37248SEddie Huang 1385