194c0ded7SThomas Gleixner// SPDX-License-Identifier: GPL-2.0-only 2b3a37248SEddie Huang/* 3b3a37248SEddie Huang * Copyright (c) 2014 MediaTek Inc. 4b3a37248SEddie Huang * Author: Eddie Huang <eddie.huang@mediatek.com> 5b3a37248SEddie Huang */ 6b3a37248SEddie Huang 7f2ce7014SSascha Hauer#include <dt-bindings/clock/mt8173-clk.h> 8b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/irq.h> 9b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/arm-gic.h> 105ff6b3a6SYong Wu#include <dt-bindings/memory/mt8173-larb-port.h> 11bfcce47aSChunfeng Yun#include <dt-bindings/phy/phy.h> 12c02e0e86SKoro Chen#include <dt-bindings/power/mt8173-power.h> 13967313e2SPhilipp Zabel#include <dt-bindings/reset/mt8173-resets.h> 14c2e66b8fSHoulong Wei#include <dt-bindings/gce/mt8173-gce.h> 1526af2884SMichael Kao#include <dt-bindings/thermal/thermal.h> 16359f9365SHongzhou Yang#include "mt8173-pinfunc.h" 17b3a37248SEddie Huang 18b3a37248SEddie Huang/ { 19b3a37248SEddie Huang compatible = "mediatek,mt8173"; 20b3a37248SEddie Huang interrupt-parent = <&sysirq>; 21b3a37248SEddie Huang #address-cells = <2>; 22b3a37248SEddie Huang #size-cells = <2>; 23b3a37248SEddie Huang 2481ad4dbaSCK Hu aliases { 2581ad4dbaSCK Hu ovl0 = &ovl0; 2681ad4dbaSCK Hu ovl1 = &ovl1; 2781ad4dbaSCK Hu rdma0 = &rdma0; 2881ad4dbaSCK Hu rdma1 = &rdma1; 2981ad4dbaSCK Hu rdma2 = &rdma2; 3081ad4dbaSCK Hu wdma0 = &wdma0; 3181ad4dbaSCK Hu wdma1 = &wdma1; 3281ad4dbaSCK Hu color0 = &color0; 3381ad4dbaSCK Hu color1 = &color1; 3481ad4dbaSCK Hu split0 = &split0; 3581ad4dbaSCK Hu split1 = &split1; 3681ad4dbaSCK Hu dpi0 = &dpi0; 3781ad4dbaSCK Hu dsi0 = &dsi0; 3881ad4dbaSCK Hu dsi1 = &dsi1; 39fff12573SHsin-Yi Wang mdp-rdma0 = &mdp_rdma0; 40fff12573SHsin-Yi Wang mdp-rdma1 = &mdp_rdma1; 41fff12573SHsin-Yi Wang mdp-rsz0 = &mdp_rsz0; 42fff12573SHsin-Yi Wang mdp-rsz1 = &mdp_rsz1; 43fff12573SHsin-Yi Wang mdp-rsz2 = &mdp_rsz2; 44fff12573SHsin-Yi Wang mdp-wdma0 = &mdp_wdma0; 45fff12573SHsin-Yi Wang mdp-wrot0 = &mdp_wrot0; 46fff12573SHsin-Yi Wang mdp-wrot1 = &mdp_wrot1; 470f5da28eSHsin-Yi Wang serial0 = &uart0; 480f5da28eSHsin-Yi Wang serial1 = &uart1; 490f5da28eSHsin-Yi Wang serial2 = &uart2; 500f5da28eSHsin-Yi Wang serial3 = &uart3; 5181ad4dbaSCK Hu }; 5281ad4dbaSCK Hu 536f117db4SKrzysztof Kozlowski cluster0_opp: opp-table-0 { 54da85a3afSAndrew-sh Cheng compatible = "operating-points-v2"; 55da85a3afSAndrew-sh Cheng opp-shared; 56da85a3afSAndrew-sh Cheng opp-507000000 { 57da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <507000000>; 58da85a3afSAndrew-sh Cheng opp-microvolt = <859000>; 59da85a3afSAndrew-sh Cheng }; 60da85a3afSAndrew-sh Cheng opp-702000000 { 61da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <702000000>; 62da85a3afSAndrew-sh Cheng opp-microvolt = <908000>; 63da85a3afSAndrew-sh Cheng }; 64da85a3afSAndrew-sh Cheng opp-1001000000 { 65da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1001000000>; 66da85a3afSAndrew-sh Cheng opp-microvolt = <983000>; 67da85a3afSAndrew-sh Cheng }; 68da85a3afSAndrew-sh Cheng opp-1105000000 { 69da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1105000000>; 70da85a3afSAndrew-sh Cheng opp-microvolt = <1009000>; 71da85a3afSAndrew-sh Cheng }; 72da85a3afSAndrew-sh Cheng opp-1209000000 { 73da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1209000000>; 74da85a3afSAndrew-sh Cheng opp-microvolt = <1034000>; 75da85a3afSAndrew-sh Cheng }; 76da85a3afSAndrew-sh Cheng opp-1300000000 { 77da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1300000000>; 78da85a3afSAndrew-sh Cheng opp-microvolt = <1057000>; 79da85a3afSAndrew-sh Cheng }; 80da85a3afSAndrew-sh Cheng opp-1508000000 { 81da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1508000000>; 82da85a3afSAndrew-sh Cheng opp-microvolt = <1109000>; 83da85a3afSAndrew-sh Cheng }; 84da85a3afSAndrew-sh Cheng opp-1703000000 { 85da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1703000000>; 86da85a3afSAndrew-sh Cheng opp-microvolt = <1125000>; 87da85a3afSAndrew-sh Cheng }; 88da85a3afSAndrew-sh Cheng }; 89da85a3afSAndrew-sh Cheng 906f117db4SKrzysztof Kozlowski cluster1_opp: opp-table-1 { 91da85a3afSAndrew-sh Cheng compatible = "operating-points-v2"; 92da85a3afSAndrew-sh Cheng opp-shared; 93da85a3afSAndrew-sh Cheng opp-507000000 { 94da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <507000000>; 95da85a3afSAndrew-sh Cheng opp-microvolt = <828000>; 96da85a3afSAndrew-sh Cheng }; 97da85a3afSAndrew-sh Cheng opp-702000000 { 98da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <702000000>; 99da85a3afSAndrew-sh Cheng opp-microvolt = <867000>; 100da85a3afSAndrew-sh Cheng }; 101da85a3afSAndrew-sh Cheng opp-1001000000 { 102da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1001000000>; 103da85a3afSAndrew-sh Cheng opp-microvolt = <927000>; 104da85a3afSAndrew-sh Cheng }; 105da85a3afSAndrew-sh Cheng opp-1209000000 { 106da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1209000000>; 107da85a3afSAndrew-sh Cheng opp-microvolt = <968000>; 108da85a3afSAndrew-sh Cheng }; 109da85a3afSAndrew-sh Cheng opp-1404000000 { 110da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1404000000>; 111da85a3afSAndrew-sh Cheng opp-microvolt = <1007000>; 112da85a3afSAndrew-sh Cheng }; 113da85a3afSAndrew-sh Cheng opp-1612000000 { 114da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1612000000>; 115da85a3afSAndrew-sh Cheng opp-microvolt = <1049000>; 116da85a3afSAndrew-sh Cheng }; 117da85a3afSAndrew-sh Cheng opp-1807000000 { 118da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1807000000>; 119da85a3afSAndrew-sh Cheng opp-microvolt = <1089000>; 120da85a3afSAndrew-sh Cheng }; 121da85a3afSAndrew-sh Cheng opp-2106000000 { 122da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <2106000000>; 123da85a3afSAndrew-sh Cheng opp-microvolt = <1125000>; 124da85a3afSAndrew-sh Cheng }; 125da85a3afSAndrew-sh Cheng }; 126da85a3afSAndrew-sh Cheng 127b3a37248SEddie Huang cpus { 128b3a37248SEddie Huang #address-cells = <1>; 129b3a37248SEddie Huang #size-cells = <0>; 130b3a37248SEddie Huang 131b3a37248SEddie Huang cpu-map { 132b3a37248SEddie Huang cluster0 { 133b3a37248SEddie Huang core0 { 134b3a37248SEddie Huang cpu = <&cpu0>; 135b3a37248SEddie Huang }; 136b3a37248SEddie Huang core1 { 137b3a37248SEddie Huang cpu = <&cpu1>; 138b3a37248SEddie Huang }; 139b3a37248SEddie Huang }; 140b3a37248SEddie Huang 141b3a37248SEddie Huang cluster1 { 142b3a37248SEddie Huang core0 { 143b3a37248SEddie Huang cpu = <&cpu2>; 144b3a37248SEddie Huang }; 145b3a37248SEddie Huang core1 { 146b3a37248SEddie Huang cpu = <&cpu3>; 147b3a37248SEddie Huang }; 148b3a37248SEddie Huang }; 149b3a37248SEddie Huang }; 150b3a37248SEddie Huang 151b3a37248SEddie Huang cpu0: cpu@0 { 152b3a37248SEddie Huang device_type = "cpu"; 153b3a37248SEddie Huang compatible = "arm,cortex-a53"; 154b3a37248SEddie Huang reg = <0x000>; 155ad4df7a5SHoward Chen enable-method = "psci"; 156ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 157acbf76eeSArnd Bergmann #cooling-cells = <2>; 15819f62c76Smichael.kao dynamic-power-coefficient = <263>; 159da85a3afSAndrew-sh Cheng clocks = <&infracfg CLK_INFRA_CA53SEL>, 160da85a3afSAndrew-sh Cheng <&apmixedsys CLK_APMIXED_MAINPLL>; 161da85a3afSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 162da85a3afSAndrew-sh Cheng operating-points-v2 = <&cluster0_opp>; 16379c528e9SHsin-Yi Wang capacity-dmips-mhz = <740>; 164b3a37248SEddie Huang }; 165b3a37248SEddie Huang 166b3a37248SEddie Huang cpu1: cpu@1 { 167b3a37248SEddie Huang device_type = "cpu"; 168b3a37248SEddie Huang compatible = "arm,cortex-a53"; 169b3a37248SEddie Huang reg = <0x001>; 170b3a37248SEddie Huang enable-method = "psci"; 171ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 172a06e5c05SViresh Kumar #cooling-cells = <2>; 17319f62c76Smichael.kao dynamic-power-coefficient = <263>; 174da85a3afSAndrew-sh Cheng clocks = <&infracfg CLK_INFRA_CA53SEL>, 175da85a3afSAndrew-sh Cheng <&apmixedsys CLK_APMIXED_MAINPLL>; 176da85a3afSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 177da85a3afSAndrew-sh Cheng operating-points-v2 = <&cluster0_opp>; 17879c528e9SHsin-Yi Wang capacity-dmips-mhz = <740>; 179b3a37248SEddie Huang }; 180b3a37248SEddie Huang 181b3a37248SEddie Huang cpu2: cpu@100 { 182b3a37248SEddie Huang device_type = "cpu"; 1835c6e116dSSeiya Wang compatible = "arm,cortex-a72"; 184b3a37248SEddie Huang reg = <0x100>; 185b3a37248SEddie Huang enable-method = "psci"; 186ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 187acbf76eeSArnd Bergmann #cooling-cells = <2>; 18819f62c76Smichael.kao dynamic-power-coefficient = <530>; 1895c6e116dSSeiya Wang clocks = <&infracfg CLK_INFRA_CA72SEL>, 190da85a3afSAndrew-sh Cheng <&apmixedsys CLK_APMIXED_MAINPLL>; 191da85a3afSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 192da85a3afSAndrew-sh Cheng operating-points-v2 = <&cluster1_opp>; 193f0e5405bSUlrich Hecht capacity-dmips-mhz = <1024>; 194b3a37248SEddie Huang }; 195b3a37248SEddie Huang 196b3a37248SEddie Huang cpu3: cpu@101 { 197b3a37248SEddie Huang device_type = "cpu"; 1985c6e116dSSeiya Wang compatible = "arm,cortex-a72"; 199b3a37248SEddie Huang reg = <0x101>; 200b3a37248SEddie Huang enable-method = "psci"; 201ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 202a06e5c05SViresh Kumar #cooling-cells = <2>; 20319f62c76Smichael.kao dynamic-power-coefficient = <530>; 2045c6e116dSSeiya Wang clocks = <&infracfg CLK_INFRA_CA72SEL>, 205da85a3afSAndrew-sh Cheng <&apmixedsys CLK_APMIXED_MAINPLL>; 206da85a3afSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 207da85a3afSAndrew-sh Cheng operating-points-v2 = <&cluster1_opp>; 208f0e5405bSUlrich Hecht capacity-dmips-mhz = <1024>; 209ad4df7a5SHoward Chen }; 210ad4df7a5SHoward Chen 211ad4df7a5SHoward Chen idle-states { 212a13f18f5SLorenzo Pieralisi entry-method = "psci"; 213ad4df7a5SHoward Chen 214ad4df7a5SHoward Chen CPU_SLEEP_0: cpu-sleep-0 { 215ad4df7a5SHoward Chen compatible = "arm,idle-state"; 216ad4df7a5SHoward Chen local-timer-stop; 217ad4df7a5SHoward Chen entry-latency-us = <639>; 218ad4df7a5SHoward Chen exit-latency-us = <680>; 219ad4df7a5SHoward Chen min-residency-us = <1088>; 220ad4df7a5SHoward Chen arm,psci-suspend-param = <0x0010000>; 221ad4df7a5SHoward Chen }; 222b3a37248SEddie Huang }; 223b3a37248SEddie Huang }; 224b3a37248SEddie Huang 225a4599f6eSSeiya Wang pmu_a53 { 226a4599f6eSSeiya Wang compatible = "arm,cortex-a53-pmu"; 227a4599f6eSSeiya Wang interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, 228a4599f6eSSeiya Wang <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>; 229a4599f6eSSeiya Wang interrupt-affinity = <&cpu0>, <&cpu1>; 230a4599f6eSSeiya Wang }; 231a4599f6eSSeiya Wang 232a4599f6eSSeiya Wang pmu_a72 { 233a4599f6eSSeiya Wang compatible = "arm,cortex-a72-pmu"; 234a4599f6eSSeiya Wang interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>, 235a4599f6eSSeiya Wang <GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>; 236a4599f6eSSeiya Wang interrupt-affinity = <&cpu2>, <&cpu3>; 237a4599f6eSSeiya Wang }; 238a4599f6eSSeiya Wang 239b3a37248SEddie Huang psci { 24005bdabe7SFan Chen compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 241b3a37248SEddie Huang method = "smc"; 242b3a37248SEddie Huang cpu_suspend = <0x84000001>; 243b3a37248SEddie Huang cpu_off = <0x84000002>; 244b3a37248SEddie Huang cpu_on = <0x84000003>; 245b3a37248SEddie Huang }; 246b3a37248SEddie Huang 24772b29215SHsin-Yi Wang clk26m: oscillator0 { 248f2ce7014SSascha Hauer compatible = "fixed-clock"; 249f2ce7014SSascha Hauer #clock-cells = <0>; 250f2ce7014SSascha Hauer clock-frequency = <26000000>; 251f2ce7014SSascha Hauer clock-output-names = "clk26m"; 252f2ce7014SSascha Hauer }; 253f2ce7014SSascha Hauer 25472b29215SHsin-Yi Wang clk32k: oscillator1 { 255f2ce7014SSascha Hauer compatible = "fixed-clock"; 256f2ce7014SSascha Hauer #clock-cells = <0>; 257f2ce7014SSascha Hauer clock-frequency = <32000>; 258f2ce7014SSascha Hauer clock-output-names = "clk32k"; 259f2ce7014SSascha Hauer }; 260f2ce7014SSascha Hauer 26172b29215SHsin-Yi Wang cpum_ck: oscillator2 { 26267e56c56SJames Liao compatible = "fixed-clock"; 26367e56c56SJames Liao #clock-cells = <0>; 26467e56c56SJames Liao clock-frequency = <0>; 26567e56c56SJames Liao clock-output-names = "cpum_ck"; 26667e56c56SJames Liao }; 26767e56c56SJames Liao 268962f5143Sdawei.chien@mediatek.com thermal-zones { 269624f1806SKrzysztof Kozlowski cpu_thermal: cpu-thermal { 270962f5143Sdawei.chien@mediatek.com polling-delay-passive = <1000>; /* milliseconds */ 271962f5143Sdawei.chien@mediatek.com polling-delay = <1000>; /* milliseconds */ 272962f5143Sdawei.chien@mediatek.com 273962f5143Sdawei.chien@mediatek.com thermal-sensors = <&thermal>; 274962f5143Sdawei.chien@mediatek.com sustainable-power = <1500>; /* milliwatts */ 275962f5143Sdawei.chien@mediatek.com 276962f5143Sdawei.chien@mediatek.com trips { 27772b29215SHsin-Yi Wang threshold: trip-point0 { 278962f5143Sdawei.chien@mediatek.com temperature = <68000>; 279962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 280962f5143Sdawei.chien@mediatek.com type = "passive"; 281962f5143Sdawei.chien@mediatek.com }; 282962f5143Sdawei.chien@mediatek.com 28372b29215SHsin-Yi Wang target: trip-point1 { 284962f5143Sdawei.chien@mediatek.com temperature = <85000>; 285962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 286962f5143Sdawei.chien@mediatek.com type = "passive"; 287962f5143Sdawei.chien@mediatek.com }; 288962f5143Sdawei.chien@mediatek.com 28972b29215SHsin-Yi Wang cpu_crit: cpu_crit0 { 290962f5143Sdawei.chien@mediatek.com temperature = <115000>; 291962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 292962f5143Sdawei.chien@mediatek.com type = "critical"; 293962f5143Sdawei.chien@mediatek.com }; 294962f5143Sdawei.chien@mediatek.com }; 295962f5143Sdawei.chien@mediatek.com 296962f5143Sdawei.chien@mediatek.com cooling-maps { 29772b29215SHsin-Yi Wang map0 { 298962f5143Sdawei.chien@mediatek.com trip = <&target>; 29926af2884SMichael Kao cooling-device = <&cpu0 THERMAL_NO_LIMIT 30026af2884SMichael Kao THERMAL_NO_LIMIT>, 30126af2884SMichael Kao <&cpu1 THERMAL_NO_LIMIT 30226af2884SMichael Kao THERMAL_NO_LIMIT>; 3037fcef92dSDaniel Kurtz contribution = <3072>; 304962f5143Sdawei.chien@mediatek.com }; 30572b29215SHsin-Yi Wang map1 { 306962f5143Sdawei.chien@mediatek.com trip = <&target>; 30726af2884SMichael Kao cooling-device = <&cpu2 THERMAL_NO_LIMIT 30826af2884SMichael Kao THERMAL_NO_LIMIT>, 30926af2884SMichael Kao <&cpu3 THERMAL_NO_LIMIT 31026af2884SMichael Kao THERMAL_NO_LIMIT>; 3117fcef92dSDaniel Kurtz contribution = <1024>; 312962f5143Sdawei.chien@mediatek.com }; 313962f5143Sdawei.chien@mediatek.com }; 314962f5143Sdawei.chien@mediatek.com }; 315962f5143Sdawei.chien@mediatek.com }; 316962f5143Sdawei.chien@mediatek.com 317404b2819SAndrew-CT Chen reserved-memory { 318404b2819SAndrew-CT Chen #address-cells = <2>; 319404b2819SAndrew-CT Chen #size-cells = <2>; 320404b2819SAndrew-CT Chen ranges; 32172b29215SHsin-Yi Wang vpu_dma_reserved: vpu_dma_mem_region@b7000000 { 322404b2819SAndrew-CT Chen compatible = "shared-dma-pool"; 323404b2819SAndrew-CT Chen reg = <0 0xb7000000 0 0x500000>; 324404b2819SAndrew-CT Chen alignment = <0x1000>; 325404b2819SAndrew-CT Chen no-map; 326404b2819SAndrew-CT Chen }; 327404b2819SAndrew-CT Chen }; 328404b2819SAndrew-CT Chen 329b3a37248SEddie Huang timer { 330b3a37248SEddie Huang compatible = "arm,armv8-timer"; 331b3a37248SEddie Huang interrupt-parent = <&gic>; 332b3a37248SEddie Huang interrupts = <GIC_PPI 13 333b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 334b3a37248SEddie Huang <GIC_PPI 14 335b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 336b3a37248SEddie Huang <GIC_PPI 11 337b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 338b3a37248SEddie Huang <GIC_PPI 10 339b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 340b5686273SHsin-Yi Wang arm,no-tick-in-suspend; 341b3a37248SEddie Huang }; 342b3a37248SEddie Huang 343b3a37248SEddie Huang soc { 344b3a37248SEddie Huang #address-cells = <2>; 345b3a37248SEddie Huang #size-cells = <2>; 346b3a37248SEddie Huang compatible = "simple-bus"; 347b3a37248SEddie Huang ranges; 348b3a37248SEddie Huang 349f2ce7014SSascha Hauer topckgen: clock-controller@10000000 { 350f2ce7014SSascha Hauer compatible = "mediatek,mt8173-topckgen"; 351f2ce7014SSascha Hauer reg = <0 0x10000000 0 0x1000>; 352f2ce7014SSascha Hauer #clock-cells = <1>; 353f2ce7014SSascha Hauer }; 354f2ce7014SSascha Hauer 355f2ce7014SSascha Hauer infracfg: power-controller@10001000 { 356f2ce7014SSascha Hauer compatible = "mediatek,mt8173-infracfg", "syscon"; 357f2ce7014SSascha Hauer reg = <0 0x10001000 0 0x1000>; 358f2ce7014SSascha Hauer #clock-cells = <1>; 359f2ce7014SSascha Hauer #reset-cells = <1>; 360f2ce7014SSascha Hauer }; 361f2ce7014SSascha Hauer 362f2ce7014SSascha Hauer pericfg: power-controller@10003000 { 363f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pericfg", "syscon"; 364f2ce7014SSascha Hauer reg = <0 0x10003000 0 0x1000>; 365f2ce7014SSascha Hauer #clock-cells = <1>; 366f2ce7014SSascha Hauer #reset-cells = <1>; 367f2ce7014SSascha Hauer }; 368f2ce7014SSascha Hauer 369f2ce7014SSascha Hauer syscfg_pctl_a: syscfg_pctl_a@10005000 { 370f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 371f2ce7014SSascha Hauer reg = <0 0x10005000 0 0x1000>; 372f2ce7014SSascha Hauer }; 373f2ce7014SSascha Hauer 37472b29215SHsin-Yi Wang pio: pinctrl@1000b000 { 375359f9365SHongzhou Yang compatible = "mediatek,mt8173-pinctrl"; 3766769b93cSYingjoe Chen reg = <0 0x1000b000 0 0x1000>; 377359f9365SHongzhou Yang mediatek,pctl-regmap = <&syscfg_pctl_a>; 378359f9365SHongzhou Yang pins-are-numbered; 379359f9365SHongzhou Yang gpio-controller; 380359f9365SHongzhou Yang #gpio-cells = <2>; 381359f9365SHongzhou Yang interrupt-controller; 382359f9365SHongzhou Yang #interrupt-cells = <2>; 383359f9365SHongzhou Yang interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 384359f9365SHongzhou Yang <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 385359f9365SHongzhou Yang <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 386091cf598SEddie Huang 387a10b57f4SCK Hu hdmi_pin: xxx { 388a10b57f4SCK Hu 389a10b57f4SCK Hu /*hdmi htplg pin*/ 390a10b57f4SCK Hu pins1 { 391a10b57f4SCK Hu pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>; 392a10b57f4SCK Hu input-enable; 393a10b57f4SCK Hu bias-pull-down; 394a10b57f4SCK Hu }; 395a10b57f4SCK Hu }; 396a10b57f4SCK Hu 397091cf598SEddie Huang i2c0_pins_a: i2c0 { 398091cf598SEddie Huang pins1 { 399091cf598SEddie Huang pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 400091cf598SEddie Huang <MT8173_PIN_46_SCL0__FUNC_SCL0>; 401091cf598SEddie Huang bias-disable; 402091cf598SEddie Huang }; 403359f9365SHongzhou Yang }; 404359f9365SHongzhou Yang 405091cf598SEddie Huang i2c1_pins_a: i2c1 { 406091cf598SEddie Huang pins1 { 407091cf598SEddie Huang pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 408091cf598SEddie Huang <MT8173_PIN_126_SCL1__FUNC_SCL1>; 409091cf598SEddie Huang bias-disable; 410091cf598SEddie Huang }; 411091cf598SEddie Huang }; 412091cf598SEddie Huang 413091cf598SEddie Huang i2c2_pins_a: i2c2 { 414091cf598SEddie Huang pins1 { 415091cf598SEddie Huang pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 416091cf598SEddie Huang <MT8173_PIN_44_SCL2__FUNC_SCL2>; 417091cf598SEddie Huang bias-disable; 418091cf598SEddie Huang }; 419091cf598SEddie Huang }; 420091cf598SEddie Huang 421091cf598SEddie Huang i2c3_pins_a: i2c3 { 422091cf598SEddie Huang pins1 { 423091cf598SEddie Huang pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 424091cf598SEddie Huang <MT8173_PIN_107_SCL3__FUNC_SCL3>; 425091cf598SEddie Huang bias-disable; 426091cf598SEddie Huang }; 427091cf598SEddie Huang }; 428091cf598SEddie Huang 429091cf598SEddie Huang i2c4_pins_a: i2c4 { 430091cf598SEddie Huang pins1 { 431091cf598SEddie Huang pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 432091cf598SEddie Huang <MT8173_PIN_134_SCL4__FUNC_SCL4>; 433091cf598SEddie Huang bias-disable; 434091cf598SEddie Huang }; 435091cf598SEddie Huang }; 436091cf598SEddie Huang 437091cf598SEddie Huang i2c6_pins_a: i2c6 { 438091cf598SEddie Huang pins1 { 439091cf598SEddie Huang pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 440091cf598SEddie Huang <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 441091cf598SEddie Huang bias-disable; 442091cf598SEddie Huang }; 443091cf598SEddie Huang }; 4446769b93cSYingjoe Chen }; 4456769b93cSYingjoe Chen 4468b656264SEnric Balletbo i Serra scpsys: syscon@10006000 { 447*d3dfd468STinghan Shen compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd"; 448c010ff53SSascha Hauer reg = <0 0x10006000 0 0x1000>; 4498b656264SEnric Balletbo i Serra 4508b656264SEnric Balletbo i Serra /* System Power Manager */ 4518b656264SEnric Balletbo i Serra spm: power-controller { 4528b656264SEnric Balletbo i Serra compatible = "mediatek,mt8173-power-controller"; 4538b656264SEnric Balletbo i Serra #address-cells = <1>; 4548b656264SEnric Balletbo i Serra #size-cells = <0>; 4558b656264SEnric Balletbo i Serra #power-domain-cells = <1>; 4568b656264SEnric Balletbo i Serra 4578b656264SEnric Balletbo i Serra /* power domains of the SoC */ 4588b656264SEnric Balletbo i Serra power-domain@MT8173_POWER_DOMAIN_VDEC { 4598b656264SEnric Balletbo i Serra reg = <MT8173_POWER_DOMAIN_VDEC>; 4608b656264SEnric Balletbo i Serra clocks = <&topckgen CLK_TOP_MM_SEL>; 4618b656264SEnric Balletbo i Serra clock-names = "mm"; 4628b656264SEnric Balletbo i Serra #power-domain-cells = <0>; 4638b656264SEnric Balletbo i Serra }; 4648b656264SEnric Balletbo i Serra power-domain@MT8173_POWER_DOMAIN_VENC { 4658b656264SEnric Balletbo i Serra reg = <MT8173_POWER_DOMAIN_VENC>; 4668b656264SEnric Balletbo i Serra clocks = <&topckgen CLK_TOP_MM_SEL>, 4678b656264SEnric Balletbo i Serra <&topckgen CLK_TOP_VENC_SEL>; 4688b656264SEnric Balletbo i Serra clock-names = "mm", "venc"; 4698b656264SEnric Balletbo i Serra #power-domain-cells = <0>; 4708b656264SEnric Balletbo i Serra }; 4718b656264SEnric Balletbo i Serra power-domain@MT8173_POWER_DOMAIN_ISP { 4728b656264SEnric Balletbo i Serra reg = <MT8173_POWER_DOMAIN_ISP>; 4738b656264SEnric Balletbo i Serra clocks = <&topckgen CLK_TOP_MM_SEL>; 4748b656264SEnric Balletbo i Serra clock-names = "mm"; 4758b656264SEnric Balletbo i Serra #power-domain-cells = <0>; 4768b656264SEnric Balletbo i Serra }; 4778b656264SEnric Balletbo i Serra power-domain@MT8173_POWER_DOMAIN_MM { 4788b656264SEnric Balletbo i Serra reg = <MT8173_POWER_DOMAIN_MM>; 4798b656264SEnric Balletbo i Serra clocks = <&topckgen CLK_TOP_MM_SEL>; 4808b656264SEnric Balletbo i Serra clock-names = "mm"; 4818b656264SEnric Balletbo i Serra #power-domain-cells = <0>; 4828b656264SEnric Balletbo i Serra mediatek,infracfg = <&infracfg>; 4838b656264SEnric Balletbo i Serra }; 4848b656264SEnric Balletbo i Serra power-domain@MT8173_POWER_DOMAIN_VENC_LT { 4858b656264SEnric Balletbo i Serra reg = <MT8173_POWER_DOMAIN_VENC_LT>; 4868b656264SEnric Balletbo i Serra clocks = <&topckgen CLK_TOP_MM_SEL>, 487e34573c9SJames Liao <&topckgen CLK_TOP_VENC_LT_SEL>; 4888b656264SEnric Balletbo i Serra clock-names = "mm", "venclt"; 4898b656264SEnric Balletbo i Serra #power-domain-cells = <0>; 4908b656264SEnric Balletbo i Serra }; 4918b656264SEnric Balletbo i Serra power-domain@MT8173_POWER_DOMAIN_AUDIO { 4928b656264SEnric Balletbo i Serra reg = <MT8173_POWER_DOMAIN_AUDIO>; 4938b656264SEnric Balletbo i Serra #power-domain-cells = <0>; 4948b656264SEnric Balletbo i Serra }; 4958b656264SEnric Balletbo i Serra power-domain@MT8173_POWER_DOMAIN_USB { 4968b656264SEnric Balletbo i Serra reg = <MT8173_POWER_DOMAIN_USB>; 4978b656264SEnric Balletbo i Serra #power-domain-cells = <0>; 4988b656264SEnric Balletbo i Serra }; 499109fd206SBilal Wasim mfg_async: power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC { 5008b656264SEnric Balletbo i Serra reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>; 5018b656264SEnric Balletbo i Serra clocks = <&clk26m>; 5028b656264SEnric Balletbo i Serra clock-names = "mfg"; 5038b656264SEnric Balletbo i Serra #address-cells = <1>; 5048b656264SEnric Balletbo i Serra #size-cells = <0>; 5058b656264SEnric Balletbo i Serra #power-domain-cells = <1>; 5068b656264SEnric Balletbo i Serra 5078b656264SEnric Balletbo i Serra power-domain@MT8173_POWER_DOMAIN_MFG_2D { 5088b656264SEnric Balletbo i Serra reg = <MT8173_POWER_DOMAIN_MFG_2D>; 5098b656264SEnric Balletbo i Serra #address-cells = <1>; 5108b656264SEnric Balletbo i Serra #size-cells = <0>; 5118b656264SEnric Balletbo i Serra #power-domain-cells = <1>; 5128b656264SEnric Balletbo i Serra 5138b656264SEnric Balletbo i Serra power-domain@MT8173_POWER_DOMAIN_MFG { 5148b656264SEnric Balletbo i Serra reg = <MT8173_POWER_DOMAIN_MFG>; 5158b656264SEnric Balletbo i Serra #power-domain-cells = <0>; 5168b656264SEnric Balletbo i Serra mediatek,infracfg = <&infracfg>; 5178b656264SEnric Balletbo i Serra }; 5188b656264SEnric Balletbo i Serra }; 5198b656264SEnric Balletbo i Serra }; 5208b656264SEnric Balletbo i Serra }; 521c010ff53SSascha Hauer }; 522c010ff53SSascha Hauer 52313421b3eSEddie Huang watchdog: watchdog@10007000 { 52413421b3eSEddie Huang compatible = "mediatek,mt8173-wdt", 52513421b3eSEddie Huang "mediatek,mt6589-wdt"; 52613421b3eSEddie Huang reg = <0 0x10007000 0 0x100>; 52713421b3eSEddie Huang }; 52813421b3eSEddie Huang 529b2c76e27SDaniel Kurtz timer: timer@10008000 { 530b2c76e27SDaniel Kurtz compatible = "mediatek,mt8173-timer", 531b2c76e27SDaniel Kurtz "mediatek,mt6577-timer"; 532b2c76e27SDaniel Kurtz reg = <0 0x10008000 0 0x1000>; 533b2c76e27SDaniel Kurtz interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 534b2c76e27SDaniel Kurtz clocks = <&infracfg CLK_INFRA_CLK_13M>, 535b2c76e27SDaniel Kurtz <&topckgen CLK_TOP_RTC_SEL>; 536b2c76e27SDaniel Kurtz }; 537b2c76e27SDaniel Kurtz 5386cf15fc2SSascha Hauer pwrap: pwrap@1000d000 { 5396cf15fc2SSascha Hauer compatible = "mediatek,mt8173-pwrap"; 5406cf15fc2SSascha Hauer reg = <0 0x1000d000 0 0x1000>; 5416cf15fc2SSascha Hauer reg-names = "pwrap"; 5426cf15fc2SSascha Hauer interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 5436cf15fc2SSascha Hauer resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 5446cf15fc2SSascha Hauer reset-names = "pwrap"; 5456cf15fc2SSascha Hauer clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 5466cf15fc2SSascha Hauer clock-names = "spi", "wrap"; 5476cf15fc2SSascha Hauer }; 5486cf15fc2SSascha Hauer 549a10b57f4SCK Hu cec: cec@10013000 { 550a10b57f4SCK Hu compatible = "mediatek,mt8173-cec"; 551a10b57f4SCK Hu reg = <0 0x10013000 0 0xbc>; 552a10b57f4SCK Hu interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; 553a10b57f4SCK Hu clocks = <&infracfg CLK_INFRA_CEC>; 554a10b57f4SCK Hu status = "disabled"; 555a10b57f4SCK Hu }; 556a10b57f4SCK Hu 557404b2819SAndrew-CT Chen vpu: vpu@10020000 { 558404b2819SAndrew-CT Chen compatible = "mediatek,mt8173-vpu"; 559404b2819SAndrew-CT Chen reg = <0 0x10020000 0 0x30000>, 560404b2819SAndrew-CT Chen <0 0x10050000 0 0x100>; 561404b2819SAndrew-CT Chen reg-names = "tcm", "cfg_reg"; 562404b2819SAndrew-CT Chen interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 563404b2819SAndrew-CT Chen clocks = <&topckgen CLK_TOP_SCP_SEL>; 564404b2819SAndrew-CT Chen clock-names = "main"; 565404b2819SAndrew-CT Chen memory-region = <&vpu_dma_reserved>; 566404b2819SAndrew-CT Chen }; 567404b2819SAndrew-CT Chen 568b3a37248SEddie Huang sysirq: intpol-controller@10200620 { 569b3a37248SEddie Huang compatible = "mediatek,mt8173-sysirq", 570b3a37248SEddie Huang "mediatek,mt6577-sysirq"; 571b3a37248SEddie Huang interrupt-controller; 572b3a37248SEddie Huang #interrupt-cells = <3>; 573b3a37248SEddie Huang interrupt-parent = <&gic>; 574b3a37248SEddie Huang reg = <0 0x10200620 0 0x20>; 575b3a37248SEddie Huang }; 576b3a37248SEddie Huang 5775ff6b3a6SYong Wu iommu: iommu@10205000 { 5785ff6b3a6SYong Wu compatible = "mediatek,mt8173-m4u"; 5795ff6b3a6SYong Wu reg = <0 0x10205000 0 0x1000>; 5805ff6b3a6SYong Wu interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 5815ff6b3a6SYong Wu clocks = <&infracfg CLK_INFRA_M4U>; 5825ff6b3a6SYong Wu clock-names = "bclk"; 5837b06e86eSAngeloGioacchino Del Regno mediatek,infracfg = <&infracfg>; 58433c7874bSNícolas F. R. A. Prado mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, 58533c7874bSNícolas F. R. A. Prado <&larb3>, <&larb4>, <&larb5>; 5865ff6b3a6SYong Wu #iommu-cells = <1>; 5875ff6b3a6SYong Wu }; 5885ff6b3a6SYong Wu 58993e9f5eeSandrew-ct.chen@mediatek.com efuse: efuse@10206000 { 59093e9f5eeSandrew-ct.chen@mediatek.com compatible = "mediatek,mt8173-efuse"; 59193e9f5eeSandrew-ct.chen@mediatek.com reg = <0 0x10206000 0 0x1000>; 5926de18454Sdawei.chien@mediatek.com #address-cells = <1>; 5936de18454Sdawei.chien@mediatek.com #size-cells = <1>; 5946de18454Sdawei.chien@mediatek.com thermal_calibration: calib@528 { 5956de18454Sdawei.chien@mediatek.com reg = <0x528 0xc>; 5966de18454Sdawei.chien@mediatek.com }; 59793e9f5eeSandrew-ct.chen@mediatek.com }; 59893e9f5eeSandrew-ct.chen@mediatek.com 599f2ce7014SSascha Hauer apmixedsys: clock-controller@10209000 { 600f2ce7014SSascha Hauer compatible = "mediatek,mt8173-apmixedsys"; 601f2ce7014SSascha Hauer reg = <0 0x10209000 0 0x1000>; 602f2ce7014SSascha Hauer #clock-cells = <1>; 603f2ce7014SSascha Hauer }; 604f2ce7014SSascha Hauer 605a10b57f4SCK Hu hdmi_phy: hdmi-phy@10209100 { 606a10b57f4SCK Hu compatible = "mediatek,mt8173-hdmi-phy"; 607a10b57f4SCK Hu reg = <0 0x10209100 0 0x24>; 608a10b57f4SCK Hu clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; 609a10b57f4SCK Hu clock-names = "pll_ref"; 610a10b57f4SCK Hu clock-output-names = "hdmitx_dig_cts"; 611a10b57f4SCK Hu mediatek,ibias = <0xa>; 612a10b57f4SCK Hu mediatek,ibias_up = <0x1c>; 613a10b57f4SCK Hu #clock-cells = <0>; 614a10b57f4SCK Hu #phy-cells = <0>; 615a10b57f4SCK Hu status = "disabled"; 616a10b57f4SCK Hu }; 617a10b57f4SCK Hu 618c2e66b8fSHoulong Wei gce: mailbox@10212000 { 619c2e66b8fSHoulong Wei compatible = "mediatek,mt8173-gce"; 620c2e66b8fSHoulong Wei reg = <0 0x10212000 0 0x1000>; 621c2e66b8fSHoulong Wei interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 622c2e66b8fSHoulong Wei clocks = <&infracfg CLK_INFRA_GCE>; 623c2e66b8fSHoulong Wei clock-names = "gce"; 624eb4a01afSHsin-Yi Wang #mbox-cells = <2>; 625c2e66b8fSHoulong Wei }; 626c2e66b8fSHoulong Wei 627c61872d5SChunfeng Yun mipi_tx0: dsi-phy@10215000 { 62881ad4dbaSCK Hu compatible = "mediatek,mt8173-mipi-tx"; 62981ad4dbaSCK Hu reg = <0 0x10215000 0 0x1000>; 63081ad4dbaSCK Hu clocks = <&clk26m>; 63181ad4dbaSCK Hu clock-output-names = "mipi_tx0_pll"; 63281ad4dbaSCK Hu #clock-cells = <0>; 63381ad4dbaSCK Hu #phy-cells = <0>; 63481ad4dbaSCK Hu status = "disabled"; 63581ad4dbaSCK Hu }; 63681ad4dbaSCK Hu 637c61872d5SChunfeng Yun mipi_tx1: dsi-phy@10216000 { 63881ad4dbaSCK Hu compatible = "mediatek,mt8173-mipi-tx"; 63981ad4dbaSCK Hu reg = <0 0x10216000 0 0x1000>; 64081ad4dbaSCK Hu clocks = <&clk26m>; 64181ad4dbaSCK Hu clock-output-names = "mipi_tx1_pll"; 64281ad4dbaSCK Hu #clock-cells = <0>; 64381ad4dbaSCK Hu #phy-cells = <0>; 64481ad4dbaSCK Hu status = "disabled"; 64581ad4dbaSCK Hu }; 64681ad4dbaSCK Hu 64772b29215SHsin-Yi Wang gic: interrupt-controller@10221000 { 648b3a37248SEddie Huang compatible = "arm,gic-400"; 649b3a37248SEddie Huang #interrupt-cells = <3>; 650b3a37248SEddie Huang interrupt-parent = <&gic>; 651b3a37248SEddie Huang interrupt-controller; 652b3a37248SEddie Huang reg = <0 0x10221000 0 0x1000>, 653b3a37248SEddie Huang <0 0x10222000 0 0x2000>, 654b3a37248SEddie Huang <0 0x10224000 0 0x2000>, 655b3a37248SEddie Huang <0 0x10226000 0 0x2000>; 656b3a37248SEddie Huang interrupts = <GIC_PPI 9 657b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 658b3a37248SEddie Huang }; 659b3a37248SEddie Huang 660748c7d4dSSascha Hauer auxadc: auxadc@11001000 { 661748c7d4dSSascha Hauer compatible = "mediatek,mt8173-auxadc"; 662748c7d4dSSascha Hauer reg = <0 0x11001000 0 0x1000>; 663a3207d64SMatthias Brugger clocks = <&pericfg CLK_PERI_AUXADC>; 664a3207d64SMatthias Brugger clock-names = "main"; 665a3207d64SMatthias Brugger #io-channel-cells = <1>; 666748c7d4dSSascha Hauer }; 667748c7d4dSSascha Hauer 668b3a37248SEddie Huang uart0: serial@11002000 { 669b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 670b3a37248SEddie Huang "mediatek,mt6577-uart"; 671b3a37248SEddie Huang reg = <0 0x11002000 0 0x400>; 672b3a37248SEddie Huang interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 6730e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 6740e84faa1SSascha Hauer clock-names = "baud", "bus"; 675b3a37248SEddie Huang status = "disabled"; 676b3a37248SEddie Huang }; 677b3a37248SEddie Huang 678b3a37248SEddie Huang uart1: serial@11003000 { 679b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 680b3a37248SEddie Huang "mediatek,mt6577-uart"; 681b3a37248SEddie Huang reg = <0 0x11003000 0 0x400>; 682b3a37248SEddie Huang interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 6830e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 6840e84faa1SSascha Hauer clock-names = "baud", "bus"; 685b3a37248SEddie Huang status = "disabled"; 686b3a37248SEddie Huang }; 687b3a37248SEddie Huang 688b3a37248SEddie Huang uart2: serial@11004000 { 689b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 690b3a37248SEddie Huang "mediatek,mt6577-uart"; 691b3a37248SEddie Huang reg = <0 0x11004000 0 0x400>; 692b3a37248SEddie Huang interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 6930e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 6940e84faa1SSascha Hauer clock-names = "baud", "bus"; 695b3a37248SEddie Huang status = "disabled"; 696b3a37248SEddie Huang }; 697b3a37248SEddie Huang 698b3a37248SEddie Huang uart3: serial@11005000 { 699b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 700b3a37248SEddie Huang "mediatek,mt6577-uart"; 701b3a37248SEddie Huang reg = <0 0x11005000 0 0x400>; 702b3a37248SEddie Huang interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 7030e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 7040e84faa1SSascha Hauer clock-names = "baud", "bus"; 705b3a37248SEddie Huang status = "disabled"; 706b3a37248SEddie Huang }; 707091cf598SEddie Huang 708091cf598SEddie Huang i2c0: i2c@11007000 { 709091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 710091cf598SEddie Huang reg = <0 0x11007000 0 0x70>, 711091cf598SEddie Huang <0 0x11000100 0 0x80>; 712091cf598SEddie Huang interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 713091cf598SEddie Huang clock-div = <16>; 714091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C0>, 715091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 716091cf598SEddie Huang clock-names = "main", "dma"; 717091cf598SEddie Huang pinctrl-names = "default"; 718091cf598SEddie Huang pinctrl-0 = <&i2c0_pins_a>; 719091cf598SEddie Huang #address-cells = <1>; 720091cf598SEddie Huang #size-cells = <0>; 721091cf598SEddie Huang status = "disabled"; 722091cf598SEddie Huang }; 723091cf598SEddie Huang 724091cf598SEddie Huang i2c1: i2c@11008000 { 725091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 726091cf598SEddie Huang reg = <0 0x11008000 0 0x70>, 727091cf598SEddie Huang <0 0x11000180 0 0x80>; 728091cf598SEddie Huang interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 729091cf598SEddie Huang clock-div = <16>; 730091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C1>, 731091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 732091cf598SEddie Huang clock-names = "main", "dma"; 733091cf598SEddie Huang pinctrl-names = "default"; 734091cf598SEddie Huang pinctrl-0 = <&i2c1_pins_a>; 735091cf598SEddie Huang #address-cells = <1>; 736091cf598SEddie Huang #size-cells = <0>; 737091cf598SEddie Huang status = "disabled"; 738091cf598SEddie Huang }; 739091cf598SEddie Huang 740091cf598SEddie Huang i2c2: i2c@11009000 { 741091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 742091cf598SEddie Huang reg = <0 0x11009000 0 0x70>, 743091cf598SEddie Huang <0 0x11000200 0 0x80>; 744091cf598SEddie Huang interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 745091cf598SEddie Huang clock-div = <16>; 746091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C2>, 747091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 748091cf598SEddie Huang clock-names = "main", "dma"; 749091cf598SEddie Huang pinctrl-names = "default"; 750091cf598SEddie Huang pinctrl-0 = <&i2c2_pins_a>; 751091cf598SEddie Huang #address-cells = <1>; 752091cf598SEddie Huang #size-cells = <0>; 753091cf598SEddie Huang status = "disabled"; 754091cf598SEddie Huang }; 755091cf598SEddie Huang 756b0c936f5SLeilk Liu spi: spi@1100a000 { 757b0c936f5SLeilk Liu compatible = "mediatek,mt8173-spi"; 758b0c936f5SLeilk Liu #address-cells = <1>; 759b0c936f5SLeilk Liu #size-cells = <0>; 760b0c936f5SLeilk Liu reg = <0 0x1100a000 0 0x1000>; 761b0c936f5SLeilk Liu interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 762b0c936f5SLeilk Liu clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 763b0c936f5SLeilk Liu <&topckgen CLK_TOP_SPI_SEL>, 764b0c936f5SLeilk Liu <&pericfg CLK_PERI_SPI0>; 765b0c936f5SLeilk Liu clock-names = "parent-clk", "sel-clk", "spi-clk"; 766b0c936f5SLeilk Liu status = "disabled"; 767b0c936f5SLeilk Liu }; 768b0c936f5SLeilk Liu 769748c7d4dSSascha Hauer thermal: thermal@1100b000 { 770748c7d4dSSascha Hauer #thermal-sensor-cells = <0>; 771748c7d4dSSascha Hauer compatible = "mediatek,mt8173-thermal"; 772748c7d4dSSascha Hauer reg = <0 0x1100b000 0 0x1000>; 773748c7d4dSSascha Hauer interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 774748c7d4dSSascha Hauer clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 775748c7d4dSSascha Hauer clock-names = "therm", "auxadc"; 776748c7d4dSSascha Hauer resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 777748c7d4dSSascha Hauer mediatek,auxadc = <&auxadc>; 778748c7d4dSSascha Hauer mediatek,apmixedsys = <&apmixedsys>; 7796de18454Sdawei.chien@mediatek.com nvmem-cells = <&thermal_calibration>; 7806de18454Sdawei.chien@mediatek.com nvmem-cell-names = "calibration-data"; 781748c7d4dSSascha Hauer }; 782748c7d4dSSascha Hauer 78386cb8a88SBayi Cheng nor_flash: spi@1100d000 { 78486cb8a88SBayi Cheng compatible = "mediatek,mt8173-nor"; 78586cb8a88SBayi Cheng reg = <0 0x1100d000 0 0xe0>; 78604266856SXiangsheng Hou assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>; 78704266856SXiangsheng Hou assigned-clock-parents = <&clk26m>; 78886cb8a88SBayi Cheng clocks = <&pericfg CLK_PERI_SPI>, 78904266856SXiangsheng Hou <&topckgen CLK_TOP_SPINFI_IFR_SEL>, 79004266856SXiangsheng Hou <&pericfg CLK_PERI_NFI>; 79104266856SXiangsheng Hou clock-names = "spi", "sf", "axi"; 79286cb8a88SBayi Cheng #address-cells = <1>; 79386cb8a88SBayi Cheng #size-cells = <0>; 79486cb8a88SBayi Cheng status = "disabled"; 79586cb8a88SBayi Cheng }; 79686cb8a88SBayi Cheng 7971ee35c05SYingjoe Chen i2c3: i2c@11010000 { 798091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 799091cf598SEddie Huang reg = <0 0x11010000 0 0x70>, 800091cf598SEddie Huang <0 0x11000280 0 0x80>; 801091cf598SEddie Huang interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 802091cf598SEddie Huang clock-div = <16>; 803091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C3>, 804091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 805091cf598SEddie Huang clock-names = "main", "dma"; 806091cf598SEddie Huang pinctrl-names = "default"; 807091cf598SEddie Huang pinctrl-0 = <&i2c3_pins_a>; 808091cf598SEddie Huang #address-cells = <1>; 809091cf598SEddie Huang #size-cells = <0>; 810091cf598SEddie Huang status = "disabled"; 811091cf598SEddie Huang }; 812091cf598SEddie Huang 8131ee35c05SYingjoe Chen i2c4: i2c@11011000 { 814091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 815091cf598SEddie Huang reg = <0 0x11011000 0 0x70>, 816091cf598SEddie Huang <0 0x11000300 0 0x80>; 817091cf598SEddie Huang interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 818091cf598SEddie Huang clock-div = <16>; 819091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C4>, 820091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 821091cf598SEddie Huang clock-names = "main", "dma"; 822091cf598SEddie Huang pinctrl-names = "default"; 823091cf598SEddie Huang pinctrl-0 = <&i2c4_pins_a>; 824091cf598SEddie Huang #address-cells = <1>; 825091cf598SEddie Huang #size-cells = <0>; 826091cf598SEddie Huang status = "disabled"; 827091cf598SEddie Huang }; 828091cf598SEddie Huang 829a10b57f4SCK Hu hdmiddc0: i2c@11012000 { 830a10b57f4SCK Hu compatible = "mediatek,mt8173-hdmi-ddc"; 831a10b57f4SCK Hu interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 832a10b57f4SCK Hu reg = <0 0x11012000 0 0x1C>; 833a10b57f4SCK Hu clocks = <&pericfg CLK_PERI_I2C5>; 834a10b57f4SCK Hu clock-names = "ddc-i2c"; 835a10b57f4SCK Hu }; 836a10b57f4SCK Hu 8371ee35c05SYingjoe Chen i2c6: i2c@11013000 { 838091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 839091cf598SEddie Huang reg = <0 0x11013000 0 0x70>, 840091cf598SEddie Huang <0 0x11000080 0 0x80>; 841091cf598SEddie Huang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 842091cf598SEddie Huang clock-div = <16>; 843091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C6>, 844091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 845091cf598SEddie Huang clock-names = "main", "dma"; 846091cf598SEddie Huang pinctrl-names = "default"; 847091cf598SEddie Huang pinctrl-0 = <&i2c6_pins_a>; 848091cf598SEddie Huang #address-cells = <1>; 849091cf598SEddie Huang #size-cells = <0>; 850091cf598SEddie Huang status = "disabled"; 851091cf598SEddie Huang }; 852c02e0e86SKoro Chen 853c02e0e86SKoro Chen afe: audio-controller@11220000 { 854c02e0e86SKoro Chen compatible = "mediatek,mt8173-afe-pcm"; 855c02e0e86SKoro Chen reg = <0 0x11220000 0 0x1000>; 856c02e0e86SKoro Chen interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 8578b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_AUDIO>; 858c02e0e86SKoro Chen clocks = <&infracfg CLK_INFRA_AUDIO>, 859c02e0e86SKoro Chen <&topckgen CLK_TOP_AUDIO_SEL>, 860c02e0e86SKoro Chen <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 861c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL1_DIV0>, 862c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL2_DIV0>, 863c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S0_M_SEL>, 864c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S1_M_SEL>, 865c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S2_M_SEL>, 866c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S3_M_SEL>, 867c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S3_B_SEL>; 868c02e0e86SKoro Chen clock-names = "infra_sys_audio_clk", 869c02e0e86SKoro Chen "top_pdn_audio", 870c02e0e86SKoro Chen "top_pdn_aud_intbus", 871c02e0e86SKoro Chen "bck0", 872c02e0e86SKoro Chen "bck1", 873c02e0e86SKoro Chen "i2s0_m", 874c02e0e86SKoro Chen "i2s1_m", 875c02e0e86SKoro Chen "i2s2_m", 876c02e0e86SKoro Chen "i2s3_m", 877c02e0e86SKoro Chen "i2s3_b"; 878c02e0e86SKoro Chen assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 879c02e0e86SKoro Chen <&topckgen CLK_TOP_AUD_2_SEL>; 880c02e0e86SKoro Chen assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 881c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL2>; 882c02e0e86SKoro Chen }; 8839719fa5aSEddie Huang 8849719fa5aSEddie Huang mmc0: mmc@11230000 { 885689362b3SChaotian Jing compatible = "mediatek,mt8173-mmc"; 8869719fa5aSEddie Huang reg = <0 0x11230000 0 0x1000>; 8879719fa5aSEddie Huang interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 8889719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_0>, 8899719fa5aSEddie Huang <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 8909719fa5aSEddie Huang clock-names = "source", "hclk"; 8919719fa5aSEddie Huang status = "disabled"; 8929719fa5aSEddie Huang }; 8939719fa5aSEddie Huang 8949719fa5aSEddie Huang mmc1: mmc@11240000 { 895689362b3SChaotian Jing compatible = "mediatek,mt8173-mmc"; 8969719fa5aSEddie Huang reg = <0 0x11240000 0 0x1000>; 8979719fa5aSEddie Huang interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 8989719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_1>, 8999719fa5aSEddie Huang <&topckgen CLK_TOP_AXI_SEL>; 9009719fa5aSEddie Huang clock-names = "source", "hclk"; 9019719fa5aSEddie Huang status = "disabled"; 9029719fa5aSEddie Huang }; 9039719fa5aSEddie Huang 9049719fa5aSEddie Huang mmc2: mmc@11250000 { 905689362b3SChaotian Jing compatible = "mediatek,mt8173-mmc"; 9069719fa5aSEddie Huang reg = <0 0x11250000 0 0x1000>; 9079719fa5aSEddie Huang interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 9089719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_2>, 9099719fa5aSEddie Huang <&topckgen CLK_TOP_AXI_SEL>; 9109719fa5aSEddie Huang clock-names = "source", "hclk"; 9119719fa5aSEddie Huang status = "disabled"; 9129719fa5aSEddie Huang }; 9139719fa5aSEddie Huang 9149719fa5aSEddie Huang mmc3: mmc@11260000 { 915689362b3SChaotian Jing compatible = "mediatek,mt8173-mmc"; 9169719fa5aSEddie Huang reg = <0 0x11260000 0 0x1000>; 9179719fa5aSEddie Huang interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 9189719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_3>, 9199719fa5aSEddie Huang <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 9209719fa5aSEddie Huang clock-names = "source", "hclk"; 9219719fa5aSEddie Huang status = "disabled"; 9229719fa5aSEddie Huang }; 92367e56c56SJames Liao 924c0891284SChunfeng Yun ssusb: usb@11271000 { 925c61872d5SChunfeng Yun compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3"; 926c0891284SChunfeng Yun reg = <0 0x11271000 0 0x3000>, 927bfcce47aSChunfeng Yun <0 0x11280700 0 0x0100>; 928c0891284SChunfeng Yun reg-names = "mac", "ippc"; 929c0891284SChunfeng Yun interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>; 930ebf61c63Schunfeng.yun@mediatek.com phys = <&u2port0 PHY_TYPE_USB2>, 931ebf61c63Schunfeng.yun@mediatek.com <&u3port0 PHY_TYPE_USB3>, 932ebf61c63Schunfeng.yun@mediatek.com <&u2port1 PHY_TYPE_USB2>; 9338b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_USB>; 934cf1fcd45SChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 935cf1fcd45SChunfeng Yun clock-names = "sys_ck", "ref_ck"; 936cf1fcd45SChunfeng Yun mediatek,syscon-wakeup = <&pericfg 0x400 1>; 937c0891284SChunfeng Yun #address-cells = <2>; 938c0891284SChunfeng Yun #size-cells = <2>; 939c0891284SChunfeng Yun ranges; 940c0891284SChunfeng Yun status = "disabled"; 941c0891284SChunfeng Yun 942c61872d5SChunfeng Yun usb_host: usb@11270000 { 943c61872d5SChunfeng Yun compatible = "mediatek,mt8173-xhci", 944c61872d5SChunfeng Yun "mediatek,mtk-xhci"; 945c0891284SChunfeng Yun reg = <0 0x11270000 0 0x1000>; 946c0891284SChunfeng Yun reg-names = "mac"; 947c0891284SChunfeng Yun interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 9488b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_USB>; 949cb6efc7bSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 950cb6efc7bSChunfeng Yun clock-names = "sys_ck", "ref_ck"; 951c0891284SChunfeng Yun status = "disabled"; 952c0891284SChunfeng Yun }; 953bfcce47aSChunfeng Yun }; 954bfcce47aSChunfeng Yun 955c61872d5SChunfeng Yun u3phy: t-phy@11290000 { 956bfcce47aSChunfeng Yun compatible = "mediatek,mt8173-u3phy"; 957bfcce47aSChunfeng Yun reg = <0 0x11290000 0 0x800>; 958bfcce47aSChunfeng Yun #address-cells = <2>; 959bfcce47aSChunfeng Yun #size-cells = <2>; 960bfcce47aSChunfeng Yun ranges; 961bfcce47aSChunfeng Yun status = "okay"; 962bfcce47aSChunfeng Yun 963ebf61c63Schunfeng.yun@mediatek.com u2port0: usb-phy@11290800 { 964ebf61c63Schunfeng.yun@mediatek.com reg = <0 0x11290800 0 0x100>; 96510f84a7aSchunfeng.yun@mediatek.com clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 96610f84a7aSchunfeng.yun@mediatek.com clock-names = "ref"; 967bfcce47aSChunfeng Yun #phy-cells = <1>; 968bfcce47aSChunfeng Yun status = "okay"; 969bfcce47aSChunfeng Yun }; 970bfcce47aSChunfeng Yun 971ebf61c63Schunfeng.yun@mediatek.com u3port0: usb-phy@11290900 { 972ebf61c63Schunfeng.yun@mediatek.com reg = <0 0x11290900 0 0x700>; 97310f84a7aSchunfeng.yun@mediatek.com clocks = <&clk26m>; 97410f84a7aSchunfeng.yun@mediatek.com clock-names = "ref"; 975ebf61c63Schunfeng.yun@mediatek.com #phy-cells = <1>; 976ebf61c63Schunfeng.yun@mediatek.com status = "okay"; 977ebf61c63Schunfeng.yun@mediatek.com }; 978ebf61c63Schunfeng.yun@mediatek.com 979ebf61c63Schunfeng.yun@mediatek.com u2port1: usb-phy@11291000 { 980ebf61c63Schunfeng.yun@mediatek.com reg = <0 0x11291000 0 0x100>; 98110f84a7aSchunfeng.yun@mediatek.com clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 98210f84a7aSchunfeng.yun@mediatek.com clock-names = "ref"; 983bfcce47aSChunfeng Yun #phy-cells = <1>; 984bfcce47aSChunfeng Yun status = "okay"; 985bfcce47aSChunfeng Yun }; 986bfcce47aSChunfeng Yun }; 987bfcce47aSChunfeng Yun 988ae167ae2SEnric Balletbo i Serra mmsys: syscon@14000000 { 98967e56c56SJames Liao compatible = "mediatek,mt8173-mmsys", "syscon"; 99067e56c56SJames Liao reg = <0 0x14000000 0 0x1000>; 9918b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 992fc6634acSBibby Hsieh assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; 993fc6634acSBibby Hsieh assigned-clock-rates = <400000000>; 99467e56c56SJames Liao #clock-cells = <1>; 9957fdb1bc3SEnric Balletbo i Serra #reset-cells = <1>; 996eb4a01afSHsin-Yi Wang mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 997eb4a01afSHsin-Yi Wang <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 998eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 99967e56c56SJames Liao }; 100067e56c56SJames Liao 1001989b292aSMinghsiu Tsai mdp_rdma0: rdma@14001000 { 10028127881fSDaniel Kurtz compatible = "mediatek,mt8173-mdp-rdma", 10038127881fSDaniel Kurtz "mediatek,mt8173-mdp"; 1004989b292aSMinghsiu Tsai reg = <0 0x14001000 0 0x1000>; 1005989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RDMA0>, 1006989b292aSMinghsiu Tsai <&mmsys CLK_MM_MUTEX_32K>; 10078b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1008989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_RDMA0>; 10098127881fSDaniel Kurtz mediatek,vpu = <&vpu>; 1010989b292aSMinghsiu Tsai }; 1011989b292aSMinghsiu Tsai 1012989b292aSMinghsiu Tsai mdp_rdma1: rdma@14002000 { 1013989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rdma"; 1014989b292aSMinghsiu Tsai reg = <0 0x14002000 0 0x1000>; 1015989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RDMA1>, 1016989b292aSMinghsiu Tsai <&mmsys CLK_MM_MUTEX_32K>; 10178b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1018989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_RDMA1>; 1019989b292aSMinghsiu Tsai }; 1020989b292aSMinghsiu Tsai 1021989b292aSMinghsiu Tsai mdp_rsz0: rsz@14003000 { 1022989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rsz"; 1023989b292aSMinghsiu Tsai reg = <0 0x14003000 0 0x1000>; 1024989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RSZ0>; 10258b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1026989b292aSMinghsiu Tsai }; 1027989b292aSMinghsiu Tsai 1028989b292aSMinghsiu Tsai mdp_rsz1: rsz@14004000 { 1029989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rsz"; 1030989b292aSMinghsiu Tsai reg = <0 0x14004000 0 0x1000>; 1031989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RSZ1>; 10328b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1033989b292aSMinghsiu Tsai }; 1034989b292aSMinghsiu Tsai 1035989b292aSMinghsiu Tsai mdp_rsz2: rsz@14005000 { 1036989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rsz"; 1037989b292aSMinghsiu Tsai reg = <0 0x14005000 0 0x1000>; 1038989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RSZ2>; 10398b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1040989b292aSMinghsiu Tsai }; 1041989b292aSMinghsiu Tsai 1042989b292aSMinghsiu Tsai mdp_wdma0: wdma@14006000 { 1043989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-wdma"; 1044989b292aSMinghsiu Tsai reg = <0 0x14006000 0 0x1000>; 1045989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_WDMA>; 10468b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1047989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_WDMA>; 1048989b292aSMinghsiu Tsai }; 1049989b292aSMinghsiu Tsai 1050989b292aSMinghsiu Tsai mdp_wrot0: wrot@14007000 { 1051989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-wrot"; 1052989b292aSMinghsiu Tsai reg = <0 0x14007000 0 0x1000>; 1053989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_WROT0>; 10548b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1055989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_WROT0>; 1056989b292aSMinghsiu Tsai }; 1057989b292aSMinghsiu Tsai 1058989b292aSMinghsiu Tsai mdp_wrot1: wrot@14008000 { 1059989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-wrot"; 1060989b292aSMinghsiu Tsai reg = <0 0x14008000 0 0x1000>; 1061989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_WROT1>; 10628b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1063989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_WROT1>; 1064989b292aSMinghsiu Tsai }; 1065989b292aSMinghsiu Tsai 106681ad4dbaSCK Hu ovl0: ovl@1400c000 { 106781ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-ovl"; 106881ad4dbaSCK Hu reg = <0 0x1400c000 0 0x1000>; 106981ad4dbaSCK Hu interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 10708b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 107181ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_OVL0>; 107281ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_OVL0>; 1073eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 107481ad4dbaSCK Hu }; 107581ad4dbaSCK Hu 107681ad4dbaSCK Hu ovl1: ovl@1400d000 { 107781ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-ovl"; 107881ad4dbaSCK Hu reg = <0 0x1400d000 0 0x1000>; 107981ad4dbaSCK Hu interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; 10808b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 108181ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_OVL1>; 108281ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_OVL1>; 1083eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 108481ad4dbaSCK Hu }; 108581ad4dbaSCK Hu 108681ad4dbaSCK Hu rdma0: rdma@1400e000 { 108781ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-rdma"; 108881ad4dbaSCK Hu reg = <0 0x1400e000 0 0x1000>; 108981ad4dbaSCK Hu interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 10908b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 109181ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_RDMA0>; 109281ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_RDMA0>; 1093eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 109481ad4dbaSCK Hu }; 109581ad4dbaSCK Hu 109681ad4dbaSCK Hu rdma1: rdma@1400f000 { 109781ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-rdma"; 109881ad4dbaSCK Hu reg = <0 0x1400f000 0 0x1000>; 109981ad4dbaSCK Hu interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; 11008b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 110181ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_RDMA1>; 110281ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_RDMA1>; 1103eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; 110481ad4dbaSCK Hu }; 110581ad4dbaSCK Hu 110681ad4dbaSCK Hu rdma2: rdma@14010000 { 110781ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-rdma"; 110881ad4dbaSCK Hu reg = <0 0x14010000 0 0x1000>; 110981ad4dbaSCK Hu interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; 11108b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 111181ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_RDMA2>; 111281ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_RDMA2>; 1113eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; 111481ad4dbaSCK Hu }; 111581ad4dbaSCK Hu 111681ad4dbaSCK Hu wdma0: wdma@14011000 { 111781ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-wdma"; 111881ad4dbaSCK Hu reg = <0 0x14011000 0 0x1000>; 111981ad4dbaSCK Hu interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 11208b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 112181ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_WDMA0>; 112281ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_WDMA0>; 1123eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 112481ad4dbaSCK Hu }; 112581ad4dbaSCK Hu 112681ad4dbaSCK Hu wdma1: wdma@14012000 { 112781ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-wdma"; 112881ad4dbaSCK Hu reg = <0 0x14012000 0 0x1000>; 112981ad4dbaSCK Hu interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; 11308b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 113181ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_WDMA1>; 113281ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_WDMA1>; 1133eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; 113481ad4dbaSCK Hu }; 113581ad4dbaSCK Hu 113681ad4dbaSCK Hu color0: color@14013000 { 113781ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-color"; 113881ad4dbaSCK Hu reg = <0 0x14013000 0 0x1000>; 113981ad4dbaSCK Hu interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; 11408b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 114181ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1142eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>; 114381ad4dbaSCK Hu }; 114481ad4dbaSCK Hu 114581ad4dbaSCK Hu color1: color@14014000 { 114681ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-color"; 114781ad4dbaSCK Hu reg = <0 0x14014000 0 0x1000>; 114881ad4dbaSCK Hu interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 11498b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 115081ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_COLOR1>; 1151eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; 115281ad4dbaSCK Hu }; 115381ad4dbaSCK Hu 115481ad4dbaSCK Hu aal@14015000 { 115581ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-aal"; 115681ad4dbaSCK Hu reg = <0 0x14015000 0 0x1000>; 115781ad4dbaSCK Hu interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 11588b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 115981ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_AAL>; 1160eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; 116181ad4dbaSCK Hu }; 116281ad4dbaSCK Hu 116381ad4dbaSCK Hu gamma@14016000 { 116481ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-gamma"; 116581ad4dbaSCK Hu reg = <0 0x14016000 0 0x1000>; 116681ad4dbaSCK Hu interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 11678b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 116881ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_GAMMA>; 1169eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; 117081ad4dbaSCK Hu }; 117181ad4dbaSCK Hu 117281ad4dbaSCK Hu merge@14017000 { 117381ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-merge"; 117481ad4dbaSCK Hu reg = <0 0x14017000 0 0x1000>; 11758b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 117681ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_MERGE>; 117781ad4dbaSCK Hu }; 117881ad4dbaSCK Hu 117981ad4dbaSCK Hu split0: split@14018000 { 118081ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-split"; 118181ad4dbaSCK Hu reg = <0 0x14018000 0 0x1000>; 11828b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 118381ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_SPLIT0>; 118481ad4dbaSCK Hu }; 118581ad4dbaSCK Hu 118681ad4dbaSCK Hu split1: split@14019000 { 118781ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-split"; 118881ad4dbaSCK Hu reg = <0 0x14019000 0 0x1000>; 11898b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 119081ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_SPLIT1>; 119181ad4dbaSCK Hu }; 119281ad4dbaSCK Hu 119381ad4dbaSCK Hu ufoe@1401a000 { 119481ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-ufoe"; 119581ad4dbaSCK Hu reg = <0 0x1401a000 0 0x1000>; 119681ad4dbaSCK Hu interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 11978b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 119881ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_UFOE>; 1199ab0c1e34SAngeloGioacchino Del Regno mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>; 120081ad4dbaSCK Hu }; 120181ad4dbaSCK Hu 120281ad4dbaSCK Hu dsi0: dsi@1401b000 { 120381ad4dbaSCK Hu compatible = "mediatek,mt8173-dsi"; 120481ad4dbaSCK Hu reg = <0 0x1401b000 0 0x1000>; 120581ad4dbaSCK Hu interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 12068b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 120781ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DSI0_ENGINE>, 120881ad4dbaSCK Hu <&mmsys CLK_MM_DSI0_DIGITAL>, 120981ad4dbaSCK Hu <&mipi_tx0>; 121081ad4dbaSCK Hu clock-names = "engine", "digital", "hs"; 12117fdb1bc3SEnric Balletbo i Serra resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>; 121281ad4dbaSCK Hu phys = <&mipi_tx0>; 121381ad4dbaSCK Hu phy-names = "dphy"; 121481ad4dbaSCK Hu status = "disabled"; 121581ad4dbaSCK Hu }; 121681ad4dbaSCK Hu 121781ad4dbaSCK Hu dsi1: dsi@1401c000 { 121881ad4dbaSCK Hu compatible = "mediatek,mt8173-dsi"; 121981ad4dbaSCK Hu reg = <0 0x1401c000 0 0x1000>; 122081ad4dbaSCK Hu interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 12218b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 122281ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DSI1_ENGINE>, 122381ad4dbaSCK Hu <&mmsys CLK_MM_DSI1_DIGITAL>, 122481ad4dbaSCK Hu <&mipi_tx1>; 122581ad4dbaSCK Hu clock-names = "engine", "digital", "hs"; 1226e4e5d030SChunfeng Yun phys = <&mipi_tx1>; 122781ad4dbaSCK Hu phy-names = "dphy"; 122881ad4dbaSCK Hu status = "disabled"; 122981ad4dbaSCK Hu }; 123081ad4dbaSCK Hu 123181ad4dbaSCK Hu dpi0: dpi@1401d000 { 123281ad4dbaSCK Hu compatible = "mediatek,mt8173-dpi"; 123381ad4dbaSCK Hu reg = <0 0x1401d000 0 0x1000>; 123481ad4dbaSCK Hu interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 12358b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 123681ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DPI_PIXEL>, 123781ad4dbaSCK Hu <&mmsys CLK_MM_DPI_ENGINE>, 123881ad4dbaSCK Hu <&apmixedsys CLK_APMIXED_TVDPLL>; 123981ad4dbaSCK Hu clock-names = "pixel", "engine", "pll"; 124081ad4dbaSCK Hu status = "disabled"; 1241a10b57f4SCK Hu 1242a10b57f4SCK Hu port { 1243a10b57f4SCK Hu dpi0_out: endpoint { 1244a10b57f4SCK Hu remote-endpoint = <&hdmi0_in>; 1245a10b57f4SCK Hu }; 1246a10b57f4SCK Hu }; 124781ad4dbaSCK Hu }; 124881ad4dbaSCK Hu 124961aee934SYH Huang pwm0: pwm@1401e000 { 125061aee934SYH Huang compatible = "mediatek,mt8173-disp-pwm", 125161aee934SYH Huang "mediatek,mt6595-disp-pwm"; 125261aee934SYH Huang reg = <0 0x1401e000 0 0x1000>; 125361aee934SYH Huang #pwm-cells = <2>; 125461aee934SYH Huang clocks = <&mmsys CLK_MM_DISP_PWM026M>, 125561aee934SYH Huang <&mmsys CLK_MM_DISP_PWM0MM>; 125661aee934SYH Huang clock-names = "main", "mm"; 125761aee934SYH Huang status = "disabled"; 125861aee934SYH Huang }; 125961aee934SYH Huang 126061aee934SYH Huang pwm1: pwm@1401f000 { 126161aee934SYH Huang compatible = "mediatek,mt8173-disp-pwm", 126261aee934SYH Huang "mediatek,mt6595-disp-pwm"; 126361aee934SYH Huang reg = <0 0x1401f000 0 0x1000>; 126461aee934SYH Huang #pwm-cells = <2>; 126561aee934SYH Huang clocks = <&mmsys CLK_MM_DISP_PWM126M>, 126661aee934SYH Huang <&mmsys CLK_MM_DISP_PWM1MM>; 126761aee934SYH Huang clock-names = "main", "mm"; 126861aee934SYH Huang status = "disabled"; 126961aee934SYH Huang }; 127061aee934SYH Huang 127181ad4dbaSCK Hu mutex: mutex@14020000 { 127281ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-mutex"; 127381ad4dbaSCK Hu reg = <0 0x14020000 0 0x1000>; 127481ad4dbaSCK Hu interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 12758b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 127681ad4dbaSCK Hu clocks = <&mmsys CLK_MM_MUTEX_32K>; 1277caaff77fSAngeloGioacchino Del Regno mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0 0x1000>; 1278eb4a01afSHsin-Yi Wang mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>, 1279eb4a01afSHsin-Yi Wang <CMDQ_EVENT_MUTEX1_STREAM_EOF>; 128081ad4dbaSCK Hu }; 128181ad4dbaSCK Hu 12825ff6b3a6SYong Wu larb0: larb@14021000 { 12835ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 12845ff6b3a6SYong Wu reg = <0 0x14021000 0 0x1000>; 12855ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 12868b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 12875ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_LARB0>, 12885ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_LARB0>; 12895ff6b3a6SYong Wu clock-names = "apb", "smi"; 12905ff6b3a6SYong Wu }; 12915ff6b3a6SYong Wu 12925ff6b3a6SYong Wu smi_common: smi@14022000 { 12935ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-common"; 12945ff6b3a6SYong Wu reg = <0 0x14022000 0 0x1000>; 12958b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 12965ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_COMMON>, 12975ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_COMMON>; 12985ff6b3a6SYong Wu clock-names = "apb", "smi"; 12995ff6b3a6SYong Wu }; 13005ff6b3a6SYong Wu 130181ad4dbaSCK Hu od@14023000 { 130281ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-od"; 130381ad4dbaSCK Hu reg = <0 0x14023000 0 0x1000>; 130481ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_OD>; 1305ab0c1e34SAngeloGioacchino Del Regno mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>; 130681ad4dbaSCK Hu }; 130781ad4dbaSCK Hu 1308a10b57f4SCK Hu hdmi0: hdmi@14025000 { 1309a10b57f4SCK Hu compatible = "mediatek,mt8173-hdmi"; 1310a10b57f4SCK Hu reg = <0 0x14025000 0 0x400>; 1311a10b57f4SCK Hu interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>; 1312a10b57f4SCK Hu clocks = <&mmsys CLK_MM_HDMI_PIXEL>, 1313a10b57f4SCK Hu <&mmsys CLK_MM_HDMI_PLLCK>, 1314a10b57f4SCK Hu <&mmsys CLK_MM_HDMI_AUDIO>, 1315a10b57f4SCK Hu <&mmsys CLK_MM_HDMI_SPDIF>; 1316a10b57f4SCK Hu clock-names = "pixel", "pll", "bclk", "spdif"; 1317a10b57f4SCK Hu pinctrl-names = "default"; 1318a10b57f4SCK Hu pinctrl-0 = <&hdmi_pin>; 1319a10b57f4SCK Hu phys = <&hdmi_phy>; 1320a10b57f4SCK Hu phy-names = "hdmi"; 1321a10b57f4SCK Hu mediatek,syscon-hdmi = <&mmsys 0x900>; 1322a10b57f4SCK Hu assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; 1323a10b57f4SCK Hu assigned-clock-parents = <&hdmi_phy>; 1324a10b57f4SCK Hu status = "disabled"; 1325a10b57f4SCK Hu 1326a10b57f4SCK Hu ports { 1327a10b57f4SCK Hu #address-cells = <1>; 1328a10b57f4SCK Hu #size-cells = <0>; 1329a10b57f4SCK Hu 1330a10b57f4SCK Hu port@0 { 1331a10b57f4SCK Hu reg = <0>; 1332a10b57f4SCK Hu 1333a10b57f4SCK Hu hdmi0_in: endpoint { 1334a10b57f4SCK Hu remote-endpoint = <&dpi0_out>; 1335a10b57f4SCK Hu }; 1336a10b57f4SCK Hu }; 1337a10b57f4SCK Hu }; 1338a10b57f4SCK Hu }; 1339a10b57f4SCK Hu 13405ff6b3a6SYong Wu larb4: larb@14027000 { 13415ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 13425ff6b3a6SYong Wu reg = <0 0x14027000 0 0x1000>; 13435ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 13448b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 13455ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_LARB4>, 13465ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_LARB4>; 13475ff6b3a6SYong Wu clock-names = "apb", "smi"; 13485ff6b3a6SYong Wu }; 13495ff6b3a6SYong Wu 135067e56c56SJames Liao imgsys: clock-controller@15000000 { 135167e56c56SJames Liao compatible = "mediatek,mt8173-imgsys", "syscon"; 135267e56c56SJames Liao reg = <0 0x15000000 0 0x1000>; 135367e56c56SJames Liao #clock-cells = <1>; 135467e56c56SJames Liao }; 135567e56c56SJames Liao 13565ff6b3a6SYong Wu larb2: larb@15001000 { 13575ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 13585ff6b3a6SYong Wu reg = <0 0x15001000 0 0x1000>; 13595ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 13608b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_ISP>; 13615ff6b3a6SYong Wu clocks = <&imgsys CLK_IMG_LARB2_SMI>, 13625ff6b3a6SYong Wu <&imgsys CLK_IMG_LARB2_SMI>; 13635ff6b3a6SYong Wu clock-names = "apb", "smi"; 13645ff6b3a6SYong Wu }; 13655ff6b3a6SYong Wu 136667e56c56SJames Liao vdecsys: clock-controller@16000000 { 136767e56c56SJames Liao compatible = "mediatek,mt8173-vdecsys", "syscon"; 136867e56c56SJames Liao reg = <0 0x16000000 0 0x1000>; 136967e56c56SJames Liao #clock-cells = <1>; 137067e56c56SJames Liao }; 137167e56c56SJames Liao 137260eaae2bSTiffany Lin vcodec_dec: vcodec@16000000 { 137360eaae2bSTiffany Lin compatible = "mediatek,mt8173-vcodec-dec"; 137460eaae2bSTiffany Lin reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */ 137560eaae2bSTiffany Lin <0 0x16020000 0 0x1000>, /* VDEC_MISC */ 137660eaae2bSTiffany Lin <0 0x16021000 0 0x800>, /* VDEC_LD */ 137760eaae2bSTiffany Lin <0 0x16021800 0 0x800>, /* VDEC_TOP */ 137860eaae2bSTiffany Lin <0 0x16022000 0 0x1000>, /* VDEC_CM */ 137960eaae2bSTiffany Lin <0 0x16023000 0 0x1000>, /* VDEC_AD */ 138060eaae2bSTiffany Lin <0 0x16024000 0 0x1000>, /* VDEC_AV */ 138160eaae2bSTiffany Lin <0 0x16025000 0 0x1000>, /* VDEC_PP */ 138260eaae2bSTiffany Lin <0 0x16026800 0 0x800>, /* VDEC_HWD */ 138360eaae2bSTiffany Lin <0 0x16027000 0 0x800>, /* VDEC_HWQ */ 138460eaae2bSTiffany Lin <0 0x16027800 0 0x800>, /* VDEC_HWB */ 138560eaae2bSTiffany Lin <0 0x16028400 0 0x400>; /* VDEC_HWG */ 138660eaae2bSTiffany Lin interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; 138760eaae2bSTiffany Lin iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, 138860eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_PP_EXT>, 138960eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, 139060eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, 139160eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, 139260eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, 139360eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, 139460eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; 139560eaae2bSTiffany Lin mediatek,vpu = <&vpu>; 13968b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>; 139760eaae2bSTiffany Lin clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, 139860eaae2bSTiffany Lin <&topckgen CLK_TOP_UNIVPLL_D2>, 139960eaae2bSTiffany Lin <&topckgen CLK_TOP_CCI400_SEL>, 140060eaae2bSTiffany Lin <&topckgen CLK_TOP_VDEC_SEL>, 140160eaae2bSTiffany Lin <&topckgen CLK_TOP_VCODECPLL>, 140260eaae2bSTiffany Lin <&apmixedsys CLK_APMIXED_VENCPLL>, 140360eaae2bSTiffany Lin <&topckgen CLK_TOP_VENC_LT_SEL>, 140460eaae2bSTiffany Lin <&topckgen CLK_TOP_VCODECPLL_370P5>; 140560eaae2bSTiffany Lin clock-names = "vcodecpll", 140660eaae2bSTiffany Lin "univpll_d2", 140760eaae2bSTiffany Lin "clk_cci400_sel", 140860eaae2bSTiffany Lin "vdec_sel", 140960eaae2bSTiffany Lin "vdecpll", 141060eaae2bSTiffany Lin "vencpll", 141160eaae2bSTiffany Lin "venc_lt_sel", 141260eaae2bSTiffany Lin "vdec_bus_clk_src"; 1413fbbad028SYunfei Dong assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>, 1414fbbad028SYunfei Dong <&topckgen CLK_TOP_CCI400_SEL>, 1415fbbad028SYunfei Dong <&topckgen CLK_TOP_VDEC_SEL>, 1416fbbad028SYunfei Dong <&apmixedsys CLK_APMIXED_VCODECPLL>, 1417fbbad028SYunfei Dong <&apmixedsys CLK_APMIXED_VENCPLL>; 1418fbbad028SYunfei Dong assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>, 1419fbbad028SYunfei Dong <&topckgen CLK_TOP_UNIVPLL_D2>, 1420fbbad028SYunfei Dong <&topckgen CLK_TOP_VCODECPLL>; 1421fbbad028SYunfei Dong assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>; 142260eaae2bSTiffany Lin }; 142360eaae2bSTiffany Lin 14245ff6b3a6SYong Wu larb1: larb@16010000 { 14255ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 14265ff6b3a6SYong Wu reg = <0 0x16010000 0 0x1000>; 14275ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 14288b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>; 14295ff6b3a6SYong Wu clocks = <&vdecsys CLK_VDEC_CKEN>, 14305ff6b3a6SYong Wu <&vdecsys CLK_VDEC_LARB_CKEN>; 14315ff6b3a6SYong Wu clock-names = "apb", "smi"; 14325ff6b3a6SYong Wu }; 14335ff6b3a6SYong Wu 143467e56c56SJames Liao vencsys: clock-controller@18000000 { 143567e56c56SJames Liao compatible = "mediatek,mt8173-vencsys", "syscon"; 143667e56c56SJames Liao reg = <0 0x18000000 0 0x1000>; 143767e56c56SJames Liao #clock-cells = <1>; 143867e56c56SJames Liao }; 143967e56c56SJames Liao 14405ff6b3a6SYong Wu larb3: larb@18001000 { 14415ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 14425ff6b3a6SYong Wu reg = <0 0x18001000 0 0x1000>; 14435ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 14448b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_VENC>; 14455ff6b3a6SYong Wu clocks = <&vencsys CLK_VENC_CKE1>, 14465ff6b3a6SYong Wu <&vencsys CLK_VENC_CKE0>; 14475ff6b3a6SYong Wu clock-names = "apb", "smi"; 14485ff6b3a6SYong Wu }; 14495ff6b3a6SYong Wu 1450e6f73028SIrui Wang vcodec_enc_avc: vcodec@18002000 { 14518eb80252STiffany Lin compatible = "mediatek,mt8173-vcodec-enc"; 1452e6f73028SIrui Wang reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */ 1453e6f73028SIrui Wang interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; 14548eb80252STiffany Lin iommus = <&iommu M4U_PORT_VENC_RCPU>, 14558eb80252STiffany Lin <&iommu M4U_PORT_VENC_REC>, 14568eb80252STiffany Lin <&iommu M4U_PORT_VENC_BSDMA>, 14578eb80252STiffany Lin <&iommu M4U_PORT_VENC_SV_COMV>, 14588eb80252STiffany Lin <&iommu M4U_PORT_VENC_RD_COMV>, 14598eb80252STiffany Lin <&iommu M4U_PORT_VENC_CUR_LUMA>, 14608eb80252STiffany Lin <&iommu M4U_PORT_VENC_CUR_CHROMA>, 14618eb80252STiffany Lin <&iommu M4U_PORT_VENC_REF_LUMA>, 14628eb80252STiffany Lin <&iommu M4U_PORT_VENC_REF_CHROMA>, 14638eb80252STiffany Lin <&iommu M4U_PORT_VENC_NBM_RDMA>, 1464e6f73028SIrui Wang <&iommu M4U_PORT_VENC_NBM_WDMA>; 14658eb80252STiffany Lin mediatek,vpu = <&vpu>; 1466e6f73028SIrui Wang clocks = <&topckgen CLK_TOP_VENC_SEL>; 1467e6f73028SIrui Wang clock-names = "venc_sel"; 1468e6f73028SIrui Wang assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; 1469e6f73028SIrui Wang assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>; 1470dab2782bSAllen-KH Cheng power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 14718eb80252STiffany Lin }; 14728eb80252STiffany Lin 14731180beb0SHsin-Yi Wang jpegdec: jpegdec@18004000 { 14741180beb0SHsin-Yi Wang compatible = "mediatek,mt8173-jpgdec"; 14751180beb0SHsin-Yi Wang reg = <0 0x18004000 0 0x1000>; 14761180beb0SHsin-Yi Wang interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW>; 14771180beb0SHsin-Yi Wang clocks = <&vencsys CLK_VENC_CKE0>, 14781180beb0SHsin-Yi Wang <&vencsys CLK_VENC_CKE3>; 14791180beb0SHsin-Yi Wang clock-names = "jpgdec-smi", 14801180beb0SHsin-Yi Wang "jpgdec"; 14818b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_VENC>; 14821180beb0SHsin-Yi Wang iommus = <&iommu M4U_PORT_JPGDEC_WDMA>, 14831180beb0SHsin-Yi Wang <&iommu M4U_PORT_JPGDEC_BSDMA>; 14841180beb0SHsin-Yi Wang }; 14851180beb0SHsin-Yi Wang 148667e56c56SJames Liao vencltsys: clock-controller@19000000 { 148767e56c56SJames Liao compatible = "mediatek,mt8173-vencltsys", "syscon"; 148867e56c56SJames Liao reg = <0 0x19000000 0 0x1000>; 148967e56c56SJames Liao #clock-cells = <1>; 149067e56c56SJames Liao }; 14915ff6b3a6SYong Wu 14925ff6b3a6SYong Wu larb5: larb@19001000 { 14935ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 14945ff6b3a6SYong Wu reg = <0 0x19001000 0 0x1000>; 14955ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 14968b656264SEnric Balletbo i Serra power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>; 14975ff6b3a6SYong Wu clocks = <&vencltsys CLK_VENCLT_CKE1>, 14985ff6b3a6SYong Wu <&vencltsys CLK_VENCLT_CKE0>; 14995ff6b3a6SYong Wu clock-names = "apb", "smi"; 15005ff6b3a6SYong Wu }; 1501e6f73028SIrui Wang 1502e6f73028SIrui Wang vcodec_enc_vp8: vcodec@19002000 { 1503e6f73028SIrui Wang compatible = "mediatek,mt8173-vcodec-enc-vp8"; 1504e6f73028SIrui Wang reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ 1505e6f73028SIrui Wang interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; 1506e6f73028SIrui Wang iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>, 1507e6f73028SIrui Wang <&iommu M4U_PORT_VENC_REC_FRM_SET2>, 1508e6f73028SIrui Wang <&iommu M4U_PORT_VENC_BSDMA_SET2>, 1509e6f73028SIrui Wang <&iommu M4U_PORT_VENC_SV_COMA_SET2>, 1510e6f73028SIrui Wang <&iommu M4U_PORT_VENC_RD_COMA_SET2>, 1511e6f73028SIrui Wang <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, 1512e6f73028SIrui Wang <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, 1513e6f73028SIrui Wang <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, 1514e6f73028SIrui Wang <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; 1515e6f73028SIrui Wang mediatek,vpu = <&vpu>; 1516e6f73028SIrui Wang clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; 1517e6f73028SIrui Wang clock-names = "venc_lt_sel"; 1518e6f73028SIrui Wang assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; 1519e6f73028SIrui Wang assigned-clock-parents = 1520e6f73028SIrui Wang <&topckgen CLK_TOP_VCODECPLL_370P5>; 1521dab2782bSAllen-KH Cheng power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; 1522e6f73028SIrui Wang }; 1523b3a37248SEddie Huang }; 1524b3a37248SEddie Huang}; 1525