1b3a37248SEddie Huang/* 2b3a37248SEddie Huang * Copyright (c) 2014 MediaTek Inc. 3b3a37248SEddie Huang * Author: Eddie Huang <eddie.huang@mediatek.com> 4b3a37248SEddie Huang * 5b3a37248SEddie Huang * This program is free software; you can redistribute it and/or modify 6b3a37248SEddie Huang * it under the terms of the GNU General Public License version 2 as 7b3a37248SEddie Huang * published by the Free Software Foundation. 8b3a37248SEddie Huang * 9b3a37248SEddie Huang * This program is distributed in the hope that it will be useful, 10b3a37248SEddie Huang * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11b3a37248SEddie Huang * GNU General Public License for more details. 12b3a37248SEddie Huang */ 13b3a37248SEddie Huang 14f2ce7014SSascha Hauer#include <dt-bindings/clock/mt8173-clk.h> 15b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/irq.h> 16b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/arm-gic.h> 175ff6b3a6SYong Wu#include <dt-bindings/memory/mt8173-larb-port.h> 18bfcce47aSChunfeng Yun#include <dt-bindings/phy/phy.h> 19c02e0e86SKoro Chen#include <dt-bindings/power/mt8173-power.h> 20967313e2SPhilipp Zabel#include <dt-bindings/reset/mt8173-resets.h> 21c2e66b8fSHoulong Wei#include <dt-bindings/gce/mt8173-gce.h> 22359f9365SHongzhou Yang#include "mt8173-pinfunc.h" 23b3a37248SEddie Huang 24b3a37248SEddie Huang/ { 25b3a37248SEddie Huang compatible = "mediatek,mt8173"; 26b3a37248SEddie Huang interrupt-parent = <&sysirq>; 27b3a37248SEddie Huang #address-cells = <2>; 28b3a37248SEddie Huang #size-cells = <2>; 29b3a37248SEddie Huang 3081ad4dbaSCK Hu aliases { 3181ad4dbaSCK Hu ovl0 = &ovl0; 3281ad4dbaSCK Hu ovl1 = &ovl1; 3381ad4dbaSCK Hu rdma0 = &rdma0; 3481ad4dbaSCK Hu rdma1 = &rdma1; 3581ad4dbaSCK Hu rdma2 = &rdma2; 3681ad4dbaSCK Hu wdma0 = &wdma0; 3781ad4dbaSCK Hu wdma1 = &wdma1; 3881ad4dbaSCK Hu color0 = &color0; 3981ad4dbaSCK Hu color1 = &color1; 4081ad4dbaSCK Hu split0 = &split0; 4181ad4dbaSCK Hu split1 = &split1; 4281ad4dbaSCK Hu dpi0 = &dpi0; 4381ad4dbaSCK Hu dsi0 = &dsi0; 4481ad4dbaSCK Hu dsi1 = &dsi1; 45989b292aSMinghsiu Tsai mdp_rdma0 = &mdp_rdma0; 46989b292aSMinghsiu Tsai mdp_rdma1 = &mdp_rdma1; 47989b292aSMinghsiu Tsai mdp_rsz0 = &mdp_rsz0; 48989b292aSMinghsiu Tsai mdp_rsz1 = &mdp_rsz1; 49989b292aSMinghsiu Tsai mdp_rsz2 = &mdp_rsz2; 50989b292aSMinghsiu Tsai mdp_wdma0 = &mdp_wdma0; 51989b292aSMinghsiu Tsai mdp_wrot0 = &mdp_wrot0; 52989b292aSMinghsiu Tsai mdp_wrot1 = &mdp_wrot1; 5381ad4dbaSCK Hu }; 5481ad4dbaSCK Hu 55da85a3afSAndrew-sh Cheng cluster0_opp: opp_table0 { 56da85a3afSAndrew-sh Cheng compatible = "operating-points-v2"; 57da85a3afSAndrew-sh Cheng opp-shared; 58da85a3afSAndrew-sh Cheng opp-507000000 { 59da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <507000000>; 60da85a3afSAndrew-sh Cheng opp-microvolt = <859000>; 61da85a3afSAndrew-sh Cheng }; 62da85a3afSAndrew-sh Cheng opp-702000000 { 63da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <702000000>; 64da85a3afSAndrew-sh Cheng opp-microvolt = <908000>; 65da85a3afSAndrew-sh Cheng }; 66da85a3afSAndrew-sh Cheng opp-1001000000 { 67da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1001000000>; 68da85a3afSAndrew-sh Cheng opp-microvolt = <983000>; 69da85a3afSAndrew-sh Cheng }; 70da85a3afSAndrew-sh Cheng opp-1105000000 { 71da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1105000000>; 72da85a3afSAndrew-sh Cheng opp-microvolt = <1009000>; 73da85a3afSAndrew-sh Cheng }; 74da85a3afSAndrew-sh Cheng opp-1209000000 { 75da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1209000000>; 76da85a3afSAndrew-sh Cheng opp-microvolt = <1034000>; 77da85a3afSAndrew-sh Cheng }; 78da85a3afSAndrew-sh Cheng opp-1300000000 { 79da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1300000000>; 80da85a3afSAndrew-sh Cheng opp-microvolt = <1057000>; 81da85a3afSAndrew-sh Cheng }; 82da85a3afSAndrew-sh Cheng opp-1508000000 { 83da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1508000000>; 84da85a3afSAndrew-sh Cheng opp-microvolt = <1109000>; 85da85a3afSAndrew-sh Cheng }; 86da85a3afSAndrew-sh Cheng opp-1703000000 { 87da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1703000000>; 88da85a3afSAndrew-sh Cheng opp-microvolt = <1125000>; 89da85a3afSAndrew-sh Cheng }; 90da85a3afSAndrew-sh Cheng }; 91da85a3afSAndrew-sh Cheng 92da85a3afSAndrew-sh Cheng cluster1_opp: opp_table1 { 93da85a3afSAndrew-sh Cheng compatible = "operating-points-v2"; 94da85a3afSAndrew-sh Cheng opp-shared; 95da85a3afSAndrew-sh Cheng opp-507000000 { 96da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <507000000>; 97da85a3afSAndrew-sh Cheng opp-microvolt = <828000>; 98da85a3afSAndrew-sh Cheng }; 99da85a3afSAndrew-sh Cheng opp-702000000 { 100da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <702000000>; 101da85a3afSAndrew-sh Cheng opp-microvolt = <867000>; 102da85a3afSAndrew-sh Cheng }; 103da85a3afSAndrew-sh Cheng opp-1001000000 { 104da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1001000000>; 105da85a3afSAndrew-sh Cheng opp-microvolt = <927000>; 106da85a3afSAndrew-sh Cheng }; 107da85a3afSAndrew-sh Cheng opp-1209000000 { 108da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1209000000>; 109da85a3afSAndrew-sh Cheng opp-microvolt = <968000>; 110da85a3afSAndrew-sh Cheng }; 111da85a3afSAndrew-sh Cheng opp-1404000000 { 112da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1404000000>; 113da85a3afSAndrew-sh Cheng opp-microvolt = <1007000>; 114da85a3afSAndrew-sh Cheng }; 115da85a3afSAndrew-sh Cheng opp-1612000000 { 116da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1612000000>; 117da85a3afSAndrew-sh Cheng opp-microvolt = <1049000>; 118da85a3afSAndrew-sh Cheng }; 119da85a3afSAndrew-sh Cheng opp-1807000000 { 120da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1807000000>; 121da85a3afSAndrew-sh Cheng opp-microvolt = <1089000>; 122da85a3afSAndrew-sh Cheng }; 123da85a3afSAndrew-sh Cheng opp-2106000000 { 124da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <2106000000>; 125da85a3afSAndrew-sh Cheng opp-microvolt = <1125000>; 126da85a3afSAndrew-sh Cheng }; 127da85a3afSAndrew-sh Cheng }; 128da85a3afSAndrew-sh Cheng 129b3a37248SEddie Huang cpus { 130b3a37248SEddie Huang #address-cells = <1>; 131b3a37248SEddie Huang #size-cells = <0>; 132b3a37248SEddie Huang 133b3a37248SEddie Huang cpu-map { 134b3a37248SEddie Huang cluster0 { 135b3a37248SEddie Huang core0 { 136b3a37248SEddie Huang cpu = <&cpu0>; 137b3a37248SEddie Huang }; 138b3a37248SEddie Huang core1 { 139b3a37248SEddie Huang cpu = <&cpu1>; 140b3a37248SEddie Huang }; 141b3a37248SEddie Huang }; 142b3a37248SEddie Huang 143b3a37248SEddie Huang cluster1 { 144b3a37248SEddie Huang core0 { 145b3a37248SEddie Huang cpu = <&cpu2>; 146b3a37248SEddie Huang }; 147b3a37248SEddie Huang core1 { 148b3a37248SEddie Huang cpu = <&cpu3>; 149b3a37248SEddie Huang }; 150b3a37248SEddie Huang }; 151b3a37248SEddie Huang }; 152b3a37248SEddie Huang 153b3a37248SEddie Huang cpu0: cpu@0 { 154b3a37248SEddie Huang device_type = "cpu"; 155b3a37248SEddie Huang compatible = "arm,cortex-a53"; 156b3a37248SEddie Huang reg = <0x000>; 157ad4df7a5SHoward Chen enable-method = "psci"; 158ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 159acbf76eeSArnd Bergmann #cooling-cells = <2>; 160da85a3afSAndrew-sh Cheng clocks = <&infracfg CLK_INFRA_CA53SEL>, 161da85a3afSAndrew-sh Cheng <&apmixedsys CLK_APMIXED_MAINPLL>; 162da85a3afSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 163da85a3afSAndrew-sh Cheng operating-points-v2 = <&cluster0_opp>; 164b3a37248SEddie Huang }; 165b3a37248SEddie Huang 166b3a37248SEddie Huang cpu1: cpu@1 { 167b3a37248SEddie Huang device_type = "cpu"; 168b3a37248SEddie Huang compatible = "arm,cortex-a53"; 169b3a37248SEddie Huang reg = <0x001>; 170b3a37248SEddie Huang enable-method = "psci"; 171ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 172a06e5c05SViresh Kumar #cooling-cells = <2>; 173da85a3afSAndrew-sh Cheng clocks = <&infracfg CLK_INFRA_CA53SEL>, 174da85a3afSAndrew-sh Cheng <&apmixedsys CLK_APMIXED_MAINPLL>; 175da85a3afSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 176da85a3afSAndrew-sh Cheng operating-points-v2 = <&cluster0_opp>; 177b3a37248SEddie Huang }; 178b3a37248SEddie Huang 179b3a37248SEddie Huang cpu2: cpu@100 { 180b3a37248SEddie Huang device_type = "cpu"; 181b3a37248SEddie Huang compatible = "arm,cortex-a57"; 182b3a37248SEddie Huang reg = <0x100>; 183b3a37248SEddie Huang enable-method = "psci"; 184ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 185acbf76eeSArnd Bergmann #cooling-cells = <2>; 186da85a3afSAndrew-sh Cheng clocks = <&infracfg CLK_INFRA_CA57SEL>, 187da85a3afSAndrew-sh Cheng <&apmixedsys CLK_APMIXED_MAINPLL>; 188da85a3afSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 189da85a3afSAndrew-sh Cheng operating-points-v2 = <&cluster1_opp>; 190b3a37248SEddie Huang }; 191b3a37248SEddie Huang 192b3a37248SEddie Huang cpu3: cpu@101 { 193b3a37248SEddie Huang device_type = "cpu"; 194b3a37248SEddie Huang compatible = "arm,cortex-a57"; 195b3a37248SEddie Huang reg = <0x101>; 196b3a37248SEddie Huang enable-method = "psci"; 197ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 198a06e5c05SViresh Kumar #cooling-cells = <2>; 199da85a3afSAndrew-sh Cheng clocks = <&infracfg CLK_INFRA_CA57SEL>, 200da85a3afSAndrew-sh Cheng <&apmixedsys CLK_APMIXED_MAINPLL>; 201da85a3afSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 202da85a3afSAndrew-sh Cheng operating-points-v2 = <&cluster1_opp>; 203ad4df7a5SHoward Chen }; 204ad4df7a5SHoward Chen 205ad4df7a5SHoward Chen idle-states { 206a13f18f5SLorenzo Pieralisi entry-method = "psci"; 207ad4df7a5SHoward Chen 208ad4df7a5SHoward Chen CPU_SLEEP_0: cpu-sleep-0 { 209ad4df7a5SHoward Chen compatible = "arm,idle-state"; 210ad4df7a5SHoward Chen local-timer-stop; 211ad4df7a5SHoward Chen entry-latency-us = <639>; 212ad4df7a5SHoward Chen exit-latency-us = <680>; 213ad4df7a5SHoward Chen min-residency-us = <1088>; 214ad4df7a5SHoward Chen arm,psci-suspend-param = <0x0010000>; 215ad4df7a5SHoward Chen }; 216b3a37248SEddie Huang }; 217b3a37248SEddie Huang }; 218b3a37248SEddie Huang 219b3a37248SEddie Huang psci { 22005bdabe7SFan Chen compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 221b3a37248SEddie Huang method = "smc"; 222b3a37248SEddie Huang cpu_suspend = <0x84000001>; 223b3a37248SEddie Huang cpu_off = <0x84000002>; 224b3a37248SEddie Huang cpu_on = <0x84000003>; 225b3a37248SEddie Huang }; 226b3a37248SEddie Huang 227f2ce7014SSascha Hauer clk26m: oscillator@0 { 228f2ce7014SSascha Hauer compatible = "fixed-clock"; 229f2ce7014SSascha Hauer #clock-cells = <0>; 230f2ce7014SSascha Hauer clock-frequency = <26000000>; 231f2ce7014SSascha Hauer clock-output-names = "clk26m"; 232f2ce7014SSascha Hauer }; 233f2ce7014SSascha Hauer 234f2ce7014SSascha Hauer clk32k: oscillator@1 { 235f2ce7014SSascha Hauer compatible = "fixed-clock"; 236f2ce7014SSascha Hauer #clock-cells = <0>; 237f2ce7014SSascha Hauer clock-frequency = <32000>; 238f2ce7014SSascha Hauer clock-output-names = "clk32k"; 239f2ce7014SSascha Hauer }; 240f2ce7014SSascha Hauer 24167e56c56SJames Liao cpum_ck: oscillator@2 { 24267e56c56SJames Liao compatible = "fixed-clock"; 24367e56c56SJames Liao #clock-cells = <0>; 24467e56c56SJames Liao clock-frequency = <0>; 24567e56c56SJames Liao clock-output-names = "cpum_ck"; 24667e56c56SJames Liao }; 24767e56c56SJames Liao 248962f5143Sdawei.chien@mediatek.com thermal-zones { 249962f5143Sdawei.chien@mediatek.com cpu_thermal: cpu_thermal { 250962f5143Sdawei.chien@mediatek.com polling-delay-passive = <1000>; /* milliseconds */ 251962f5143Sdawei.chien@mediatek.com polling-delay = <1000>; /* milliseconds */ 252962f5143Sdawei.chien@mediatek.com 253962f5143Sdawei.chien@mediatek.com thermal-sensors = <&thermal>; 254962f5143Sdawei.chien@mediatek.com sustainable-power = <1500>; /* milliwatts */ 255962f5143Sdawei.chien@mediatek.com 256962f5143Sdawei.chien@mediatek.com trips { 257962f5143Sdawei.chien@mediatek.com threshold: trip-point@0 { 258962f5143Sdawei.chien@mediatek.com temperature = <68000>; 259962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 260962f5143Sdawei.chien@mediatek.com type = "passive"; 261962f5143Sdawei.chien@mediatek.com }; 262962f5143Sdawei.chien@mediatek.com 263962f5143Sdawei.chien@mediatek.com target: trip-point@1 { 264962f5143Sdawei.chien@mediatek.com temperature = <85000>; 265962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 266962f5143Sdawei.chien@mediatek.com type = "passive"; 267962f5143Sdawei.chien@mediatek.com }; 268962f5143Sdawei.chien@mediatek.com 269962f5143Sdawei.chien@mediatek.com cpu_crit: cpu_crit@0 { 270962f5143Sdawei.chien@mediatek.com temperature = <115000>; 271962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 272962f5143Sdawei.chien@mediatek.com type = "critical"; 273962f5143Sdawei.chien@mediatek.com }; 274962f5143Sdawei.chien@mediatek.com }; 275962f5143Sdawei.chien@mediatek.com 276962f5143Sdawei.chien@mediatek.com cooling-maps { 277962f5143Sdawei.chien@mediatek.com map@0 { 278962f5143Sdawei.chien@mediatek.com trip = <&target>; 279962f5143Sdawei.chien@mediatek.com cooling-device = <&cpu0 0 0>; 2807fcef92dSDaniel Kurtz contribution = <3072>; 281962f5143Sdawei.chien@mediatek.com }; 282962f5143Sdawei.chien@mediatek.com map@1 { 283962f5143Sdawei.chien@mediatek.com trip = <&target>; 284962f5143Sdawei.chien@mediatek.com cooling-device = <&cpu2 0 0>; 2857fcef92dSDaniel Kurtz contribution = <1024>; 286962f5143Sdawei.chien@mediatek.com }; 287962f5143Sdawei.chien@mediatek.com }; 288962f5143Sdawei.chien@mediatek.com }; 289962f5143Sdawei.chien@mediatek.com }; 290962f5143Sdawei.chien@mediatek.com 291404b2819SAndrew-CT Chen reserved-memory { 292404b2819SAndrew-CT Chen #address-cells = <2>; 293404b2819SAndrew-CT Chen #size-cells = <2>; 294404b2819SAndrew-CT Chen ranges; 295404b2819SAndrew-CT Chen vpu_dma_reserved: vpu_dma_mem_region { 296404b2819SAndrew-CT Chen compatible = "shared-dma-pool"; 297404b2819SAndrew-CT Chen reg = <0 0xb7000000 0 0x500000>; 298404b2819SAndrew-CT Chen alignment = <0x1000>; 299404b2819SAndrew-CT Chen no-map; 300404b2819SAndrew-CT Chen }; 301404b2819SAndrew-CT Chen }; 302404b2819SAndrew-CT Chen 303b3a37248SEddie Huang timer { 304b3a37248SEddie Huang compatible = "arm,armv8-timer"; 305b3a37248SEddie Huang interrupt-parent = <&gic>; 306b3a37248SEddie Huang interrupts = <GIC_PPI 13 307b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 308b3a37248SEddie Huang <GIC_PPI 14 309b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 310b3a37248SEddie Huang <GIC_PPI 11 311b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 312b3a37248SEddie Huang <GIC_PPI 10 313b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 314b3a37248SEddie Huang }; 315b3a37248SEddie Huang 316b3a37248SEddie Huang soc { 317b3a37248SEddie Huang #address-cells = <2>; 318b3a37248SEddie Huang #size-cells = <2>; 319b3a37248SEddie Huang compatible = "simple-bus"; 320b3a37248SEddie Huang ranges; 321b3a37248SEddie Huang 322f2ce7014SSascha Hauer topckgen: clock-controller@10000000 { 323f2ce7014SSascha Hauer compatible = "mediatek,mt8173-topckgen"; 324f2ce7014SSascha Hauer reg = <0 0x10000000 0 0x1000>; 325f2ce7014SSascha Hauer #clock-cells = <1>; 326f2ce7014SSascha Hauer }; 327f2ce7014SSascha Hauer 328f2ce7014SSascha Hauer infracfg: power-controller@10001000 { 329f2ce7014SSascha Hauer compatible = "mediatek,mt8173-infracfg", "syscon"; 330f2ce7014SSascha Hauer reg = <0 0x10001000 0 0x1000>; 331f2ce7014SSascha Hauer #clock-cells = <1>; 332f2ce7014SSascha Hauer #reset-cells = <1>; 333f2ce7014SSascha Hauer }; 334f2ce7014SSascha Hauer 335f2ce7014SSascha Hauer pericfg: power-controller@10003000 { 336f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pericfg", "syscon"; 337f2ce7014SSascha Hauer reg = <0 0x10003000 0 0x1000>; 338f2ce7014SSascha Hauer #clock-cells = <1>; 339f2ce7014SSascha Hauer #reset-cells = <1>; 340f2ce7014SSascha Hauer }; 341f2ce7014SSascha Hauer 342f2ce7014SSascha Hauer syscfg_pctl_a: syscfg_pctl_a@10005000 { 343f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 344f2ce7014SSascha Hauer reg = <0 0x10005000 0 0x1000>; 345f2ce7014SSascha Hauer }; 346f2ce7014SSascha Hauer 3479977a8c3SMathieu Malaterre pio: pinctrl@10005000 { 348359f9365SHongzhou Yang compatible = "mediatek,mt8173-pinctrl"; 3496769b93cSYingjoe Chen reg = <0 0x1000b000 0 0x1000>; 350359f9365SHongzhou Yang mediatek,pctl-regmap = <&syscfg_pctl_a>; 351359f9365SHongzhou Yang pins-are-numbered; 352359f9365SHongzhou Yang gpio-controller; 353359f9365SHongzhou Yang #gpio-cells = <2>; 354359f9365SHongzhou Yang interrupt-controller; 355359f9365SHongzhou Yang #interrupt-cells = <2>; 356359f9365SHongzhou Yang interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 357359f9365SHongzhou Yang <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 358359f9365SHongzhou Yang <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 359091cf598SEddie Huang 360a10b57f4SCK Hu hdmi_pin: xxx { 361a10b57f4SCK Hu 362a10b57f4SCK Hu /*hdmi htplg pin*/ 363a10b57f4SCK Hu pins1 { 364a10b57f4SCK Hu pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>; 365a10b57f4SCK Hu input-enable; 366a10b57f4SCK Hu bias-pull-down; 367a10b57f4SCK Hu }; 368a10b57f4SCK Hu }; 369a10b57f4SCK Hu 370091cf598SEddie Huang i2c0_pins_a: i2c0 { 371091cf598SEddie Huang pins1 { 372091cf598SEddie Huang pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 373091cf598SEddie Huang <MT8173_PIN_46_SCL0__FUNC_SCL0>; 374091cf598SEddie Huang bias-disable; 375091cf598SEddie Huang }; 376359f9365SHongzhou Yang }; 377359f9365SHongzhou Yang 378091cf598SEddie Huang i2c1_pins_a: i2c1 { 379091cf598SEddie Huang pins1 { 380091cf598SEddie Huang pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 381091cf598SEddie Huang <MT8173_PIN_126_SCL1__FUNC_SCL1>; 382091cf598SEddie Huang bias-disable; 383091cf598SEddie Huang }; 384091cf598SEddie Huang }; 385091cf598SEddie Huang 386091cf598SEddie Huang i2c2_pins_a: i2c2 { 387091cf598SEddie Huang pins1 { 388091cf598SEddie Huang pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 389091cf598SEddie Huang <MT8173_PIN_44_SCL2__FUNC_SCL2>; 390091cf598SEddie Huang bias-disable; 391091cf598SEddie Huang }; 392091cf598SEddie Huang }; 393091cf598SEddie Huang 394091cf598SEddie Huang i2c3_pins_a: i2c3 { 395091cf598SEddie Huang pins1 { 396091cf598SEddie Huang pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 397091cf598SEddie Huang <MT8173_PIN_107_SCL3__FUNC_SCL3>; 398091cf598SEddie Huang bias-disable; 399091cf598SEddie Huang }; 400091cf598SEddie Huang }; 401091cf598SEddie Huang 402091cf598SEddie Huang i2c4_pins_a: i2c4 { 403091cf598SEddie Huang pins1 { 404091cf598SEddie Huang pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 405091cf598SEddie Huang <MT8173_PIN_134_SCL4__FUNC_SCL4>; 406091cf598SEddie Huang bias-disable; 407091cf598SEddie Huang }; 408091cf598SEddie Huang }; 409091cf598SEddie Huang 410091cf598SEddie Huang i2c6_pins_a: i2c6 { 411091cf598SEddie Huang pins1 { 412091cf598SEddie Huang pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 413091cf598SEddie Huang <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 414091cf598SEddie Huang bias-disable; 415091cf598SEddie Huang }; 416091cf598SEddie Huang }; 4176769b93cSYingjoe Chen }; 4186769b93cSYingjoe Chen 419c010ff53SSascha Hauer scpsys: scpsys@10006000 { 420c010ff53SSascha Hauer compatible = "mediatek,mt8173-scpsys"; 421c010ff53SSascha Hauer #power-domain-cells = <1>; 422c010ff53SSascha Hauer reg = <0 0x10006000 0 0x1000>; 423c010ff53SSascha Hauer clocks = <&clk26m>, 424e34573c9SJames Liao <&topckgen CLK_TOP_MM_SEL>, 425e34573c9SJames Liao <&topckgen CLK_TOP_VENC_SEL>, 426e34573c9SJames Liao <&topckgen CLK_TOP_VENC_LT_SEL>; 427e34573c9SJames Liao clock-names = "mfg", "mm", "venc", "venc_lt"; 428c010ff53SSascha Hauer infracfg = <&infracfg>; 429c010ff53SSascha Hauer }; 430c010ff53SSascha Hauer 43113421b3eSEddie Huang watchdog: watchdog@10007000 { 43213421b3eSEddie Huang compatible = "mediatek,mt8173-wdt", 43313421b3eSEddie Huang "mediatek,mt6589-wdt"; 43413421b3eSEddie Huang reg = <0 0x10007000 0 0x100>; 43513421b3eSEddie Huang }; 43613421b3eSEddie Huang 437b2c76e27SDaniel Kurtz timer: timer@10008000 { 438b2c76e27SDaniel Kurtz compatible = "mediatek,mt8173-timer", 439b2c76e27SDaniel Kurtz "mediatek,mt6577-timer"; 440b2c76e27SDaniel Kurtz reg = <0 0x10008000 0 0x1000>; 441b2c76e27SDaniel Kurtz interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 442b2c76e27SDaniel Kurtz clocks = <&infracfg CLK_INFRA_CLK_13M>, 443b2c76e27SDaniel Kurtz <&topckgen CLK_TOP_RTC_SEL>; 444b2c76e27SDaniel Kurtz }; 445b2c76e27SDaniel Kurtz 4466cf15fc2SSascha Hauer pwrap: pwrap@1000d000 { 4476cf15fc2SSascha Hauer compatible = "mediatek,mt8173-pwrap"; 4486cf15fc2SSascha Hauer reg = <0 0x1000d000 0 0x1000>; 4496cf15fc2SSascha Hauer reg-names = "pwrap"; 4506cf15fc2SSascha Hauer interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 4516cf15fc2SSascha Hauer resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 4526cf15fc2SSascha Hauer reset-names = "pwrap"; 4536cf15fc2SSascha Hauer clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 4546cf15fc2SSascha Hauer clock-names = "spi", "wrap"; 4556cf15fc2SSascha Hauer }; 4566cf15fc2SSascha Hauer 457a10b57f4SCK Hu cec: cec@10013000 { 458a10b57f4SCK Hu compatible = "mediatek,mt8173-cec"; 459a10b57f4SCK Hu reg = <0 0x10013000 0 0xbc>; 460a10b57f4SCK Hu interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; 461a10b57f4SCK Hu clocks = <&infracfg CLK_INFRA_CEC>; 462a10b57f4SCK Hu status = "disabled"; 463a10b57f4SCK Hu }; 464a10b57f4SCK Hu 465404b2819SAndrew-CT Chen vpu: vpu@10020000 { 466404b2819SAndrew-CT Chen compatible = "mediatek,mt8173-vpu"; 467404b2819SAndrew-CT Chen reg = <0 0x10020000 0 0x30000>, 468404b2819SAndrew-CT Chen <0 0x10050000 0 0x100>; 469404b2819SAndrew-CT Chen reg-names = "tcm", "cfg_reg"; 470404b2819SAndrew-CT Chen interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 471404b2819SAndrew-CT Chen clocks = <&topckgen CLK_TOP_SCP_SEL>; 472404b2819SAndrew-CT Chen clock-names = "main"; 473404b2819SAndrew-CT Chen memory-region = <&vpu_dma_reserved>; 474404b2819SAndrew-CT Chen }; 475404b2819SAndrew-CT Chen 476b3a37248SEddie Huang sysirq: intpol-controller@10200620 { 477b3a37248SEddie Huang compatible = "mediatek,mt8173-sysirq", 478b3a37248SEddie Huang "mediatek,mt6577-sysirq"; 479b3a37248SEddie Huang interrupt-controller; 480b3a37248SEddie Huang #interrupt-cells = <3>; 481b3a37248SEddie Huang interrupt-parent = <&gic>; 482b3a37248SEddie Huang reg = <0 0x10200620 0 0x20>; 483b3a37248SEddie Huang }; 484b3a37248SEddie Huang 4855ff6b3a6SYong Wu iommu: iommu@10205000 { 4865ff6b3a6SYong Wu compatible = "mediatek,mt8173-m4u"; 4875ff6b3a6SYong Wu reg = <0 0x10205000 0 0x1000>; 4885ff6b3a6SYong Wu interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 4895ff6b3a6SYong Wu clocks = <&infracfg CLK_INFRA_M4U>; 4905ff6b3a6SYong Wu clock-names = "bclk"; 4915ff6b3a6SYong Wu mediatek,larbs = <&larb0 &larb1 &larb2 4925ff6b3a6SYong Wu &larb3 &larb4 &larb5>; 4935ff6b3a6SYong Wu #iommu-cells = <1>; 4945ff6b3a6SYong Wu }; 4955ff6b3a6SYong Wu 49693e9f5eeSandrew-ct.chen@mediatek.com efuse: efuse@10206000 { 49793e9f5eeSandrew-ct.chen@mediatek.com compatible = "mediatek,mt8173-efuse"; 49893e9f5eeSandrew-ct.chen@mediatek.com reg = <0 0x10206000 0 0x1000>; 4996de18454Sdawei.chien@mediatek.com #address-cells = <1>; 5006de18454Sdawei.chien@mediatek.com #size-cells = <1>; 5016de18454Sdawei.chien@mediatek.com thermal_calibration: calib@528 { 5026de18454Sdawei.chien@mediatek.com reg = <0x528 0xc>; 5036de18454Sdawei.chien@mediatek.com }; 50493e9f5eeSandrew-ct.chen@mediatek.com }; 50593e9f5eeSandrew-ct.chen@mediatek.com 506f2ce7014SSascha Hauer apmixedsys: clock-controller@10209000 { 507f2ce7014SSascha Hauer compatible = "mediatek,mt8173-apmixedsys"; 508f2ce7014SSascha Hauer reg = <0 0x10209000 0 0x1000>; 509f2ce7014SSascha Hauer #clock-cells = <1>; 510f2ce7014SSascha Hauer }; 511f2ce7014SSascha Hauer 512a10b57f4SCK Hu hdmi_phy: hdmi-phy@10209100 { 513a10b57f4SCK Hu compatible = "mediatek,mt8173-hdmi-phy"; 514a10b57f4SCK Hu reg = <0 0x10209100 0 0x24>; 515a10b57f4SCK Hu clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; 516a10b57f4SCK Hu clock-names = "pll_ref"; 517a10b57f4SCK Hu clock-output-names = "hdmitx_dig_cts"; 518a10b57f4SCK Hu mediatek,ibias = <0xa>; 519a10b57f4SCK Hu mediatek,ibias_up = <0x1c>; 520a10b57f4SCK Hu #clock-cells = <0>; 521a10b57f4SCK Hu #phy-cells = <0>; 522a10b57f4SCK Hu status = "disabled"; 523a10b57f4SCK Hu }; 524a10b57f4SCK Hu 525c2e66b8fSHoulong Wei gce: mailbox@10212000 { 526c2e66b8fSHoulong Wei compatible = "mediatek,mt8173-gce"; 527c2e66b8fSHoulong Wei reg = <0 0x10212000 0 0x1000>; 528c2e66b8fSHoulong Wei interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 529c2e66b8fSHoulong Wei clocks = <&infracfg CLK_INFRA_GCE>; 530c2e66b8fSHoulong Wei clock-names = "gce"; 531c2e66b8fSHoulong Wei #mbox-cells = <3>; 532c2e66b8fSHoulong Wei }; 533c2e66b8fSHoulong Wei 53481ad4dbaSCK Hu mipi_tx0: mipi-dphy@10215000 { 53581ad4dbaSCK Hu compatible = "mediatek,mt8173-mipi-tx"; 53681ad4dbaSCK Hu reg = <0 0x10215000 0 0x1000>; 53781ad4dbaSCK Hu clocks = <&clk26m>; 53881ad4dbaSCK Hu clock-output-names = "mipi_tx0_pll"; 53981ad4dbaSCK Hu #clock-cells = <0>; 54081ad4dbaSCK Hu #phy-cells = <0>; 54181ad4dbaSCK Hu status = "disabled"; 54281ad4dbaSCK Hu }; 54381ad4dbaSCK Hu 54481ad4dbaSCK Hu mipi_tx1: mipi-dphy@10216000 { 54581ad4dbaSCK Hu compatible = "mediatek,mt8173-mipi-tx"; 54681ad4dbaSCK Hu reg = <0 0x10216000 0 0x1000>; 54781ad4dbaSCK Hu clocks = <&clk26m>; 54881ad4dbaSCK Hu clock-output-names = "mipi_tx1_pll"; 54981ad4dbaSCK Hu #clock-cells = <0>; 55081ad4dbaSCK Hu #phy-cells = <0>; 55181ad4dbaSCK Hu status = "disabled"; 55281ad4dbaSCK Hu }; 55381ad4dbaSCK Hu 554b3a37248SEddie Huang gic: interrupt-controller@10220000 { 555b3a37248SEddie Huang compatible = "arm,gic-400"; 556b3a37248SEddie Huang #interrupt-cells = <3>; 557b3a37248SEddie Huang interrupt-parent = <&gic>; 558b3a37248SEddie Huang interrupt-controller; 559b3a37248SEddie Huang reg = <0 0x10221000 0 0x1000>, 560b3a37248SEddie Huang <0 0x10222000 0 0x2000>, 561b3a37248SEddie Huang <0 0x10224000 0 0x2000>, 562b3a37248SEddie Huang <0 0x10226000 0 0x2000>; 563b3a37248SEddie Huang interrupts = <GIC_PPI 9 564b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 565b3a37248SEddie Huang }; 566b3a37248SEddie Huang 567748c7d4dSSascha Hauer auxadc: auxadc@11001000 { 568748c7d4dSSascha Hauer compatible = "mediatek,mt8173-auxadc"; 569748c7d4dSSascha Hauer reg = <0 0x11001000 0 0x1000>; 570a3207d64SMatthias Brugger clocks = <&pericfg CLK_PERI_AUXADC>; 571a3207d64SMatthias Brugger clock-names = "main"; 572a3207d64SMatthias Brugger #io-channel-cells = <1>; 573748c7d4dSSascha Hauer }; 574748c7d4dSSascha Hauer 575b3a37248SEddie Huang uart0: serial@11002000 { 576b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 577b3a37248SEddie Huang "mediatek,mt6577-uart"; 578b3a37248SEddie Huang reg = <0 0x11002000 0 0x400>; 579b3a37248SEddie Huang interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 5800e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 5810e84faa1SSascha Hauer clock-names = "baud", "bus"; 582b3a37248SEddie Huang status = "disabled"; 583b3a37248SEddie Huang }; 584b3a37248SEddie Huang 585b3a37248SEddie Huang uart1: serial@11003000 { 586b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 587b3a37248SEddie Huang "mediatek,mt6577-uart"; 588b3a37248SEddie Huang reg = <0 0x11003000 0 0x400>; 589b3a37248SEddie Huang interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 5900e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 5910e84faa1SSascha Hauer clock-names = "baud", "bus"; 592b3a37248SEddie Huang status = "disabled"; 593b3a37248SEddie Huang }; 594b3a37248SEddie Huang 595b3a37248SEddie Huang uart2: serial@11004000 { 596b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 597b3a37248SEddie Huang "mediatek,mt6577-uart"; 598b3a37248SEddie Huang reg = <0 0x11004000 0 0x400>; 599b3a37248SEddie Huang interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 6000e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 6010e84faa1SSascha Hauer clock-names = "baud", "bus"; 602b3a37248SEddie Huang status = "disabled"; 603b3a37248SEddie Huang }; 604b3a37248SEddie Huang 605b3a37248SEddie Huang uart3: serial@11005000 { 606b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 607b3a37248SEddie Huang "mediatek,mt6577-uart"; 608b3a37248SEddie Huang reg = <0 0x11005000 0 0x400>; 609b3a37248SEddie Huang interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 6100e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 6110e84faa1SSascha Hauer clock-names = "baud", "bus"; 612b3a37248SEddie Huang status = "disabled"; 613b3a37248SEddie Huang }; 614091cf598SEddie Huang 615091cf598SEddie Huang i2c0: i2c@11007000 { 616091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 617091cf598SEddie Huang reg = <0 0x11007000 0 0x70>, 618091cf598SEddie Huang <0 0x11000100 0 0x80>; 619091cf598SEddie Huang interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 620091cf598SEddie Huang clock-div = <16>; 621091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C0>, 622091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 623091cf598SEddie Huang clock-names = "main", "dma"; 624091cf598SEddie Huang pinctrl-names = "default"; 625091cf598SEddie Huang pinctrl-0 = <&i2c0_pins_a>; 626091cf598SEddie Huang #address-cells = <1>; 627091cf598SEddie Huang #size-cells = <0>; 628091cf598SEddie Huang status = "disabled"; 629091cf598SEddie Huang }; 630091cf598SEddie Huang 631091cf598SEddie Huang i2c1: i2c@11008000 { 632091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 633091cf598SEddie Huang reg = <0 0x11008000 0 0x70>, 634091cf598SEddie Huang <0 0x11000180 0 0x80>; 635091cf598SEddie Huang interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 636091cf598SEddie Huang clock-div = <16>; 637091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C1>, 638091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 639091cf598SEddie Huang clock-names = "main", "dma"; 640091cf598SEddie Huang pinctrl-names = "default"; 641091cf598SEddie Huang pinctrl-0 = <&i2c1_pins_a>; 642091cf598SEddie Huang #address-cells = <1>; 643091cf598SEddie Huang #size-cells = <0>; 644091cf598SEddie Huang status = "disabled"; 645091cf598SEddie Huang }; 646091cf598SEddie Huang 647091cf598SEddie Huang i2c2: i2c@11009000 { 648091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 649091cf598SEddie Huang reg = <0 0x11009000 0 0x70>, 650091cf598SEddie Huang <0 0x11000200 0 0x80>; 651091cf598SEddie Huang interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 652091cf598SEddie Huang clock-div = <16>; 653091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C2>, 654091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 655091cf598SEddie Huang clock-names = "main", "dma"; 656091cf598SEddie Huang pinctrl-names = "default"; 657091cf598SEddie Huang pinctrl-0 = <&i2c2_pins_a>; 658091cf598SEddie Huang #address-cells = <1>; 659091cf598SEddie Huang #size-cells = <0>; 660091cf598SEddie Huang status = "disabled"; 661091cf598SEddie Huang }; 662091cf598SEddie Huang 663b0c936f5SLeilk Liu spi: spi@1100a000 { 664b0c936f5SLeilk Liu compatible = "mediatek,mt8173-spi"; 665b0c936f5SLeilk Liu #address-cells = <1>; 666b0c936f5SLeilk Liu #size-cells = <0>; 667b0c936f5SLeilk Liu reg = <0 0x1100a000 0 0x1000>; 668b0c936f5SLeilk Liu interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 669b0c936f5SLeilk Liu clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 670b0c936f5SLeilk Liu <&topckgen CLK_TOP_SPI_SEL>, 671b0c936f5SLeilk Liu <&pericfg CLK_PERI_SPI0>; 672b0c936f5SLeilk Liu clock-names = "parent-clk", "sel-clk", "spi-clk"; 673b0c936f5SLeilk Liu status = "disabled"; 674b0c936f5SLeilk Liu }; 675b0c936f5SLeilk Liu 676748c7d4dSSascha Hauer thermal: thermal@1100b000 { 677748c7d4dSSascha Hauer #thermal-sensor-cells = <0>; 678748c7d4dSSascha Hauer compatible = "mediatek,mt8173-thermal"; 679748c7d4dSSascha Hauer reg = <0 0x1100b000 0 0x1000>; 680748c7d4dSSascha Hauer interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 681748c7d4dSSascha Hauer clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 682748c7d4dSSascha Hauer clock-names = "therm", "auxadc"; 683748c7d4dSSascha Hauer resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 684748c7d4dSSascha Hauer mediatek,auxadc = <&auxadc>; 685748c7d4dSSascha Hauer mediatek,apmixedsys = <&apmixedsys>; 6866de18454Sdawei.chien@mediatek.com nvmem-cells = <&thermal_calibration>; 6876de18454Sdawei.chien@mediatek.com nvmem-cell-names = "calibration-data"; 688748c7d4dSSascha Hauer }; 689748c7d4dSSascha Hauer 69086cb8a88SBayi Cheng nor_flash: spi@1100d000 { 69186cb8a88SBayi Cheng compatible = "mediatek,mt8173-nor"; 69286cb8a88SBayi Cheng reg = <0 0x1100d000 0 0xe0>; 69386cb8a88SBayi Cheng clocks = <&pericfg CLK_PERI_SPI>, 69486cb8a88SBayi Cheng <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 69586cb8a88SBayi Cheng clock-names = "spi", "sf"; 69686cb8a88SBayi Cheng #address-cells = <1>; 69786cb8a88SBayi Cheng #size-cells = <0>; 69886cb8a88SBayi Cheng status = "disabled"; 69986cb8a88SBayi Cheng }; 70086cb8a88SBayi Cheng 7011ee35c05SYingjoe Chen i2c3: i2c@11010000 { 702091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 703091cf598SEddie Huang reg = <0 0x11010000 0 0x70>, 704091cf598SEddie Huang <0 0x11000280 0 0x80>; 705091cf598SEddie Huang interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 706091cf598SEddie Huang clock-div = <16>; 707091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C3>, 708091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 709091cf598SEddie Huang clock-names = "main", "dma"; 710091cf598SEddie Huang pinctrl-names = "default"; 711091cf598SEddie Huang pinctrl-0 = <&i2c3_pins_a>; 712091cf598SEddie Huang #address-cells = <1>; 713091cf598SEddie Huang #size-cells = <0>; 714091cf598SEddie Huang status = "disabled"; 715091cf598SEddie Huang }; 716091cf598SEddie Huang 7171ee35c05SYingjoe Chen i2c4: i2c@11011000 { 718091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 719091cf598SEddie Huang reg = <0 0x11011000 0 0x70>, 720091cf598SEddie Huang <0 0x11000300 0 0x80>; 721091cf598SEddie Huang interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 722091cf598SEddie Huang clock-div = <16>; 723091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C4>, 724091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 725091cf598SEddie Huang clock-names = "main", "dma"; 726091cf598SEddie Huang pinctrl-names = "default"; 727091cf598SEddie Huang pinctrl-0 = <&i2c4_pins_a>; 728091cf598SEddie Huang #address-cells = <1>; 729091cf598SEddie Huang #size-cells = <0>; 730091cf598SEddie Huang status = "disabled"; 731091cf598SEddie Huang }; 732091cf598SEddie Huang 733a10b57f4SCK Hu hdmiddc0: i2c@11012000 { 734a10b57f4SCK Hu compatible = "mediatek,mt8173-hdmi-ddc"; 735a10b57f4SCK Hu interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 736a10b57f4SCK Hu reg = <0 0x11012000 0 0x1C>; 737a10b57f4SCK Hu clocks = <&pericfg CLK_PERI_I2C5>; 738a10b57f4SCK Hu clock-names = "ddc-i2c"; 739a10b57f4SCK Hu }; 740a10b57f4SCK Hu 7411ee35c05SYingjoe Chen i2c6: i2c@11013000 { 742091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 743091cf598SEddie Huang reg = <0 0x11013000 0 0x70>, 744091cf598SEddie Huang <0 0x11000080 0 0x80>; 745091cf598SEddie Huang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 746091cf598SEddie Huang clock-div = <16>; 747091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C6>, 748091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 749091cf598SEddie Huang clock-names = "main", "dma"; 750091cf598SEddie Huang pinctrl-names = "default"; 751091cf598SEddie Huang pinctrl-0 = <&i2c6_pins_a>; 752091cf598SEddie Huang #address-cells = <1>; 753091cf598SEddie Huang #size-cells = <0>; 754091cf598SEddie Huang status = "disabled"; 755091cf598SEddie Huang }; 756c02e0e86SKoro Chen 757c02e0e86SKoro Chen afe: audio-controller@11220000 { 758c02e0e86SKoro Chen compatible = "mediatek,mt8173-afe-pcm"; 759c02e0e86SKoro Chen reg = <0 0x11220000 0 0x1000>; 760c02e0e86SKoro Chen interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 761c02e0e86SKoro Chen power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; 762c02e0e86SKoro Chen clocks = <&infracfg CLK_INFRA_AUDIO>, 763c02e0e86SKoro Chen <&topckgen CLK_TOP_AUDIO_SEL>, 764c02e0e86SKoro Chen <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 765c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL1_DIV0>, 766c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL2_DIV0>, 767c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S0_M_SEL>, 768c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S1_M_SEL>, 769c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S2_M_SEL>, 770c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S3_M_SEL>, 771c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S3_B_SEL>; 772c02e0e86SKoro Chen clock-names = "infra_sys_audio_clk", 773c02e0e86SKoro Chen "top_pdn_audio", 774c02e0e86SKoro Chen "top_pdn_aud_intbus", 775c02e0e86SKoro Chen "bck0", 776c02e0e86SKoro Chen "bck1", 777c02e0e86SKoro Chen "i2s0_m", 778c02e0e86SKoro Chen "i2s1_m", 779c02e0e86SKoro Chen "i2s2_m", 780c02e0e86SKoro Chen "i2s3_m", 781c02e0e86SKoro Chen "i2s3_b"; 782c02e0e86SKoro Chen assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 783c02e0e86SKoro Chen <&topckgen CLK_TOP_AUD_2_SEL>; 784c02e0e86SKoro Chen assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 785c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL2>; 786c02e0e86SKoro Chen }; 7879719fa5aSEddie Huang 7889719fa5aSEddie Huang mmc0: mmc@11230000 { 789689362b3SChaotian Jing compatible = "mediatek,mt8173-mmc"; 7909719fa5aSEddie Huang reg = <0 0x11230000 0 0x1000>; 7919719fa5aSEddie Huang interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 7929719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_0>, 7939719fa5aSEddie Huang <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 7949719fa5aSEddie Huang clock-names = "source", "hclk"; 7959719fa5aSEddie Huang status = "disabled"; 7969719fa5aSEddie Huang }; 7979719fa5aSEddie Huang 7989719fa5aSEddie Huang mmc1: mmc@11240000 { 799689362b3SChaotian Jing compatible = "mediatek,mt8173-mmc"; 8009719fa5aSEddie Huang reg = <0 0x11240000 0 0x1000>; 8019719fa5aSEddie Huang interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 8029719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_1>, 8039719fa5aSEddie Huang <&topckgen CLK_TOP_AXI_SEL>; 8049719fa5aSEddie Huang clock-names = "source", "hclk"; 8059719fa5aSEddie Huang status = "disabled"; 8069719fa5aSEddie Huang }; 8079719fa5aSEddie Huang 8089719fa5aSEddie Huang mmc2: mmc@11250000 { 809689362b3SChaotian Jing compatible = "mediatek,mt8173-mmc"; 8109719fa5aSEddie Huang reg = <0 0x11250000 0 0x1000>; 8119719fa5aSEddie Huang interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 8129719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_2>, 8139719fa5aSEddie Huang <&topckgen CLK_TOP_AXI_SEL>; 8149719fa5aSEddie Huang clock-names = "source", "hclk"; 8159719fa5aSEddie Huang status = "disabled"; 8169719fa5aSEddie Huang }; 8179719fa5aSEddie Huang 8189719fa5aSEddie Huang mmc3: mmc@11260000 { 819689362b3SChaotian Jing compatible = "mediatek,mt8173-mmc"; 8209719fa5aSEddie Huang reg = <0 0x11260000 0 0x1000>; 8219719fa5aSEddie Huang interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 8229719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_3>, 8239719fa5aSEddie Huang <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 8249719fa5aSEddie Huang clock-names = "source", "hclk"; 8259719fa5aSEddie Huang status = "disabled"; 8269719fa5aSEddie Huang }; 82767e56c56SJames Liao 828c0891284SChunfeng Yun ssusb: usb@11271000 { 829c0891284SChunfeng Yun compatible = "mediatek,mt8173-mtu3"; 830c0891284SChunfeng Yun reg = <0 0x11271000 0 0x3000>, 831bfcce47aSChunfeng Yun <0 0x11280700 0 0x0100>; 832c0891284SChunfeng Yun reg-names = "mac", "ippc"; 833c0891284SChunfeng Yun interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>; 834ebf61c63Schunfeng.yun@mediatek.com phys = <&u2port0 PHY_TYPE_USB2>, 835ebf61c63Schunfeng.yun@mediatek.com <&u3port0 PHY_TYPE_USB3>, 836ebf61c63Schunfeng.yun@mediatek.com <&u2port1 PHY_TYPE_USB2>; 837bfcce47aSChunfeng Yun power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 838cf1fcd45SChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 839cf1fcd45SChunfeng Yun clock-names = "sys_ck", "ref_ck"; 840cf1fcd45SChunfeng Yun mediatek,syscon-wakeup = <&pericfg 0x400 1>; 841c0891284SChunfeng Yun #address-cells = <2>; 842c0891284SChunfeng Yun #size-cells = <2>; 843c0891284SChunfeng Yun ranges; 844c0891284SChunfeng Yun status = "disabled"; 845c0891284SChunfeng Yun 846c0891284SChunfeng Yun usb_host: xhci@11270000 { 847c0891284SChunfeng Yun compatible = "mediatek,mt8173-xhci"; 848c0891284SChunfeng Yun reg = <0 0x11270000 0 0x1000>; 849c0891284SChunfeng Yun reg-names = "mac"; 850c0891284SChunfeng Yun interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 851c0891284SChunfeng Yun power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 852cb6efc7bSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 853cb6efc7bSChunfeng Yun clock-names = "sys_ck", "ref_ck"; 854c0891284SChunfeng Yun status = "disabled"; 855c0891284SChunfeng Yun }; 856bfcce47aSChunfeng Yun }; 857bfcce47aSChunfeng Yun 858bfcce47aSChunfeng Yun u3phy: usb-phy@11290000 { 859bfcce47aSChunfeng Yun compatible = "mediatek,mt8173-u3phy"; 860bfcce47aSChunfeng Yun reg = <0 0x11290000 0 0x800>; 861bfcce47aSChunfeng Yun #address-cells = <2>; 862bfcce47aSChunfeng Yun #size-cells = <2>; 863bfcce47aSChunfeng Yun ranges; 864bfcce47aSChunfeng Yun status = "okay"; 865bfcce47aSChunfeng Yun 866ebf61c63Schunfeng.yun@mediatek.com u2port0: usb-phy@11290800 { 867ebf61c63Schunfeng.yun@mediatek.com reg = <0 0x11290800 0 0x100>; 86810f84a7aSchunfeng.yun@mediatek.com clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 86910f84a7aSchunfeng.yun@mediatek.com clock-names = "ref"; 870bfcce47aSChunfeng Yun #phy-cells = <1>; 871bfcce47aSChunfeng Yun status = "okay"; 872bfcce47aSChunfeng Yun }; 873bfcce47aSChunfeng Yun 874ebf61c63Schunfeng.yun@mediatek.com u3port0: usb-phy@11290900 { 875ebf61c63Schunfeng.yun@mediatek.com reg = <0 0x11290900 0 0x700>; 87610f84a7aSchunfeng.yun@mediatek.com clocks = <&clk26m>; 87710f84a7aSchunfeng.yun@mediatek.com clock-names = "ref"; 878ebf61c63Schunfeng.yun@mediatek.com #phy-cells = <1>; 879ebf61c63Schunfeng.yun@mediatek.com status = "okay"; 880ebf61c63Schunfeng.yun@mediatek.com }; 881ebf61c63Schunfeng.yun@mediatek.com 882ebf61c63Schunfeng.yun@mediatek.com u2port1: usb-phy@11291000 { 883ebf61c63Schunfeng.yun@mediatek.com reg = <0 0x11291000 0 0x100>; 88410f84a7aSchunfeng.yun@mediatek.com clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 88510f84a7aSchunfeng.yun@mediatek.com clock-names = "ref"; 886bfcce47aSChunfeng Yun #phy-cells = <1>; 887bfcce47aSChunfeng Yun status = "okay"; 888bfcce47aSChunfeng Yun }; 889bfcce47aSChunfeng Yun }; 890bfcce47aSChunfeng Yun 89167e56c56SJames Liao mmsys: clock-controller@14000000 { 89267e56c56SJames Liao compatible = "mediatek,mt8173-mmsys", "syscon"; 89367e56c56SJames Liao reg = <0 0x14000000 0 0x1000>; 89481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 895fc6634acSBibby Hsieh assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; 896fc6634acSBibby Hsieh assigned-clock-rates = <400000000>; 89767e56c56SJames Liao #clock-cells = <1>; 89867e56c56SJames Liao }; 89967e56c56SJames Liao 900989b292aSMinghsiu Tsai mdp_rdma0: rdma@14001000 { 9018127881fSDaniel Kurtz compatible = "mediatek,mt8173-mdp-rdma", 9028127881fSDaniel Kurtz "mediatek,mt8173-mdp"; 903989b292aSMinghsiu Tsai reg = <0 0x14001000 0 0x1000>; 904989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RDMA0>, 905989b292aSMinghsiu Tsai <&mmsys CLK_MM_MUTEX_32K>; 906989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 907989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_RDMA0>; 908989b292aSMinghsiu Tsai mediatek,larb = <&larb0>; 9098127881fSDaniel Kurtz mediatek,vpu = <&vpu>; 910989b292aSMinghsiu Tsai }; 911989b292aSMinghsiu Tsai 912989b292aSMinghsiu Tsai mdp_rdma1: rdma@14002000 { 913989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rdma"; 914989b292aSMinghsiu Tsai reg = <0 0x14002000 0 0x1000>; 915989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RDMA1>, 916989b292aSMinghsiu Tsai <&mmsys CLK_MM_MUTEX_32K>; 917989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 918989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_RDMA1>; 919989b292aSMinghsiu Tsai mediatek,larb = <&larb4>; 920989b292aSMinghsiu Tsai }; 921989b292aSMinghsiu Tsai 922989b292aSMinghsiu Tsai mdp_rsz0: rsz@14003000 { 923989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rsz"; 924989b292aSMinghsiu Tsai reg = <0 0x14003000 0 0x1000>; 925989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RSZ0>; 926989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 927989b292aSMinghsiu Tsai }; 928989b292aSMinghsiu Tsai 929989b292aSMinghsiu Tsai mdp_rsz1: rsz@14004000 { 930989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rsz"; 931989b292aSMinghsiu Tsai reg = <0 0x14004000 0 0x1000>; 932989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RSZ1>; 933989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 934989b292aSMinghsiu Tsai }; 935989b292aSMinghsiu Tsai 936989b292aSMinghsiu Tsai mdp_rsz2: rsz@14005000 { 937989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rsz"; 938989b292aSMinghsiu Tsai reg = <0 0x14005000 0 0x1000>; 939989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RSZ2>; 940989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 941989b292aSMinghsiu Tsai }; 942989b292aSMinghsiu Tsai 943989b292aSMinghsiu Tsai mdp_wdma0: wdma@14006000 { 944989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-wdma"; 945989b292aSMinghsiu Tsai reg = <0 0x14006000 0 0x1000>; 946989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_WDMA>; 947989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 948989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_WDMA>; 949989b292aSMinghsiu Tsai mediatek,larb = <&larb0>; 950989b292aSMinghsiu Tsai }; 951989b292aSMinghsiu Tsai 952989b292aSMinghsiu Tsai mdp_wrot0: wrot@14007000 { 953989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-wrot"; 954989b292aSMinghsiu Tsai reg = <0 0x14007000 0 0x1000>; 955989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_WROT0>; 956989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 957989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_WROT0>; 958989b292aSMinghsiu Tsai mediatek,larb = <&larb0>; 959989b292aSMinghsiu Tsai }; 960989b292aSMinghsiu Tsai 961989b292aSMinghsiu Tsai mdp_wrot1: wrot@14008000 { 962989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-wrot"; 963989b292aSMinghsiu Tsai reg = <0 0x14008000 0 0x1000>; 964989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_WROT1>; 965989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 966989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_WROT1>; 967989b292aSMinghsiu Tsai mediatek,larb = <&larb4>; 968989b292aSMinghsiu Tsai }; 969989b292aSMinghsiu Tsai 97081ad4dbaSCK Hu ovl0: ovl@1400c000 { 97181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-ovl"; 97281ad4dbaSCK Hu reg = <0 0x1400c000 0 0x1000>; 97381ad4dbaSCK Hu interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 97481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 97581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_OVL0>; 97681ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_OVL0>; 97781ad4dbaSCK Hu mediatek,larb = <&larb0>; 97881ad4dbaSCK Hu }; 97981ad4dbaSCK Hu 98081ad4dbaSCK Hu ovl1: ovl@1400d000 { 98181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-ovl"; 98281ad4dbaSCK Hu reg = <0 0x1400d000 0 0x1000>; 98381ad4dbaSCK Hu interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; 98481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 98581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_OVL1>; 98681ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_OVL1>; 98781ad4dbaSCK Hu mediatek,larb = <&larb4>; 98881ad4dbaSCK Hu }; 98981ad4dbaSCK Hu 99081ad4dbaSCK Hu rdma0: rdma@1400e000 { 99181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-rdma"; 99281ad4dbaSCK Hu reg = <0 0x1400e000 0 0x1000>; 99381ad4dbaSCK Hu interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 99481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 99581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_RDMA0>; 99681ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_RDMA0>; 99781ad4dbaSCK Hu mediatek,larb = <&larb0>; 99881ad4dbaSCK Hu }; 99981ad4dbaSCK Hu 100081ad4dbaSCK Hu rdma1: rdma@1400f000 { 100181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-rdma"; 100281ad4dbaSCK Hu reg = <0 0x1400f000 0 0x1000>; 100381ad4dbaSCK Hu interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; 100481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 100581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_RDMA1>; 100681ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_RDMA1>; 100781ad4dbaSCK Hu mediatek,larb = <&larb4>; 100881ad4dbaSCK Hu }; 100981ad4dbaSCK Hu 101081ad4dbaSCK Hu rdma2: rdma@14010000 { 101181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-rdma"; 101281ad4dbaSCK Hu reg = <0 0x14010000 0 0x1000>; 101381ad4dbaSCK Hu interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; 101481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 101581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_RDMA2>; 101681ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_RDMA2>; 101781ad4dbaSCK Hu mediatek,larb = <&larb4>; 101881ad4dbaSCK Hu }; 101981ad4dbaSCK Hu 102081ad4dbaSCK Hu wdma0: wdma@14011000 { 102181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-wdma"; 102281ad4dbaSCK Hu reg = <0 0x14011000 0 0x1000>; 102381ad4dbaSCK Hu interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 102481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 102581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_WDMA0>; 102681ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_WDMA0>; 102781ad4dbaSCK Hu mediatek,larb = <&larb0>; 102881ad4dbaSCK Hu }; 102981ad4dbaSCK Hu 103081ad4dbaSCK Hu wdma1: wdma@14012000 { 103181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-wdma"; 103281ad4dbaSCK Hu reg = <0 0x14012000 0 0x1000>; 103381ad4dbaSCK Hu interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; 103481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 103581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_WDMA1>; 103681ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_WDMA1>; 103781ad4dbaSCK Hu mediatek,larb = <&larb4>; 103881ad4dbaSCK Hu }; 103981ad4dbaSCK Hu 104081ad4dbaSCK Hu color0: color@14013000 { 104181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-color"; 104281ad4dbaSCK Hu reg = <0 0x14013000 0 0x1000>; 104381ad4dbaSCK Hu interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; 104481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 104581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_COLOR0>; 104681ad4dbaSCK Hu }; 104781ad4dbaSCK Hu 104881ad4dbaSCK Hu color1: color@14014000 { 104981ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-color"; 105081ad4dbaSCK Hu reg = <0 0x14014000 0 0x1000>; 105181ad4dbaSCK Hu interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 105281ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 105381ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_COLOR1>; 105481ad4dbaSCK Hu }; 105581ad4dbaSCK Hu 105681ad4dbaSCK Hu aal@14015000 { 105781ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-aal"; 105881ad4dbaSCK Hu reg = <0 0x14015000 0 0x1000>; 105981ad4dbaSCK Hu interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 106081ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 106181ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_AAL>; 106281ad4dbaSCK Hu }; 106381ad4dbaSCK Hu 106481ad4dbaSCK Hu gamma@14016000 { 106581ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-gamma"; 106681ad4dbaSCK Hu reg = <0 0x14016000 0 0x1000>; 106781ad4dbaSCK Hu interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 106881ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 106981ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_GAMMA>; 107081ad4dbaSCK Hu }; 107181ad4dbaSCK Hu 107281ad4dbaSCK Hu merge@14017000 { 107381ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-merge"; 107481ad4dbaSCK Hu reg = <0 0x14017000 0 0x1000>; 107581ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 107681ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_MERGE>; 107781ad4dbaSCK Hu }; 107881ad4dbaSCK Hu 107981ad4dbaSCK Hu split0: split@14018000 { 108081ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-split"; 108181ad4dbaSCK Hu reg = <0 0x14018000 0 0x1000>; 108281ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 108381ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_SPLIT0>; 108481ad4dbaSCK Hu }; 108581ad4dbaSCK Hu 108681ad4dbaSCK Hu split1: split@14019000 { 108781ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-split"; 108881ad4dbaSCK Hu reg = <0 0x14019000 0 0x1000>; 108981ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 109081ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_SPLIT1>; 109181ad4dbaSCK Hu }; 109281ad4dbaSCK Hu 109381ad4dbaSCK Hu ufoe@1401a000 { 109481ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-ufoe"; 109581ad4dbaSCK Hu reg = <0 0x1401a000 0 0x1000>; 109681ad4dbaSCK Hu interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 109781ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 109881ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_UFOE>; 109981ad4dbaSCK Hu }; 110081ad4dbaSCK Hu 110181ad4dbaSCK Hu dsi0: dsi@1401b000 { 110281ad4dbaSCK Hu compatible = "mediatek,mt8173-dsi"; 110381ad4dbaSCK Hu reg = <0 0x1401b000 0 0x1000>; 110481ad4dbaSCK Hu interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 110581ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 110681ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DSI0_ENGINE>, 110781ad4dbaSCK Hu <&mmsys CLK_MM_DSI0_DIGITAL>, 110881ad4dbaSCK Hu <&mipi_tx0>; 110981ad4dbaSCK Hu clock-names = "engine", "digital", "hs"; 111081ad4dbaSCK Hu phys = <&mipi_tx0>; 111181ad4dbaSCK Hu phy-names = "dphy"; 111281ad4dbaSCK Hu status = "disabled"; 111381ad4dbaSCK Hu }; 111481ad4dbaSCK Hu 111581ad4dbaSCK Hu dsi1: dsi@1401c000 { 111681ad4dbaSCK Hu compatible = "mediatek,mt8173-dsi"; 111781ad4dbaSCK Hu reg = <0 0x1401c000 0 0x1000>; 111881ad4dbaSCK Hu interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 111981ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 112081ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DSI1_ENGINE>, 112181ad4dbaSCK Hu <&mmsys CLK_MM_DSI1_DIGITAL>, 112281ad4dbaSCK Hu <&mipi_tx1>; 112381ad4dbaSCK Hu clock-names = "engine", "digital", "hs"; 112481ad4dbaSCK Hu phy = <&mipi_tx1>; 112581ad4dbaSCK Hu phy-names = "dphy"; 112681ad4dbaSCK Hu status = "disabled"; 112781ad4dbaSCK Hu }; 112881ad4dbaSCK Hu 112981ad4dbaSCK Hu dpi0: dpi@1401d000 { 113081ad4dbaSCK Hu compatible = "mediatek,mt8173-dpi"; 113181ad4dbaSCK Hu reg = <0 0x1401d000 0 0x1000>; 113281ad4dbaSCK Hu interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 113381ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 113481ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DPI_PIXEL>, 113581ad4dbaSCK Hu <&mmsys CLK_MM_DPI_ENGINE>, 113681ad4dbaSCK Hu <&apmixedsys CLK_APMIXED_TVDPLL>; 113781ad4dbaSCK Hu clock-names = "pixel", "engine", "pll"; 113881ad4dbaSCK Hu status = "disabled"; 1139a10b57f4SCK Hu 1140a10b57f4SCK Hu port { 1141a10b57f4SCK Hu dpi0_out: endpoint { 1142a10b57f4SCK Hu remote-endpoint = <&hdmi0_in>; 1143a10b57f4SCK Hu }; 1144a10b57f4SCK Hu }; 114581ad4dbaSCK Hu }; 114681ad4dbaSCK Hu 114761aee934SYH Huang pwm0: pwm@1401e000 { 114861aee934SYH Huang compatible = "mediatek,mt8173-disp-pwm", 114961aee934SYH Huang "mediatek,mt6595-disp-pwm"; 115061aee934SYH Huang reg = <0 0x1401e000 0 0x1000>; 115161aee934SYH Huang #pwm-cells = <2>; 115261aee934SYH Huang clocks = <&mmsys CLK_MM_DISP_PWM026M>, 115361aee934SYH Huang <&mmsys CLK_MM_DISP_PWM0MM>; 115461aee934SYH Huang clock-names = "main", "mm"; 115561aee934SYH Huang status = "disabled"; 115661aee934SYH Huang }; 115761aee934SYH Huang 115861aee934SYH Huang pwm1: pwm@1401f000 { 115961aee934SYH Huang compatible = "mediatek,mt8173-disp-pwm", 116061aee934SYH Huang "mediatek,mt6595-disp-pwm"; 116161aee934SYH Huang reg = <0 0x1401f000 0 0x1000>; 116261aee934SYH Huang #pwm-cells = <2>; 116361aee934SYH Huang clocks = <&mmsys CLK_MM_DISP_PWM126M>, 116461aee934SYH Huang <&mmsys CLK_MM_DISP_PWM1MM>; 116561aee934SYH Huang clock-names = "main", "mm"; 116661aee934SYH Huang status = "disabled"; 116761aee934SYH Huang }; 116861aee934SYH Huang 116981ad4dbaSCK Hu mutex: mutex@14020000 { 117081ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-mutex"; 117181ad4dbaSCK Hu reg = <0 0x14020000 0 0x1000>; 117281ad4dbaSCK Hu interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 117381ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 117481ad4dbaSCK Hu clocks = <&mmsys CLK_MM_MUTEX_32K>; 117581ad4dbaSCK Hu }; 117681ad4dbaSCK Hu 11775ff6b3a6SYong Wu larb0: larb@14021000 { 11785ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 11795ff6b3a6SYong Wu reg = <0 0x14021000 0 0x1000>; 11805ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 11815ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 11825ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_LARB0>, 11835ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_LARB0>; 11845ff6b3a6SYong Wu clock-names = "apb", "smi"; 11855ff6b3a6SYong Wu }; 11865ff6b3a6SYong Wu 11875ff6b3a6SYong Wu smi_common: smi@14022000 { 11885ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-common"; 11895ff6b3a6SYong Wu reg = <0 0x14022000 0 0x1000>; 11905ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 11915ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_COMMON>, 11925ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_COMMON>; 11935ff6b3a6SYong Wu clock-names = "apb", "smi"; 11945ff6b3a6SYong Wu }; 11955ff6b3a6SYong Wu 119681ad4dbaSCK Hu od@14023000 { 119781ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-od"; 119881ad4dbaSCK Hu reg = <0 0x14023000 0 0x1000>; 119981ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_OD>; 120081ad4dbaSCK Hu }; 120181ad4dbaSCK Hu 1202a10b57f4SCK Hu hdmi0: hdmi@14025000 { 1203a10b57f4SCK Hu compatible = "mediatek,mt8173-hdmi"; 1204a10b57f4SCK Hu reg = <0 0x14025000 0 0x400>; 1205a10b57f4SCK Hu interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>; 1206a10b57f4SCK Hu clocks = <&mmsys CLK_MM_HDMI_PIXEL>, 1207a10b57f4SCK Hu <&mmsys CLK_MM_HDMI_PLLCK>, 1208a10b57f4SCK Hu <&mmsys CLK_MM_HDMI_AUDIO>, 1209a10b57f4SCK Hu <&mmsys CLK_MM_HDMI_SPDIF>; 1210a10b57f4SCK Hu clock-names = "pixel", "pll", "bclk", "spdif"; 1211a10b57f4SCK Hu pinctrl-names = "default"; 1212a10b57f4SCK Hu pinctrl-0 = <&hdmi_pin>; 1213a10b57f4SCK Hu phys = <&hdmi_phy>; 1214a10b57f4SCK Hu phy-names = "hdmi"; 1215a10b57f4SCK Hu mediatek,syscon-hdmi = <&mmsys 0x900>; 1216a10b57f4SCK Hu assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; 1217a10b57f4SCK Hu assigned-clock-parents = <&hdmi_phy>; 1218a10b57f4SCK Hu status = "disabled"; 1219a10b57f4SCK Hu 1220a10b57f4SCK Hu ports { 1221a10b57f4SCK Hu #address-cells = <1>; 1222a10b57f4SCK Hu #size-cells = <0>; 1223a10b57f4SCK Hu 1224a10b57f4SCK Hu port@0 { 1225a10b57f4SCK Hu reg = <0>; 1226a10b57f4SCK Hu 1227a10b57f4SCK Hu hdmi0_in: endpoint { 1228a10b57f4SCK Hu remote-endpoint = <&dpi0_out>; 1229a10b57f4SCK Hu }; 1230a10b57f4SCK Hu }; 1231a10b57f4SCK Hu }; 1232a10b57f4SCK Hu }; 1233a10b57f4SCK Hu 12345ff6b3a6SYong Wu larb4: larb@14027000 { 12355ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 12365ff6b3a6SYong Wu reg = <0 0x14027000 0 0x1000>; 12375ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 12385ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 12395ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_LARB4>, 12405ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_LARB4>; 12415ff6b3a6SYong Wu clock-names = "apb", "smi"; 12425ff6b3a6SYong Wu }; 12435ff6b3a6SYong Wu 124467e56c56SJames Liao imgsys: clock-controller@15000000 { 124567e56c56SJames Liao compatible = "mediatek,mt8173-imgsys", "syscon"; 124667e56c56SJames Liao reg = <0 0x15000000 0 0x1000>; 124767e56c56SJames Liao #clock-cells = <1>; 124867e56c56SJames Liao }; 124967e56c56SJames Liao 12505ff6b3a6SYong Wu larb2: larb@15001000 { 12515ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 12525ff6b3a6SYong Wu reg = <0 0x15001000 0 0x1000>; 12535ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 12545ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>; 12555ff6b3a6SYong Wu clocks = <&imgsys CLK_IMG_LARB2_SMI>, 12565ff6b3a6SYong Wu <&imgsys CLK_IMG_LARB2_SMI>; 12575ff6b3a6SYong Wu clock-names = "apb", "smi"; 12585ff6b3a6SYong Wu }; 12595ff6b3a6SYong Wu 126067e56c56SJames Liao vdecsys: clock-controller@16000000 { 126167e56c56SJames Liao compatible = "mediatek,mt8173-vdecsys", "syscon"; 126267e56c56SJames Liao reg = <0 0x16000000 0 0x1000>; 126367e56c56SJames Liao #clock-cells = <1>; 126467e56c56SJames Liao }; 126567e56c56SJames Liao 126660eaae2bSTiffany Lin vcodec_dec: vcodec@16000000 { 126760eaae2bSTiffany Lin compatible = "mediatek,mt8173-vcodec-dec"; 126860eaae2bSTiffany Lin reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */ 126960eaae2bSTiffany Lin <0 0x16020000 0 0x1000>, /* VDEC_MISC */ 127060eaae2bSTiffany Lin <0 0x16021000 0 0x800>, /* VDEC_LD */ 127160eaae2bSTiffany Lin <0 0x16021800 0 0x800>, /* VDEC_TOP */ 127260eaae2bSTiffany Lin <0 0x16022000 0 0x1000>, /* VDEC_CM */ 127360eaae2bSTiffany Lin <0 0x16023000 0 0x1000>, /* VDEC_AD */ 127460eaae2bSTiffany Lin <0 0x16024000 0 0x1000>, /* VDEC_AV */ 127560eaae2bSTiffany Lin <0 0x16025000 0 0x1000>, /* VDEC_PP */ 127660eaae2bSTiffany Lin <0 0x16026800 0 0x800>, /* VDEC_HWD */ 127760eaae2bSTiffany Lin <0 0x16027000 0 0x800>, /* VDEC_HWQ */ 127860eaae2bSTiffany Lin <0 0x16027800 0 0x800>, /* VDEC_HWB */ 127960eaae2bSTiffany Lin <0 0x16028400 0 0x400>; /* VDEC_HWG */ 128060eaae2bSTiffany Lin interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; 128160eaae2bSTiffany Lin mediatek,larb = <&larb1>; 128260eaae2bSTiffany Lin iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, 128360eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_PP_EXT>, 128460eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, 128560eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, 128660eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, 128760eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, 128860eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, 128960eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; 129060eaae2bSTiffany Lin mediatek,vpu = <&vpu>; 129160eaae2bSTiffany Lin power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 129260eaae2bSTiffany Lin clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, 129360eaae2bSTiffany Lin <&topckgen CLK_TOP_UNIVPLL_D2>, 129460eaae2bSTiffany Lin <&topckgen CLK_TOP_CCI400_SEL>, 129560eaae2bSTiffany Lin <&topckgen CLK_TOP_VDEC_SEL>, 129660eaae2bSTiffany Lin <&topckgen CLK_TOP_VCODECPLL>, 129760eaae2bSTiffany Lin <&apmixedsys CLK_APMIXED_VENCPLL>, 129860eaae2bSTiffany Lin <&topckgen CLK_TOP_VENC_LT_SEL>, 129960eaae2bSTiffany Lin <&topckgen CLK_TOP_VCODECPLL_370P5>; 130060eaae2bSTiffany Lin clock-names = "vcodecpll", 130160eaae2bSTiffany Lin "univpll_d2", 130260eaae2bSTiffany Lin "clk_cci400_sel", 130360eaae2bSTiffany Lin "vdec_sel", 130460eaae2bSTiffany Lin "vdecpll", 130560eaae2bSTiffany Lin "vencpll", 130660eaae2bSTiffany Lin "venc_lt_sel", 130760eaae2bSTiffany Lin "vdec_bus_clk_src"; 130860eaae2bSTiffany Lin }; 130960eaae2bSTiffany Lin 13105ff6b3a6SYong Wu larb1: larb@16010000 { 13115ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 13125ff6b3a6SYong Wu reg = <0 0x16010000 0 0x1000>; 13135ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 13145ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 13155ff6b3a6SYong Wu clocks = <&vdecsys CLK_VDEC_CKEN>, 13165ff6b3a6SYong Wu <&vdecsys CLK_VDEC_LARB_CKEN>; 13175ff6b3a6SYong Wu clock-names = "apb", "smi"; 13185ff6b3a6SYong Wu }; 13195ff6b3a6SYong Wu 132067e56c56SJames Liao vencsys: clock-controller@18000000 { 132167e56c56SJames Liao compatible = "mediatek,mt8173-vencsys", "syscon"; 132267e56c56SJames Liao reg = <0 0x18000000 0 0x1000>; 132367e56c56SJames Liao #clock-cells = <1>; 132467e56c56SJames Liao }; 132567e56c56SJames Liao 13265ff6b3a6SYong Wu larb3: larb@18001000 { 13275ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 13285ff6b3a6SYong Wu reg = <0 0x18001000 0 0x1000>; 13295ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 13305ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 13315ff6b3a6SYong Wu clocks = <&vencsys CLK_VENC_CKE1>, 13325ff6b3a6SYong Wu <&vencsys CLK_VENC_CKE0>; 13335ff6b3a6SYong Wu clock-names = "apb", "smi"; 13345ff6b3a6SYong Wu }; 13355ff6b3a6SYong Wu 13368eb80252STiffany Lin vcodec_enc: vcodec@18002000 { 13378eb80252STiffany Lin compatible = "mediatek,mt8173-vcodec-enc"; 13388eb80252STiffany Lin reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */ 13398eb80252STiffany Lin <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ 13408eb80252STiffany Lin interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>, 13418eb80252STiffany Lin <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; 13428eb80252STiffany Lin mediatek,larb = <&larb3>, 13438eb80252STiffany Lin <&larb5>; 13448eb80252STiffany Lin iommus = <&iommu M4U_PORT_VENC_RCPU>, 13458eb80252STiffany Lin <&iommu M4U_PORT_VENC_REC>, 13468eb80252STiffany Lin <&iommu M4U_PORT_VENC_BSDMA>, 13478eb80252STiffany Lin <&iommu M4U_PORT_VENC_SV_COMV>, 13488eb80252STiffany Lin <&iommu M4U_PORT_VENC_RD_COMV>, 13498eb80252STiffany Lin <&iommu M4U_PORT_VENC_CUR_LUMA>, 13508eb80252STiffany Lin <&iommu M4U_PORT_VENC_CUR_CHROMA>, 13518eb80252STiffany Lin <&iommu M4U_PORT_VENC_REF_LUMA>, 13528eb80252STiffany Lin <&iommu M4U_PORT_VENC_REF_CHROMA>, 13538eb80252STiffany Lin <&iommu M4U_PORT_VENC_NBM_RDMA>, 13548eb80252STiffany Lin <&iommu M4U_PORT_VENC_NBM_WDMA>, 13558eb80252STiffany Lin <&iommu M4U_PORT_VENC_RCPU_SET2>, 13568eb80252STiffany Lin <&iommu M4U_PORT_VENC_REC_FRM_SET2>, 13578eb80252STiffany Lin <&iommu M4U_PORT_VENC_BSDMA_SET2>, 13588eb80252STiffany Lin <&iommu M4U_PORT_VENC_SV_COMA_SET2>, 13598eb80252STiffany Lin <&iommu M4U_PORT_VENC_RD_COMA_SET2>, 13608eb80252STiffany Lin <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, 13618eb80252STiffany Lin <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, 13628eb80252STiffany Lin <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, 13638eb80252STiffany Lin <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; 13648eb80252STiffany Lin mediatek,vpu = <&vpu>; 13658eb80252STiffany Lin clocks = <&topckgen CLK_TOP_VENCPLL_D2>, 13668eb80252STiffany Lin <&topckgen CLK_TOP_VENC_SEL>, 13678eb80252STiffany Lin <&topckgen CLK_TOP_UNIVPLL1_D2>, 13688eb80252STiffany Lin <&topckgen CLK_TOP_VENC_LT_SEL>; 13698eb80252STiffany Lin clock-names = "venc_sel_src", 13708eb80252STiffany Lin "venc_sel", 13718eb80252STiffany Lin "venc_lt_sel_src", 13728eb80252STiffany Lin "venc_lt_sel"; 13738eb80252STiffany Lin }; 13748eb80252STiffany Lin 137567e56c56SJames Liao vencltsys: clock-controller@19000000 { 137667e56c56SJames Liao compatible = "mediatek,mt8173-vencltsys", "syscon"; 137767e56c56SJames Liao reg = <0 0x19000000 0 0x1000>; 137867e56c56SJames Liao #clock-cells = <1>; 137967e56c56SJames Liao }; 13805ff6b3a6SYong Wu 13815ff6b3a6SYong Wu larb5: larb@19001000 { 13825ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 13835ff6b3a6SYong Wu reg = <0 0x19001000 0 0x1000>; 13845ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 13855ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; 13865ff6b3a6SYong Wu clocks = <&vencltsys CLK_VENCLT_CKE1>, 13875ff6b3a6SYong Wu <&vencltsys CLK_VENCLT_CKE0>; 13885ff6b3a6SYong Wu clock-names = "apb", "smi"; 13895ff6b3a6SYong Wu }; 1390b3a37248SEddie Huang }; 1391b3a37248SEddie Huang}; 1392b3a37248SEddie Huang 1393