1b3a37248SEddie Huang/* 2b3a37248SEddie Huang * Copyright (c) 2014 MediaTek Inc. 3b3a37248SEddie Huang * Author: Eddie Huang <eddie.huang@mediatek.com> 4b3a37248SEddie Huang * 5b3a37248SEddie Huang * This program is free software; you can redistribute it and/or modify 6b3a37248SEddie Huang * it under the terms of the GNU General Public License version 2 as 7b3a37248SEddie Huang * published by the Free Software Foundation. 8b3a37248SEddie Huang * 9b3a37248SEddie Huang * This program is distributed in the hope that it will be useful, 10b3a37248SEddie Huang * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11b3a37248SEddie Huang * GNU General Public License for more details. 12b3a37248SEddie Huang */ 13b3a37248SEddie Huang 14f2ce7014SSascha Hauer#include <dt-bindings/clock/mt8173-clk.h> 15b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/irq.h> 16b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/arm-gic.h> 17c02e0e86SKoro Chen#include <dt-bindings/power/mt8173-power.h> 186cf15fc2SSascha Hauer#include <dt-bindings/reset-controller/mt8173-resets.h> 19359f9365SHongzhou Yang#include "mt8173-pinfunc.h" 20b3a37248SEddie Huang 21b3a37248SEddie Huang/ { 22b3a37248SEddie Huang compatible = "mediatek,mt8173"; 23b3a37248SEddie Huang interrupt-parent = <&sysirq>; 24b3a37248SEddie Huang #address-cells = <2>; 25b3a37248SEddie Huang #size-cells = <2>; 26b3a37248SEddie Huang 27b3a37248SEddie Huang cpus { 28b3a37248SEddie Huang #address-cells = <1>; 29b3a37248SEddie Huang #size-cells = <0>; 30b3a37248SEddie Huang 31b3a37248SEddie Huang cpu-map { 32b3a37248SEddie Huang cluster0 { 33b3a37248SEddie Huang core0 { 34b3a37248SEddie Huang cpu = <&cpu0>; 35b3a37248SEddie Huang }; 36b3a37248SEddie Huang core1 { 37b3a37248SEddie Huang cpu = <&cpu1>; 38b3a37248SEddie Huang }; 39b3a37248SEddie Huang }; 40b3a37248SEddie Huang 41b3a37248SEddie Huang cluster1 { 42b3a37248SEddie Huang core0 { 43b3a37248SEddie Huang cpu = <&cpu2>; 44b3a37248SEddie Huang }; 45b3a37248SEddie Huang core1 { 46b3a37248SEddie Huang cpu = <&cpu3>; 47b3a37248SEddie Huang }; 48b3a37248SEddie Huang }; 49b3a37248SEddie Huang }; 50b3a37248SEddie Huang 51b3a37248SEddie Huang cpu0: cpu@0 { 52b3a37248SEddie Huang device_type = "cpu"; 53b3a37248SEddie Huang compatible = "arm,cortex-a53"; 54b3a37248SEddie Huang reg = <0x000>; 55ad4df7a5SHoward Chen enable-method = "psci"; 56ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 57b3a37248SEddie Huang }; 58b3a37248SEddie Huang 59b3a37248SEddie Huang cpu1: cpu@1 { 60b3a37248SEddie Huang device_type = "cpu"; 61b3a37248SEddie Huang compatible = "arm,cortex-a53"; 62b3a37248SEddie Huang reg = <0x001>; 63b3a37248SEddie Huang enable-method = "psci"; 64ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 65b3a37248SEddie Huang }; 66b3a37248SEddie Huang 67b3a37248SEddie Huang cpu2: cpu@100 { 68b3a37248SEddie Huang device_type = "cpu"; 69b3a37248SEddie Huang compatible = "arm,cortex-a57"; 70b3a37248SEddie Huang reg = <0x100>; 71b3a37248SEddie Huang enable-method = "psci"; 72ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 73b3a37248SEddie Huang }; 74b3a37248SEddie Huang 75b3a37248SEddie Huang cpu3: cpu@101 { 76b3a37248SEddie Huang device_type = "cpu"; 77b3a37248SEddie Huang compatible = "arm,cortex-a57"; 78b3a37248SEddie Huang reg = <0x101>; 79b3a37248SEddie Huang enable-method = "psci"; 80ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 81ad4df7a5SHoward Chen }; 82ad4df7a5SHoward Chen 83ad4df7a5SHoward Chen idle-states { 84ad4df7a5SHoward Chen entry-method = "arm,psci"; 85ad4df7a5SHoward Chen 86ad4df7a5SHoward Chen CPU_SLEEP_0: cpu-sleep-0 { 87ad4df7a5SHoward Chen compatible = "arm,idle-state"; 88ad4df7a5SHoward Chen local-timer-stop; 89ad4df7a5SHoward Chen entry-latency-us = <639>; 90ad4df7a5SHoward Chen exit-latency-us = <680>; 91ad4df7a5SHoward Chen min-residency-us = <1088>; 92ad4df7a5SHoward Chen arm,psci-suspend-param = <0x0010000>; 93ad4df7a5SHoward Chen }; 94b3a37248SEddie Huang }; 95b3a37248SEddie Huang }; 96b3a37248SEddie Huang 97b3a37248SEddie Huang psci { 98b3a37248SEddie Huang compatible = "arm,psci"; 99b3a37248SEddie Huang method = "smc"; 100b3a37248SEddie Huang cpu_suspend = <0x84000001>; 101b3a37248SEddie Huang cpu_off = <0x84000002>; 102b3a37248SEddie Huang cpu_on = <0x84000003>; 103b3a37248SEddie Huang }; 104b3a37248SEddie Huang 105f2ce7014SSascha Hauer clk26m: oscillator@0 { 106f2ce7014SSascha Hauer compatible = "fixed-clock"; 107f2ce7014SSascha Hauer #clock-cells = <0>; 108f2ce7014SSascha Hauer clock-frequency = <26000000>; 109f2ce7014SSascha Hauer clock-output-names = "clk26m"; 110f2ce7014SSascha Hauer }; 111f2ce7014SSascha Hauer 112f2ce7014SSascha Hauer clk32k: oscillator@1 { 113f2ce7014SSascha Hauer compatible = "fixed-clock"; 114f2ce7014SSascha Hauer #clock-cells = <0>; 115f2ce7014SSascha Hauer clock-frequency = <32000>; 116f2ce7014SSascha Hauer clock-output-names = "clk32k"; 117f2ce7014SSascha Hauer }; 118f2ce7014SSascha Hauer 119b3a37248SEddie Huang timer { 120b3a37248SEddie Huang compatible = "arm,armv8-timer"; 121b3a37248SEddie Huang interrupt-parent = <&gic>; 122b3a37248SEddie Huang interrupts = <GIC_PPI 13 123b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 124b3a37248SEddie Huang <GIC_PPI 14 125b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 126b3a37248SEddie Huang <GIC_PPI 11 127b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 128b3a37248SEddie Huang <GIC_PPI 10 129b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 130b3a37248SEddie Huang }; 131b3a37248SEddie Huang 132b3a37248SEddie Huang soc { 133b3a37248SEddie Huang #address-cells = <2>; 134b3a37248SEddie Huang #size-cells = <2>; 135b3a37248SEddie Huang compatible = "simple-bus"; 136b3a37248SEddie Huang ranges; 137b3a37248SEddie Huang 138f2ce7014SSascha Hauer topckgen: clock-controller@10000000 { 139f2ce7014SSascha Hauer compatible = "mediatek,mt8173-topckgen"; 140f2ce7014SSascha Hauer reg = <0 0x10000000 0 0x1000>; 141f2ce7014SSascha Hauer #clock-cells = <1>; 142f2ce7014SSascha Hauer }; 143f2ce7014SSascha Hauer 144f2ce7014SSascha Hauer infracfg: power-controller@10001000 { 145f2ce7014SSascha Hauer compatible = "mediatek,mt8173-infracfg", "syscon"; 146f2ce7014SSascha Hauer reg = <0 0x10001000 0 0x1000>; 147f2ce7014SSascha Hauer #clock-cells = <1>; 148f2ce7014SSascha Hauer #reset-cells = <1>; 149f2ce7014SSascha Hauer }; 150f2ce7014SSascha Hauer 151f2ce7014SSascha Hauer pericfg: power-controller@10003000 { 152f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pericfg", "syscon"; 153f2ce7014SSascha Hauer reg = <0 0x10003000 0 0x1000>; 154f2ce7014SSascha Hauer #clock-cells = <1>; 155f2ce7014SSascha Hauer #reset-cells = <1>; 156f2ce7014SSascha Hauer }; 157f2ce7014SSascha Hauer 158f2ce7014SSascha Hauer syscfg_pctl_a: syscfg_pctl_a@10005000 { 159f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 160f2ce7014SSascha Hauer reg = <0 0x10005000 0 0x1000>; 161f2ce7014SSascha Hauer }; 162f2ce7014SSascha Hauer 163f2ce7014SSascha Hauer pio: pinctrl@0x10005000 { 164359f9365SHongzhou Yang compatible = "mediatek,mt8173-pinctrl"; 1656769b93cSYingjoe Chen reg = <0 0x1000b000 0 0x1000>; 166359f9365SHongzhou Yang mediatek,pctl-regmap = <&syscfg_pctl_a>; 167359f9365SHongzhou Yang pins-are-numbered; 168359f9365SHongzhou Yang gpio-controller; 169359f9365SHongzhou Yang #gpio-cells = <2>; 170359f9365SHongzhou Yang interrupt-controller; 171359f9365SHongzhou Yang #interrupt-cells = <2>; 172359f9365SHongzhou Yang interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 173359f9365SHongzhou Yang <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 174359f9365SHongzhou Yang <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 175091cf598SEddie Huang 176091cf598SEddie Huang i2c0_pins_a: i2c0 { 177091cf598SEddie Huang pins1 { 178091cf598SEddie Huang pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 179091cf598SEddie Huang <MT8173_PIN_46_SCL0__FUNC_SCL0>; 180091cf598SEddie Huang bias-disable; 181091cf598SEddie Huang }; 182359f9365SHongzhou Yang }; 183359f9365SHongzhou Yang 184091cf598SEddie Huang i2c1_pins_a: i2c1 { 185091cf598SEddie Huang pins1 { 186091cf598SEddie Huang pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 187091cf598SEddie Huang <MT8173_PIN_126_SCL1__FUNC_SCL1>; 188091cf598SEddie Huang bias-disable; 189091cf598SEddie Huang }; 190091cf598SEddie Huang }; 191091cf598SEddie Huang 192091cf598SEddie Huang i2c2_pins_a: i2c2 { 193091cf598SEddie Huang pins1 { 194091cf598SEddie Huang pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 195091cf598SEddie Huang <MT8173_PIN_44_SCL2__FUNC_SCL2>; 196091cf598SEddie Huang bias-disable; 197091cf598SEddie Huang }; 198091cf598SEddie Huang }; 199091cf598SEddie Huang 200091cf598SEddie Huang i2c3_pins_a: i2c3 { 201091cf598SEddie Huang pins1 { 202091cf598SEddie Huang pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 203091cf598SEddie Huang <MT8173_PIN_107_SCL3__FUNC_SCL3>; 204091cf598SEddie Huang bias-disable; 205091cf598SEddie Huang }; 206091cf598SEddie Huang }; 207091cf598SEddie Huang 208091cf598SEddie Huang i2c4_pins_a: i2c4 { 209091cf598SEddie Huang pins1 { 210091cf598SEddie Huang pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 211091cf598SEddie Huang <MT8173_PIN_134_SCL4__FUNC_SCL4>; 212091cf598SEddie Huang bias-disable; 213091cf598SEddie Huang }; 214091cf598SEddie Huang }; 215091cf598SEddie Huang 216091cf598SEddie Huang i2c6_pins_a: i2c6 { 217091cf598SEddie Huang pins1 { 218091cf598SEddie Huang pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 219091cf598SEddie Huang <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 220091cf598SEddie Huang bias-disable; 221091cf598SEddie Huang }; 222091cf598SEddie Huang }; 2236769b93cSYingjoe Chen }; 2246769b93cSYingjoe Chen 225c010ff53SSascha Hauer scpsys: scpsys@10006000 { 226c010ff53SSascha Hauer compatible = "mediatek,mt8173-scpsys"; 227c010ff53SSascha Hauer #power-domain-cells = <1>; 228c010ff53SSascha Hauer reg = <0 0x10006000 0 0x1000>; 229c010ff53SSascha Hauer clocks = <&clk26m>, 230c010ff53SSascha Hauer <&topckgen CLK_TOP_MM_SEL>; 231c010ff53SSascha Hauer clock-names = "mfg", "mm"; 232c010ff53SSascha Hauer infracfg = <&infracfg>; 233c010ff53SSascha Hauer }; 234c010ff53SSascha Hauer 23513421b3eSEddie Huang watchdog: watchdog@10007000 { 23613421b3eSEddie Huang compatible = "mediatek,mt8173-wdt", 23713421b3eSEddie Huang "mediatek,mt6589-wdt"; 23813421b3eSEddie Huang reg = <0 0x10007000 0 0x100>; 23913421b3eSEddie Huang }; 24013421b3eSEddie Huang 2416cf15fc2SSascha Hauer pwrap: pwrap@1000d000 { 2426cf15fc2SSascha Hauer compatible = "mediatek,mt8173-pwrap"; 2436cf15fc2SSascha Hauer reg = <0 0x1000d000 0 0x1000>; 2446cf15fc2SSascha Hauer reg-names = "pwrap"; 2456cf15fc2SSascha Hauer interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 2466cf15fc2SSascha Hauer resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 2476cf15fc2SSascha Hauer reset-names = "pwrap"; 2486cf15fc2SSascha Hauer clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 2496cf15fc2SSascha Hauer clock-names = "spi", "wrap"; 2506cf15fc2SSascha Hauer }; 2516cf15fc2SSascha Hauer 252b3a37248SEddie Huang sysirq: intpol-controller@10200620 { 253b3a37248SEddie Huang compatible = "mediatek,mt8173-sysirq", 254b3a37248SEddie Huang "mediatek,mt6577-sysirq"; 255b3a37248SEddie Huang interrupt-controller; 256b3a37248SEddie Huang #interrupt-cells = <3>; 257b3a37248SEddie Huang interrupt-parent = <&gic>; 258b3a37248SEddie Huang reg = <0 0x10200620 0 0x20>; 259b3a37248SEddie Huang }; 260b3a37248SEddie Huang 261f2ce7014SSascha Hauer apmixedsys: clock-controller@10209000 { 262f2ce7014SSascha Hauer compatible = "mediatek,mt8173-apmixedsys"; 263f2ce7014SSascha Hauer reg = <0 0x10209000 0 0x1000>; 264f2ce7014SSascha Hauer #clock-cells = <1>; 265f2ce7014SSascha Hauer }; 266f2ce7014SSascha Hauer 267b3a37248SEddie Huang gic: interrupt-controller@10220000 { 268b3a37248SEddie Huang compatible = "arm,gic-400"; 269b3a37248SEddie Huang #interrupt-cells = <3>; 270b3a37248SEddie Huang interrupt-parent = <&gic>; 271b3a37248SEddie Huang interrupt-controller; 272b3a37248SEddie Huang reg = <0 0x10221000 0 0x1000>, 273b3a37248SEddie Huang <0 0x10222000 0 0x2000>, 274b3a37248SEddie Huang <0 0x10224000 0 0x2000>, 275b3a37248SEddie Huang <0 0x10226000 0 0x2000>; 276b3a37248SEddie Huang interrupts = <GIC_PPI 9 277b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 278b3a37248SEddie Huang }; 279b3a37248SEddie Huang 280b3a37248SEddie Huang uart0: serial@11002000 { 281b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 282b3a37248SEddie Huang "mediatek,mt6577-uart"; 283b3a37248SEddie Huang reg = <0 0x11002000 0 0x400>; 284b3a37248SEddie Huang interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 2850e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 2860e84faa1SSascha Hauer clock-names = "baud", "bus"; 287b3a37248SEddie Huang status = "disabled"; 288b3a37248SEddie Huang }; 289b3a37248SEddie Huang 290b3a37248SEddie Huang uart1: serial@11003000 { 291b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 292b3a37248SEddie Huang "mediatek,mt6577-uart"; 293b3a37248SEddie Huang reg = <0 0x11003000 0 0x400>; 294b3a37248SEddie Huang interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 2950e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 2960e84faa1SSascha Hauer clock-names = "baud", "bus"; 297b3a37248SEddie Huang status = "disabled"; 298b3a37248SEddie Huang }; 299b3a37248SEddie Huang 300b3a37248SEddie Huang uart2: serial@11004000 { 301b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 302b3a37248SEddie Huang "mediatek,mt6577-uart"; 303b3a37248SEddie Huang reg = <0 0x11004000 0 0x400>; 304b3a37248SEddie Huang interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 3050e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 3060e84faa1SSascha Hauer clock-names = "baud", "bus"; 307b3a37248SEddie Huang status = "disabled"; 308b3a37248SEddie Huang }; 309b3a37248SEddie Huang 310b3a37248SEddie Huang uart3: serial@11005000 { 311b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 312b3a37248SEddie Huang "mediatek,mt6577-uart"; 313b3a37248SEddie Huang reg = <0 0x11005000 0 0x400>; 314b3a37248SEddie Huang interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 3150e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 3160e84faa1SSascha Hauer clock-names = "baud", "bus"; 317b3a37248SEddie Huang status = "disabled"; 318b3a37248SEddie Huang }; 319091cf598SEddie Huang 320091cf598SEddie Huang i2c0: i2c@11007000 { 321091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 322091cf598SEddie Huang reg = <0 0x11007000 0 0x70>, 323091cf598SEddie Huang <0 0x11000100 0 0x80>; 324091cf598SEddie Huang interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 325091cf598SEddie Huang clock-div = <16>; 326091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C0>, 327091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 328091cf598SEddie Huang clock-names = "main", "dma"; 329091cf598SEddie Huang pinctrl-names = "default"; 330091cf598SEddie Huang pinctrl-0 = <&i2c0_pins_a>; 331091cf598SEddie Huang #address-cells = <1>; 332091cf598SEddie Huang #size-cells = <0>; 333091cf598SEddie Huang status = "disabled"; 334091cf598SEddie Huang }; 335091cf598SEddie Huang 336091cf598SEddie Huang i2c1: i2c@11008000 { 337091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 338091cf598SEddie Huang reg = <0 0x11008000 0 0x70>, 339091cf598SEddie Huang <0 0x11000180 0 0x80>; 340091cf598SEddie Huang interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 341091cf598SEddie Huang clock-div = <16>; 342091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C1>, 343091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 344091cf598SEddie Huang clock-names = "main", "dma"; 345091cf598SEddie Huang pinctrl-names = "default"; 346091cf598SEddie Huang pinctrl-0 = <&i2c1_pins_a>; 347091cf598SEddie Huang #address-cells = <1>; 348091cf598SEddie Huang #size-cells = <0>; 349091cf598SEddie Huang status = "disabled"; 350091cf598SEddie Huang }; 351091cf598SEddie Huang 352091cf598SEddie Huang i2c2: i2c@11009000 { 353091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 354091cf598SEddie Huang reg = <0 0x11009000 0 0x70>, 355091cf598SEddie Huang <0 0x11000200 0 0x80>; 356091cf598SEddie Huang interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 357091cf598SEddie Huang clock-div = <16>; 358091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C2>, 359091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 360091cf598SEddie Huang clock-names = "main", "dma"; 361091cf598SEddie Huang pinctrl-names = "default"; 362091cf598SEddie Huang pinctrl-0 = <&i2c2_pins_a>; 363091cf598SEddie Huang #address-cells = <1>; 364091cf598SEddie Huang #size-cells = <0>; 365091cf598SEddie Huang status = "disabled"; 366091cf598SEddie Huang }; 367091cf598SEddie Huang 368091cf598SEddie Huang i2c3: i2c3@11010000 { 369091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 370091cf598SEddie Huang reg = <0 0x11010000 0 0x70>, 371091cf598SEddie Huang <0 0x11000280 0 0x80>; 372091cf598SEddie Huang interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 373091cf598SEddie Huang clock-div = <16>; 374091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C3>, 375091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 376091cf598SEddie Huang clock-names = "main", "dma"; 377091cf598SEddie Huang pinctrl-names = "default"; 378091cf598SEddie Huang pinctrl-0 = <&i2c3_pins_a>; 379091cf598SEddie Huang #address-cells = <1>; 380091cf598SEddie Huang #size-cells = <0>; 381091cf598SEddie Huang status = "disabled"; 382091cf598SEddie Huang }; 383091cf598SEddie Huang 384091cf598SEddie Huang i2c4: i2c4@11011000 { 385091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 386091cf598SEddie Huang reg = <0 0x11011000 0 0x70>, 387091cf598SEddie Huang <0 0x11000300 0 0x80>; 388091cf598SEddie Huang interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 389091cf598SEddie Huang clock-div = <16>; 390091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C4>, 391091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 392091cf598SEddie Huang clock-names = "main", "dma"; 393091cf598SEddie Huang pinctrl-names = "default"; 394091cf598SEddie Huang pinctrl-0 = <&i2c4_pins_a>; 395091cf598SEddie Huang #address-cells = <1>; 396091cf598SEddie Huang #size-cells = <0>; 397091cf598SEddie Huang status = "disabled"; 398091cf598SEddie Huang }; 399091cf598SEddie Huang 400091cf598SEddie Huang i2c6: i2c6@11013000 { 401091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 402091cf598SEddie Huang reg = <0 0x11013000 0 0x70>, 403091cf598SEddie Huang <0 0x11000080 0 0x80>; 404091cf598SEddie Huang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 405091cf598SEddie Huang clock-div = <16>; 406091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C6>, 407091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 408091cf598SEddie Huang clock-names = "main", "dma"; 409091cf598SEddie Huang pinctrl-names = "default"; 410091cf598SEddie Huang pinctrl-0 = <&i2c6_pins_a>; 411091cf598SEddie Huang #address-cells = <1>; 412091cf598SEddie Huang #size-cells = <0>; 413091cf598SEddie Huang status = "disabled"; 414091cf598SEddie Huang }; 415c02e0e86SKoro Chen 416c02e0e86SKoro Chen afe: audio-controller@11220000 { 417c02e0e86SKoro Chen compatible = "mediatek,mt8173-afe-pcm"; 418c02e0e86SKoro Chen reg = <0 0x11220000 0 0x1000>; 419c02e0e86SKoro Chen interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 420c02e0e86SKoro Chen power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; 421c02e0e86SKoro Chen clocks = <&infracfg CLK_INFRA_AUDIO>, 422c02e0e86SKoro Chen <&topckgen CLK_TOP_AUDIO_SEL>, 423c02e0e86SKoro Chen <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 424c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL1_DIV0>, 425c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL2_DIV0>, 426c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S0_M_SEL>, 427c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S1_M_SEL>, 428c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S2_M_SEL>, 429c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S3_M_SEL>, 430c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S3_B_SEL>; 431c02e0e86SKoro Chen clock-names = "infra_sys_audio_clk", 432c02e0e86SKoro Chen "top_pdn_audio", 433c02e0e86SKoro Chen "top_pdn_aud_intbus", 434c02e0e86SKoro Chen "bck0", 435c02e0e86SKoro Chen "bck1", 436c02e0e86SKoro Chen "i2s0_m", 437c02e0e86SKoro Chen "i2s1_m", 438c02e0e86SKoro Chen "i2s2_m", 439c02e0e86SKoro Chen "i2s3_m", 440c02e0e86SKoro Chen "i2s3_b"; 441c02e0e86SKoro Chen assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 442c02e0e86SKoro Chen <&topckgen CLK_TOP_AUD_2_SEL>; 443c02e0e86SKoro Chen assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 444c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL2>; 445c02e0e86SKoro Chen }; 446b3a37248SEddie Huang }; 447b3a37248SEddie Huang}; 448b3a37248SEddie Huang 449