1b3a37248SEddie Huang/* 2b3a37248SEddie Huang * Copyright (c) 2014 MediaTek Inc. 3b3a37248SEddie Huang * Author: Eddie Huang <eddie.huang@mediatek.com> 4b3a37248SEddie Huang * 5b3a37248SEddie Huang * This program is free software; you can redistribute it and/or modify 6b3a37248SEddie Huang * it under the terms of the GNU General Public License version 2 as 7b3a37248SEddie Huang * published by the Free Software Foundation. 8b3a37248SEddie Huang * 9b3a37248SEddie Huang * This program is distributed in the hope that it will be useful, 10b3a37248SEddie Huang * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11b3a37248SEddie Huang * GNU General Public License for more details. 12b3a37248SEddie Huang */ 13b3a37248SEddie Huang 14f2ce7014SSascha Hauer#include <dt-bindings/clock/mt8173-clk.h> 15b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/irq.h> 16b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/arm-gic.h> 176cf15fc2SSascha Hauer#include <dt-bindings/reset-controller/mt8173-resets.h> 18359f9365SHongzhou Yang#include "mt8173-pinfunc.h" 19b3a37248SEddie Huang 20b3a37248SEddie Huang/ { 21b3a37248SEddie Huang compatible = "mediatek,mt8173"; 22b3a37248SEddie Huang interrupt-parent = <&sysirq>; 23b3a37248SEddie Huang #address-cells = <2>; 24b3a37248SEddie Huang #size-cells = <2>; 25b3a37248SEddie Huang 26b3a37248SEddie Huang cpus { 27b3a37248SEddie Huang #address-cells = <1>; 28b3a37248SEddie Huang #size-cells = <0>; 29b3a37248SEddie Huang 30b3a37248SEddie Huang cpu-map { 31b3a37248SEddie Huang cluster0 { 32b3a37248SEddie Huang core0 { 33b3a37248SEddie Huang cpu = <&cpu0>; 34b3a37248SEddie Huang }; 35b3a37248SEddie Huang core1 { 36b3a37248SEddie Huang cpu = <&cpu1>; 37b3a37248SEddie Huang }; 38b3a37248SEddie Huang }; 39b3a37248SEddie Huang 40b3a37248SEddie Huang cluster1 { 41b3a37248SEddie Huang core0 { 42b3a37248SEddie Huang cpu = <&cpu2>; 43b3a37248SEddie Huang }; 44b3a37248SEddie Huang core1 { 45b3a37248SEddie Huang cpu = <&cpu3>; 46b3a37248SEddie Huang }; 47b3a37248SEddie Huang }; 48b3a37248SEddie Huang }; 49b3a37248SEddie Huang 50b3a37248SEddie Huang cpu0: cpu@0 { 51b3a37248SEddie Huang device_type = "cpu"; 52b3a37248SEddie Huang compatible = "arm,cortex-a53"; 53b3a37248SEddie Huang reg = <0x000>; 54b3a37248SEddie Huang }; 55b3a37248SEddie Huang 56b3a37248SEddie Huang cpu1: cpu@1 { 57b3a37248SEddie Huang device_type = "cpu"; 58b3a37248SEddie Huang compatible = "arm,cortex-a53"; 59b3a37248SEddie Huang reg = <0x001>; 60b3a37248SEddie Huang enable-method = "psci"; 61b3a37248SEddie Huang }; 62b3a37248SEddie Huang 63b3a37248SEddie Huang cpu2: cpu@100 { 64b3a37248SEddie Huang device_type = "cpu"; 65b3a37248SEddie Huang compatible = "arm,cortex-a57"; 66b3a37248SEddie Huang reg = <0x100>; 67b3a37248SEddie Huang enable-method = "psci"; 68b3a37248SEddie Huang }; 69b3a37248SEddie Huang 70b3a37248SEddie Huang cpu3: cpu@101 { 71b3a37248SEddie Huang device_type = "cpu"; 72b3a37248SEddie Huang compatible = "arm,cortex-a57"; 73b3a37248SEddie Huang reg = <0x101>; 74b3a37248SEddie Huang enable-method = "psci"; 75b3a37248SEddie Huang }; 76b3a37248SEddie Huang }; 77b3a37248SEddie Huang 78b3a37248SEddie Huang psci { 79b3a37248SEddie Huang compatible = "arm,psci"; 80b3a37248SEddie Huang method = "smc"; 81b3a37248SEddie Huang cpu_suspend = <0x84000001>; 82b3a37248SEddie Huang cpu_off = <0x84000002>; 83b3a37248SEddie Huang cpu_on = <0x84000003>; 84b3a37248SEddie Huang }; 85b3a37248SEddie Huang 86f2ce7014SSascha Hauer clk26m: oscillator@0 { 87f2ce7014SSascha Hauer compatible = "fixed-clock"; 88f2ce7014SSascha Hauer #clock-cells = <0>; 89f2ce7014SSascha Hauer clock-frequency = <26000000>; 90f2ce7014SSascha Hauer clock-output-names = "clk26m"; 91f2ce7014SSascha Hauer }; 92f2ce7014SSascha Hauer 93f2ce7014SSascha Hauer clk32k: oscillator@1 { 94f2ce7014SSascha Hauer compatible = "fixed-clock"; 95f2ce7014SSascha Hauer #clock-cells = <0>; 96f2ce7014SSascha Hauer clock-frequency = <32000>; 97f2ce7014SSascha Hauer clock-output-names = "clk32k"; 98f2ce7014SSascha Hauer }; 99f2ce7014SSascha Hauer 100b3a37248SEddie Huang timer { 101b3a37248SEddie Huang compatible = "arm,armv8-timer"; 102b3a37248SEddie Huang interrupt-parent = <&gic>; 103b3a37248SEddie Huang interrupts = <GIC_PPI 13 104b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 105b3a37248SEddie Huang <GIC_PPI 14 106b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 107b3a37248SEddie Huang <GIC_PPI 11 108b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 109b3a37248SEddie Huang <GIC_PPI 10 110b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 111b3a37248SEddie Huang }; 112b3a37248SEddie Huang 113b3a37248SEddie Huang soc { 114b3a37248SEddie Huang #address-cells = <2>; 115b3a37248SEddie Huang #size-cells = <2>; 116b3a37248SEddie Huang compatible = "simple-bus"; 117b3a37248SEddie Huang ranges; 118b3a37248SEddie Huang 119f2ce7014SSascha Hauer topckgen: clock-controller@10000000 { 120f2ce7014SSascha Hauer compatible = "mediatek,mt8173-topckgen"; 121f2ce7014SSascha Hauer reg = <0 0x10000000 0 0x1000>; 122f2ce7014SSascha Hauer #clock-cells = <1>; 123f2ce7014SSascha Hauer }; 124f2ce7014SSascha Hauer 125f2ce7014SSascha Hauer infracfg: power-controller@10001000 { 126f2ce7014SSascha Hauer compatible = "mediatek,mt8173-infracfg", "syscon"; 127f2ce7014SSascha Hauer reg = <0 0x10001000 0 0x1000>; 128f2ce7014SSascha Hauer #clock-cells = <1>; 129f2ce7014SSascha Hauer #reset-cells = <1>; 130f2ce7014SSascha Hauer }; 131f2ce7014SSascha Hauer 132f2ce7014SSascha Hauer pericfg: power-controller@10003000 { 133f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pericfg", "syscon"; 134f2ce7014SSascha Hauer reg = <0 0x10003000 0 0x1000>; 135f2ce7014SSascha Hauer #clock-cells = <1>; 136f2ce7014SSascha Hauer #reset-cells = <1>; 137f2ce7014SSascha Hauer }; 138f2ce7014SSascha Hauer 139f2ce7014SSascha Hauer syscfg_pctl_a: syscfg_pctl_a@10005000 { 140f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 141f2ce7014SSascha Hauer reg = <0 0x10005000 0 0x1000>; 142f2ce7014SSascha Hauer }; 143f2ce7014SSascha Hauer 144f2ce7014SSascha Hauer pio: pinctrl@0x10005000 { 145359f9365SHongzhou Yang compatible = "mediatek,mt8173-pinctrl"; 1466769b93cSYingjoe Chen reg = <0 0x1000b000 0 0x1000>; 147359f9365SHongzhou Yang mediatek,pctl-regmap = <&syscfg_pctl_a>; 148359f9365SHongzhou Yang pins-are-numbered; 149359f9365SHongzhou Yang gpio-controller; 150359f9365SHongzhou Yang #gpio-cells = <2>; 151359f9365SHongzhou Yang interrupt-controller; 152359f9365SHongzhou Yang #interrupt-cells = <2>; 153359f9365SHongzhou Yang interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 154359f9365SHongzhou Yang <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 155359f9365SHongzhou Yang <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 156091cf598SEddie Huang 157091cf598SEddie Huang i2c0_pins_a: i2c0 { 158091cf598SEddie Huang pins1 { 159091cf598SEddie Huang pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 160091cf598SEddie Huang <MT8173_PIN_46_SCL0__FUNC_SCL0>; 161091cf598SEddie Huang bias-disable; 162091cf598SEddie Huang }; 163359f9365SHongzhou Yang }; 164359f9365SHongzhou Yang 165091cf598SEddie Huang i2c1_pins_a: i2c1 { 166091cf598SEddie Huang pins1 { 167091cf598SEddie Huang pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 168091cf598SEddie Huang <MT8173_PIN_126_SCL1__FUNC_SCL1>; 169091cf598SEddie Huang bias-disable; 170091cf598SEddie Huang }; 171091cf598SEddie Huang }; 172091cf598SEddie Huang 173091cf598SEddie Huang i2c2_pins_a: i2c2 { 174091cf598SEddie Huang pins1 { 175091cf598SEddie Huang pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 176091cf598SEddie Huang <MT8173_PIN_44_SCL2__FUNC_SCL2>; 177091cf598SEddie Huang bias-disable; 178091cf598SEddie Huang }; 179091cf598SEddie Huang }; 180091cf598SEddie Huang 181091cf598SEddie Huang i2c3_pins_a: i2c3 { 182091cf598SEddie Huang pins1 { 183091cf598SEddie Huang pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 184091cf598SEddie Huang <MT8173_PIN_107_SCL3__FUNC_SCL3>; 185091cf598SEddie Huang bias-disable; 186091cf598SEddie Huang }; 187091cf598SEddie Huang }; 188091cf598SEddie Huang 189091cf598SEddie Huang i2c4_pins_a: i2c4 { 190091cf598SEddie Huang pins1 { 191091cf598SEddie Huang pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 192091cf598SEddie Huang <MT8173_PIN_134_SCL4__FUNC_SCL4>; 193091cf598SEddie Huang bias-disable; 194091cf598SEddie Huang }; 195091cf598SEddie Huang }; 196091cf598SEddie Huang 197091cf598SEddie Huang i2c6_pins_a: i2c6 { 198091cf598SEddie Huang pins1 { 199091cf598SEddie Huang pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 200091cf598SEddie Huang <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 201091cf598SEddie Huang bias-disable; 202091cf598SEddie Huang }; 203091cf598SEddie Huang }; 2046769b93cSYingjoe Chen }; 2056769b93cSYingjoe Chen 206c010ff53SSascha Hauer scpsys: scpsys@10006000 { 207c010ff53SSascha Hauer compatible = "mediatek,mt8173-scpsys"; 208c010ff53SSascha Hauer #power-domain-cells = <1>; 209c010ff53SSascha Hauer reg = <0 0x10006000 0 0x1000>; 210c010ff53SSascha Hauer clocks = <&clk26m>, 211c010ff53SSascha Hauer <&topckgen CLK_TOP_MM_SEL>; 212c010ff53SSascha Hauer clock-names = "mfg", "mm"; 213c010ff53SSascha Hauer infracfg = <&infracfg>; 214c010ff53SSascha Hauer }; 215c010ff53SSascha Hauer 21613421b3eSEddie Huang watchdog: watchdog@10007000 { 21713421b3eSEddie Huang compatible = "mediatek,mt8173-wdt", 21813421b3eSEddie Huang "mediatek,mt6589-wdt"; 21913421b3eSEddie Huang reg = <0 0x10007000 0 0x100>; 22013421b3eSEddie Huang }; 22113421b3eSEddie Huang 2226cf15fc2SSascha Hauer pwrap: pwrap@1000d000 { 2236cf15fc2SSascha Hauer compatible = "mediatek,mt8173-pwrap"; 2246cf15fc2SSascha Hauer reg = <0 0x1000d000 0 0x1000>; 2256cf15fc2SSascha Hauer reg-names = "pwrap"; 2266cf15fc2SSascha Hauer interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 2276cf15fc2SSascha Hauer resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 2286cf15fc2SSascha Hauer reset-names = "pwrap"; 2296cf15fc2SSascha Hauer clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 2306cf15fc2SSascha Hauer clock-names = "spi", "wrap"; 2316cf15fc2SSascha Hauer }; 2326cf15fc2SSascha Hauer 233b3a37248SEddie Huang sysirq: intpol-controller@10200620 { 234b3a37248SEddie Huang compatible = "mediatek,mt8173-sysirq", 235b3a37248SEddie Huang "mediatek,mt6577-sysirq"; 236b3a37248SEddie Huang interrupt-controller; 237b3a37248SEddie Huang #interrupt-cells = <3>; 238b3a37248SEddie Huang interrupt-parent = <&gic>; 239b3a37248SEddie Huang reg = <0 0x10200620 0 0x20>; 240b3a37248SEddie Huang }; 241b3a37248SEddie Huang 242f2ce7014SSascha Hauer apmixedsys: clock-controller@10209000 { 243f2ce7014SSascha Hauer compatible = "mediatek,mt8173-apmixedsys"; 244f2ce7014SSascha Hauer reg = <0 0x10209000 0 0x1000>; 245f2ce7014SSascha Hauer #clock-cells = <1>; 246f2ce7014SSascha Hauer }; 247f2ce7014SSascha Hauer 248b3a37248SEddie Huang gic: interrupt-controller@10220000 { 249b3a37248SEddie Huang compatible = "arm,gic-400"; 250b3a37248SEddie Huang #interrupt-cells = <3>; 251b3a37248SEddie Huang interrupt-parent = <&gic>; 252b3a37248SEddie Huang interrupt-controller; 253b3a37248SEddie Huang reg = <0 0x10221000 0 0x1000>, 254b3a37248SEddie Huang <0 0x10222000 0 0x2000>, 255b3a37248SEddie Huang <0 0x10224000 0 0x2000>, 256b3a37248SEddie Huang <0 0x10226000 0 0x2000>; 257b3a37248SEddie Huang interrupts = <GIC_PPI 9 258b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 259b3a37248SEddie Huang }; 260b3a37248SEddie Huang 261b3a37248SEddie Huang uart0: serial@11002000 { 262b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 263b3a37248SEddie Huang "mediatek,mt6577-uart"; 264b3a37248SEddie Huang reg = <0 0x11002000 0 0x400>; 265b3a37248SEddie Huang interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 2660e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 2670e84faa1SSascha Hauer clock-names = "baud", "bus"; 268b3a37248SEddie Huang status = "disabled"; 269b3a37248SEddie Huang }; 270b3a37248SEddie Huang 271b3a37248SEddie Huang uart1: serial@11003000 { 272b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 273b3a37248SEddie Huang "mediatek,mt6577-uart"; 274b3a37248SEddie Huang reg = <0 0x11003000 0 0x400>; 275b3a37248SEddie Huang interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 2760e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 2770e84faa1SSascha Hauer clock-names = "baud", "bus"; 278b3a37248SEddie Huang status = "disabled"; 279b3a37248SEddie Huang }; 280b3a37248SEddie Huang 281b3a37248SEddie Huang uart2: serial@11004000 { 282b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 283b3a37248SEddie Huang "mediatek,mt6577-uart"; 284b3a37248SEddie Huang reg = <0 0x11004000 0 0x400>; 285b3a37248SEddie Huang interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 2860e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 2870e84faa1SSascha Hauer clock-names = "baud", "bus"; 288b3a37248SEddie Huang status = "disabled"; 289b3a37248SEddie Huang }; 290b3a37248SEddie Huang 291b3a37248SEddie Huang uart3: serial@11005000 { 292b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 293b3a37248SEddie Huang "mediatek,mt6577-uart"; 294b3a37248SEddie Huang reg = <0 0x11005000 0 0x400>; 295b3a37248SEddie Huang interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 2960e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 2970e84faa1SSascha Hauer clock-names = "baud", "bus"; 298b3a37248SEddie Huang status = "disabled"; 299b3a37248SEddie Huang }; 300091cf598SEddie Huang 301091cf598SEddie Huang i2c0: i2c@11007000 { 302091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 303091cf598SEddie Huang reg = <0 0x11007000 0 0x70>, 304091cf598SEddie Huang <0 0x11000100 0 0x80>; 305091cf598SEddie Huang interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 306091cf598SEddie Huang clock-div = <16>; 307091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C0>, 308091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 309091cf598SEddie Huang clock-names = "main", "dma"; 310091cf598SEddie Huang pinctrl-names = "default"; 311091cf598SEddie Huang pinctrl-0 = <&i2c0_pins_a>; 312091cf598SEddie Huang #address-cells = <1>; 313091cf598SEddie Huang #size-cells = <0>; 314091cf598SEddie Huang status = "disabled"; 315091cf598SEddie Huang }; 316091cf598SEddie Huang 317091cf598SEddie Huang i2c1: i2c@11008000 { 318091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 319091cf598SEddie Huang reg = <0 0x11008000 0 0x70>, 320091cf598SEddie Huang <0 0x11000180 0 0x80>; 321091cf598SEddie Huang interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 322091cf598SEddie Huang clock-div = <16>; 323091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C1>, 324091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 325091cf598SEddie Huang clock-names = "main", "dma"; 326091cf598SEddie Huang pinctrl-names = "default"; 327091cf598SEddie Huang pinctrl-0 = <&i2c1_pins_a>; 328091cf598SEddie Huang #address-cells = <1>; 329091cf598SEddie Huang #size-cells = <0>; 330091cf598SEddie Huang status = "disabled"; 331091cf598SEddie Huang }; 332091cf598SEddie Huang 333091cf598SEddie Huang i2c2: i2c@11009000 { 334091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 335091cf598SEddie Huang reg = <0 0x11009000 0 0x70>, 336091cf598SEddie Huang <0 0x11000200 0 0x80>; 337091cf598SEddie Huang interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 338091cf598SEddie Huang clock-div = <16>; 339091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C2>, 340091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 341091cf598SEddie Huang clock-names = "main", "dma"; 342091cf598SEddie Huang pinctrl-names = "default"; 343091cf598SEddie Huang pinctrl-0 = <&i2c2_pins_a>; 344091cf598SEddie Huang #address-cells = <1>; 345091cf598SEddie Huang #size-cells = <0>; 346091cf598SEddie Huang status = "disabled"; 347091cf598SEddie Huang }; 348091cf598SEddie Huang 349091cf598SEddie Huang i2c3: i2c3@11010000 { 350091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 351091cf598SEddie Huang reg = <0 0x11010000 0 0x70>, 352091cf598SEddie Huang <0 0x11000280 0 0x80>; 353091cf598SEddie Huang interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 354091cf598SEddie Huang clock-div = <16>; 355091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C3>, 356091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 357091cf598SEddie Huang clock-names = "main", "dma"; 358091cf598SEddie Huang pinctrl-names = "default"; 359091cf598SEddie Huang pinctrl-0 = <&i2c3_pins_a>; 360091cf598SEddie Huang #address-cells = <1>; 361091cf598SEddie Huang #size-cells = <0>; 362091cf598SEddie Huang status = "disabled"; 363091cf598SEddie Huang }; 364091cf598SEddie Huang 365091cf598SEddie Huang i2c4: i2c4@11011000 { 366091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 367091cf598SEddie Huang reg = <0 0x11011000 0 0x70>, 368091cf598SEddie Huang <0 0x11000300 0 0x80>; 369091cf598SEddie Huang interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 370091cf598SEddie Huang clock-div = <16>; 371091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C4>, 372091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 373091cf598SEddie Huang clock-names = "main", "dma"; 374091cf598SEddie Huang pinctrl-names = "default"; 375091cf598SEddie Huang pinctrl-0 = <&i2c4_pins_a>; 376091cf598SEddie Huang #address-cells = <1>; 377091cf598SEddie Huang #size-cells = <0>; 378091cf598SEddie Huang status = "disabled"; 379091cf598SEddie Huang }; 380091cf598SEddie Huang 381091cf598SEddie Huang i2c6: i2c6@11013000 { 382091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 383091cf598SEddie Huang reg = <0 0x11013000 0 0x70>, 384091cf598SEddie Huang <0 0x11000080 0 0x80>; 385091cf598SEddie Huang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 386091cf598SEddie Huang clock-div = <16>; 387091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C6>, 388091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 389091cf598SEddie Huang clock-names = "main", "dma"; 390091cf598SEddie Huang pinctrl-names = "default"; 391091cf598SEddie Huang pinctrl-0 = <&i2c6_pins_a>; 392091cf598SEddie Huang #address-cells = <1>; 393091cf598SEddie Huang #size-cells = <0>; 394091cf598SEddie Huang status = "disabled"; 395091cf598SEddie Huang }; 396b3a37248SEddie Huang }; 397b3a37248SEddie Huang}; 398b3a37248SEddie Huang 399