1b3a37248SEddie Huang/* 2b3a37248SEddie Huang * Copyright (c) 2014 MediaTek Inc. 3b3a37248SEddie Huang * Author: Eddie Huang <eddie.huang@mediatek.com> 4b3a37248SEddie Huang * 5b3a37248SEddie Huang * This program is free software; you can redistribute it and/or modify 6b3a37248SEddie Huang * it under the terms of the GNU General Public License version 2 as 7b3a37248SEddie Huang * published by the Free Software Foundation. 8b3a37248SEddie Huang * 9b3a37248SEddie Huang * This program is distributed in the hope that it will be useful, 10b3a37248SEddie Huang * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11b3a37248SEddie Huang * GNU General Public License for more details. 12b3a37248SEddie Huang */ 13b3a37248SEddie Huang 14b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/irq.h> 15b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/arm-gic.h> 16b3a37248SEddie Huang 17b3a37248SEddie Huang/ { 18b3a37248SEddie Huang compatible = "mediatek,mt8173"; 19b3a37248SEddie Huang interrupt-parent = <&sysirq>; 20b3a37248SEddie Huang #address-cells = <2>; 21b3a37248SEddie Huang #size-cells = <2>; 22b3a37248SEddie Huang 23b3a37248SEddie Huang cpus { 24b3a37248SEddie Huang #address-cells = <1>; 25b3a37248SEddie Huang #size-cells = <0>; 26b3a37248SEddie Huang 27b3a37248SEddie Huang cpu-map { 28b3a37248SEddie Huang cluster0 { 29b3a37248SEddie Huang core0 { 30b3a37248SEddie Huang cpu = <&cpu0>; 31b3a37248SEddie Huang }; 32b3a37248SEddie Huang core1 { 33b3a37248SEddie Huang cpu = <&cpu1>; 34b3a37248SEddie Huang }; 35b3a37248SEddie Huang }; 36b3a37248SEddie Huang 37b3a37248SEddie Huang cluster1 { 38b3a37248SEddie Huang core0 { 39b3a37248SEddie Huang cpu = <&cpu2>; 40b3a37248SEddie Huang }; 41b3a37248SEddie Huang core1 { 42b3a37248SEddie Huang cpu = <&cpu3>; 43b3a37248SEddie Huang }; 44b3a37248SEddie Huang }; 45b3a37248SEddie Huang }; 46b3a37248SEddie Huang 47b3a37248SEddie Huang cpu0: cpu@0 { 48b3a37248SEddie Huang device_type = "cpu"; 49b3a37248SEddie Huang compatible = "arm,cortex-a53"; 50b3a37248SEddie Huang reg = <0x000>; 51b3a37248SEddie Huang }; 52b3a37248SEddie Huang 53b3a37248SEddie Huang cpu1: cpu@1 { 54b3a37248SEddie Huang device_type = "cpu"; 55b3a37248SEddie Huang compatible = "arm,cortex-a53"; 56b3a37248SEddie Huang reg = <0x001>; 57b3a37248SEddie Huang enable-method = "psci"; 58b3a37248SEddie Huang }; 59b3a37248SEddie Huang 60b3a37248SEddie Huang cpu2: cpu@100 { 61b3a37248SEddie Huang device_type = "cpu"; 62b3a37248SEddie Huang compatible = "arm,cortex-a57"; 63b3a37248SEddie Huang reg = <0x100>; 64b3a37248SEddie Huang enable-method = "psci"; 65b3a37248SEddie Huang }; 66b3a37248SEddie Huang 67b3a37248SEddie Huang cpu3: cpu@101 { 68b3a37248SEddie Huang device_type = "cpu"; 69b3a37248SEddie Huang compatible = "arm,cortex-a57"; 70b3a37248SEddie Huang reg = <0x101>; 71b3a37248SEddie Huang enable-method = "psci"; 72b3a37248SEddie Huang }; 73b3a37248SEddie Huang }; 74b3a37248SEddie Huang 75b3a37248SEddie Huang psci { 76b3a37248SEddie Huang compatible = "arm,psci"; 77b3a37248SEddie Huang method = "smc"; 78b3a37248SEddie Huang cpu_suspend = <0x84000001>; 79b3a37248SEddie Huang cpu_off = <0x84000002>; 80b3a37248SEddie Huang cpu_on = <0x84000003>; 81b3a37248SEddie Huang }; 82b3a37248SEddie Huang 83b3a37248SEddie Huang uart_clk: dummy26m { 84b3a37248SEddie Huang compatible = "fixed-clock"; 85b3a37248SEddie Huang clock-frequency = <26000000>; 86b3a37248SEddie Huang #clock-cells = <0>; 87b3a37248SEddie Huang }; 88b3a37248SEddie Huang 89b3a37248SEddie Huang timer { 90b3a37248SEddie Huang compatible = "arm,armv8-timer"; 91b3a37248SEddie Huang interrupt-parent = <&gic>; 92b3a37248SEddie Huang interrupts = <GIC_PPI 13 93b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 94b3a37248SEddie Huang <GIC_PPI 14 95b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 96b3a37248SEddie Huang <GIC_PPI 11 97b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 98b3a37248SEddie Huang <GIC_PPI 10 99b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 100b3a37248SEddie Huang }; 101b3a37248SEddie Huang 102b3a37248SEddie Huang soc { 103b3a37248SEddie Huang #address-cells = <2>; 104b3a37248SEddie Huang #size-cells = <2>; 105b3a37248SEddie Huang compatible = "simple-bus"; 106b3a37248SEddie Huang ranges; 107b3a37248SEddie Huang 108b3a37248SEddie Huang sysirq: intpol-controller@10200620 { 109b3a37248SEddie Huang compatible = "mediatek,mt8173-sysirq", 110b3a37248SEddie Huang "mediatek,mt6577-sysirq"; 111b3a37248SEddie Huang interrupt-controller; 112b3a37248SEddie Huang #interrupt-cells = <3>; 113b3a37248SEddie Huang interrupt-parent = <&gic>; 114b3a37248SEddie Huang reg = <0 0x10200620 0 0x20>; 115b3a37248SEddie Huang }; 116b3a37248SEddie Huang 117b3a37248SEddie Huang gic: interrupt-controller@10220000 { 118b3a37248SEddie Huang compatible = "arm,gic-400"; 119b3a37248SEddie Huang #interrupt-cells = <3>; 120b3a37248SEddie Huang interrupt-parent = <&gic>; 121b3a37248SEddie Huang interrupt-controller; 122b3a37248SEddie Huang reg = <0 0x10221000 0 0x1000>, 123b3a37248SEddie Huang <0 0x10222000 0 0x2000>, 124b3a37248SEddie Huang <0 0x10224000 0 0x2000>, 125b3a37248SEddie Huang <0 0x10226000 0 0x2000>; 126b3a37248SEddie Huang interrupts = <GIC_PPI 9 127b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 128b3a37248SEddie Huang }; 129b3a37248SEddie Huang 130b3a37248SEddie Huang uart0: serial@11002000 { 131b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 132b3a37248SEddie Huang "mediatek,mt6577-uart"; 133b3a37248SEddie Huang reg = <0 0x11002000 0 0x400>; 134b3a37248SEddie Huang interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 135b3a37248SEddie Huang clocks = <&uart_clk>; 136b3a37248SEddie Huang status = "disabled"; 137b3a37248SEddie Huang }; 138b3a37248SEddie Huang 139b3a37248SEddie Huang uart1: serial@11003000 { 140b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 141b3a37248SEddie Huang "mediatek,mt6577-uart"; 142b3a37248SEddie Huang reg = <0 0x11003000 0 0x400>; 143b3a37248SEddie Huang interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 144b3a37248SEddie Huang clocks = <&uart_clk>; 145b3a37248SEddie Huang status = "disabled"; 146b3a37248SEddie Huang }; 147b3a37248SEddie Huang 148b3a37248SEddie Huang uart2: serial@11004000 { 149b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 150b3a37248SEddie Huang "mediatek,mt6577-uart"; 151b3a37248SEddie Huang reg = <0 0x11004000 0 0x400>; 152b3a37248SEddie Huang interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 153b3a37248SEddie Huang clocks = <&uart_clk>; 154b3a37248SEddie Huang status = "disabled"; 155b3a37248SEddie Huang }; 156b3a37248SEddie Huang 157b3a37248SEddie Huang uart3: serial@11005000 { 158b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 159b3a37248SEddie Huang "mediatek,mt6577-uart"; 160b3a37248SEddie Huang reg = <0 0x11005000 0 0x400>; 161b3a37248SEddie Huang interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 162b3a37248SEddie Huang clocks = <&uart_clk>; 163b3a37248SEddie Huang status = "disabled"; 164b3a37248SEddie Huang }; 165b3a37248SEddie Huang }; 166b3a37248SEddie Huang 167b3a37248SEddie Huang}; 168b3a37248SEddie Huang 169