1b3a37248SEddie Huang/* 2b3a37248SEddie Huang * Copyright (c) 2014 MediaTek Inc. 3b3a37248SEddie Huang * Author: Eddie Huang <eddie.huang@mediatek.com> 4b3a37248SEddie Huang * 5b3a37248SEddie Huang * This program is free software; you can redistribute it and/or modify 6b3a37248SEddie Huang * it under the terms of the GNU General Public License version 2 as 7b3a37248SEddie Huang * published by the Free Software Foundation. 8b3a37248SEddie Huang * 9b3a37248SEddie Huang * This program is distributed in the hope that it will be useful, 10b3a37248SEddie Huang * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11b3a37248SEddie Huang * GNU General Public License for more details. 12b3a37248SEddie Huang */ 13b3a37248SEddie Huang 14f2ce7014SSascha Hauer#include <dt-bindings/clock/mt8173-clk.h> 15b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/irq.h> 16b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/arm-gic.h> 176cf15fc2SSascha Hauer#include <dt-bindings/reset-controller/mt8173-resets.h> 18359f9365SHongzhou Yang#include "mt8173-pinfunc.h" 19b3a37248SEddie Huang 20b3a37248SEddie Huang/ { 21b3a37248SEddie Huang compatible = "mediatek,mt8173"; 22b3a37248SEddie Huang interrupt-parent = <&sysirq>; 23b3a37248SEddie Huang #address-cells = <2>; 24b3a37248SEddie Huang #size-cells = <2>; 25b3a37248SEddie Huang 26b3a37248SEddie Huang cpus { 27b3a37248SEddie Huang #address-cells = <1>; 28b3a37248SEddie Huang #size-cells = <0>; 29b3a37248SEddie Huang 30b3a37248SEddie Huang cpu-map { 31b3a37248SEddie Huang cluster0 { 32b3a37248SEddie Huang core0 { 33b3a37248SEddie Huang cpu = <&cpu0>; 34b3a37248SEddie Huang }; 35b3a37248SEddie Huang core1 { 36b3a37248SEddie Huang cpu = <&cpu1>; 37b3a37248SEddie Huang }; 38b3a37248SEddie Huang }; 39b3a37248SEddie Huang 40b3a37248SEddie Huang cluster1 { 41b3a37248SEddie Huang core0 { 42b3a37248SEddie Huang cpu = <&cpu2>; 43b3a37248SEddie Huang }; 44b3a37248SEddie Huang core1 { 45b3a37248SEddie Huang cpu = <&cpu3>; 46b3a37248SEddie Huang }; 47b3a37248SEddie Huang }; 48b3a37248SEddie Huang }; 49b3a37248SEddie Huang 50b3a37248SEddie Huang cpu0: cpu@0 { 51b3a37248SEddie Huang device_type = "cpu"; 52b3a37248SEddie Huang compatible = "arm,cortex-a53"; 53b3a37248SEddie Huang reg = <0x000>; 54ad4df7a5SHoward Chen enable-method = "psci"; 55ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 56b3a37248SEddie Huang }; 57b3a37248SEddie Huang 58b3a37248SEddie Huang cpu1: cpu@1 { 59b3a37248SEddie Huang device_type = "cpu"; 60b3a37248SEddie Huang compatible = "arm,cortex-a53"; 61b3a37248SEddie Huang reg = <0x001>; 62b3a37248SEddie Huang enable-method = "psci"; 63ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 64b3a37248SEddie Huang }; 65b3a37248SEddie Huang 66b3a37248SEddie Huang cpu2: cpu@100 { 67b3a37248SEddie Huang device_type = "cpu"; 68b3a37248SEddie Huang compatible = "arm,cortex-a57"; 69b3a37248SEddie Huang reg = <0x100>; 70b3a37248SEddie Huang enable-method = "psci"; 71ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 72b3a37248SEddie Huang }; 73b3a37248SEddie Huang 74b3a37248SEddie Huang cpu3: cpu@101 { 75b3a37248SEddie Huang device_type = "cpu"; 76b3a37248SEddie Huang compatible = "arm,cortex-a57"; 77b3a37248SEddie Huang reg = <0x101>; 78b3a37248SEddie Huang enable-method = "psci"; 79ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 80ad4df7a5SHoward Chen }; 81ad4df7a5SHoward Chen 82ad4df7a5SHoward Chen idle-states { 83ad4df7a5SHoward Chen entry-method = "arm,psci"; 84ad4df7a5SHoward Chen 85ad4df7a5SHoward Chen CPU_SLEEP_0: cpu-sleep-0 { 86ad4df7a5SHoward Chen compatible = "arm,idle-state"; 87ad4df7a5SHoward Chen local-timer-stop; 88ad4df7a5SHoward Chen entry-latency-us = <639>; 89ad4df7a5SHoward Chen exit-latency-us = <680>; 90ad4df7a5SHoward Chen min-residency-us = <1088>; 91ad4df7a5SHoward Chen arm,psci-suspend-param = <0x0010000>; 92ad4df7a5SHoward Chen }; 93b3a37248SEddie Huang }; 94b3a37248SEddie Huang }; 95b3a37248SEddie Huang 96b3a37248SEddie Huang psci { 97b3a37248SEddie Huang compatible = "arm,psci"; 98b3a37248SEddie Huang method = "smc"; 99b3a37248SEddie Huang cpu_suspend = <0x84000001>; 100b3a37248SEddie Huang cpu_off = <0x84000002>; 101b3a37248SEddie Huang cpu_on = <0x84000003>; 102b3a37248SEddie Huang }; 103b3a37248SEddie Huang 104f2ce7014SSascha Hauer clk26m: oscillator@0 { 105f2ce7014SSascha Hauer compatible = "fixed-clock"; 106f2ce7014SSascha Hauer #clock-cells = <0>; 107f2ce7014SSascha Hauer clock-frequency = <26000000>; 108f2ce7014SSascha Hauer clock-output-names = "clk26m"; 109f2ce7014SSascha Hauer }; 110f2ce7014SSascha Hauer 111f2ce7014SSascha Hauer clk32k: oscillator@1 { 112f2ce7014SSascha Hauer compatible = "fixed-clock"; 113f2ce7014SSascha Hauer #clock-cells = <0>; 114f2ce7014SSascha Hauer clock-frequency = <32000>; 115f2ce7014SSascha Hauer clock-output-names = "clk32k"; 116f2ce7014SSascha Hauer }; 117f2ce7014SSascha Hauer 118b3a37248SEddie Huang timer { 119b3a37248SEddie Huang compatible = "arm,armv8-timer"; 120b3a37248SEddie Huang interrupt-parent = <&gic>; 121b3a37248SEddie Huang interrupts = <GIC_PPI 13 122b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 123b3a37248SEddie Huang <GIC_PPI 14 124b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 125b3a37248SEddie Huang <GIC_PPI 11 126b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 127b3a37248SEddie Huang <GIC_PPI 10 128b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 129b3a37248SEddie Huang }; 130b3a37248SEddie Huang 131b3a37248SEddie Huang soc { 132b3a37248SEddie Huang #address-cells = <2>; 133b3a37248SEddie Huang #size-cells = <2>; 134b3a37248SEddie Huang compatible = "simple-bus"; 135b3a37248SEddie Huang ranges; 136b3a37248SEddie Huang 137f2ce7014SSascha Hauer topckgen: clock-controller@10000000 { 138f2ce7014SSascha Hauer compatible = "mediatek,mt8173-topckgen"; 139f2ce7014SSascha Hauer reg = <0 0x10000000 0 0x1000>; 140f2ce7014SSascha Hauer #clock-cells = <1>; 141f2ce7014SSascha Hauer }; 142f2ce7014SSascha Hauer 143f2ce7014SSascha Hauer infracfg: power-controller@10001000 { 144f2ce7014SSascha Hauer compatible = "mediatek,mt8173-infracfg", "syscon"; 145f2ce7014SSascha Hauer reg = <0 0x10001000 0 0x1000>; 146f2ce7014SSascha Hauer #clock-cells = <1>; 147f2ce7014SSascha Hauer #reset-cells = <1>; 148f2ce7014SSascha Hauer }; 149f2ce7014SSascha Hauer 150f2ce7014SSascha Hauer pericfg: power-controller@10003000 { 151f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pericfg", "syscon"; 152f2ce7014SSascha Hauer reg = <0 0x10003000 0 0x1000>; 153f2ce7014SSascha Hauer #clock-cells = <1>; 154f2ce7014SSascha Hauer #reset-cells = <1>; 155f2ce7014SSascha Hauer }; 156f2ce7014SSascha Hauer 157f2ce7014SSascha Hauer syscfg_pctl_a: syscfg_pctl_a@10005000 { 158f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 159f2ce7014SSascha Hauer reg = <0 0x10005000 0 0x1000>; 160f2ce7014SSascha Hauer }; 161f2ce7014SSascha Hauer 162f2ce7014SSascha Hauer pio: pinctrl@0x10005000 { 163359f9365SHongzhou Yang compatible = "mediatek,mt8173-pinctrl"; 1646769b93cSYingjoe Chen reg = <0 0x1000b000 0 0x1000>; 165359f9365SHongzhou Yang mediatek,pctl-regmap = <&syscfg_pctl_a>; 166359f9365SHongzhou Yang pins-are-numbered; 167359f9365SHongzhou Yang gpio-controller; 168359f9365SHongzhou Yang #gpio-cells = <2>; 169359f9365SHongzhou Yang interrupt-controller; 170359f9365SHongzhou Yang #interrupt-cells = <2>; 171359f9365SHongzhou Yang interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 172359f9365SHongzhou Yang <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 173359f9365SHongzhou Yang <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 174091cf598SEddie Huang 175091cf598SEddie Huang i2c0_pins_a: i2c0 { 176091cf598SEddie Huang pins1 { 177091cf598SEddie Huang pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 178091cf598SEddie Huang <MT8173_PIN_46_SCL0__FUNC_SCL0>; 179091cf598SEddie Huang bias-disable; 180091cf598SEddie Huang }; 181359f9365SHongzhou Yang }; 182359f9365SHongzhou Yang 183091cf598SEddie Huang i2c1_pins_a: i2c1 { 184091cf598SEddie Huang pins1 { 185091cf598SEddie Huang pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 186091cf598SEddie Huang <MT8173_PIN_126_SCL1__FUNC_SCL1>; 187091cf598SEddie Huang bias-disable; 188091cf598SEddie Huang }; 189091cf598SEddie Huang }; 190091cf598SEddie Huang 191091cf598SEddie Huang i2c2_pins_a: i2c2 { 192091cf598SEddie Huang pins1 { 193091cf598SEddie Huang pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 194091cf598SEddie Huang <MT8173_PIN_44_SCL2__FUNC_SCL2>; 195091cf598SEddie Huang bias-disable; 196091cf598SEddie Huang }; 197091cf598SEddie Huang }; 198091cf598SEddie Huang 199091cf598SEddie Huang i2c3_pins_a: i2c3 { 200091cf598SEddie Huang pins1 { 201091cf598SEddie Huang pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 202091cf598SEddie Huang <MT8173_PIN_107_SCL3__FUNC_SCL3>; 203091cf598SEddie Huang bias-disable; 204091cf598SEddie Huang }; 205091cf598SEddie Huang }; 206091cf598SEddie Huang 207091cf598SEddie Huang i2c4_pins_a: i2c4 { 208091cf598SEddie Huang pins1 { 209091cf598SEddie Huang pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 210091cf598SEddie Huang <MT8173_PIN_134_SCL4__FUNC_SCL4>; 211091cf598SEddie Huang bias-disable; 212091cf598SEddie Huang }; 213091cf598SEddie Huang }; 214091cf598SEddie Huang 215091cf598SEddie Huang i2c6_pins_a: i2c6 { 216091cf598SEddie Huang pins1 { 217091cf598SEddie Huang pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 218091cf598SEddie Huang <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 219091cf598SEddie Huang bias-disable; 220091cf598SEddie Huang }; 221091cf598SEddie Huang }; 2226769b93cSYingjoe Chen }; 2236769b93cSYingjoe Chen 224c010ff53SSascha Hauer scpsys: scpsys@10006000 { 225c010ff53SSascha Hauer compatible = "mediatek,mt8173-scpsys"; 226c010ff53SSascha Hauer #power-domain-cells = <1>; 227c010ff53SSascha Hauer reg = <0 0x10006000 0 0x1000>; 228c010ff53SSascha Hauer clocks = <&clk26m>, 229c010ff53SSascha Hauer <&topckgen CLK_TOP_MM_SEL>; 230c010ff53SSascha Hauer clock-names = "mfg", "mm"; 231c010ff53SSascha Hauer infracfg = <&infracfg>; 232c010ff53SSascha Hauer }; 233c010ff53SSascha Hauer 23413421b3eSEddie Huang watchdog: watchdog@10007000 { 23513421b3eSEddie Huang compatible = "mediatek,mt8173-wdt", 23613421b3eSEddie Huang "mediatek,mt6589-wdt"; 23713421b3eSEddie Huang reg = <0 0x10007000 0 0x100>; 23813421b3eSEddie Huang }; 23913421b3eSEddie Huang 2406cf15fc2SSascha Hauer pwrap: pwrap@1000d000 { 2416cf15fc2SSascha Hauer compatible = "mediatek,mt8173-pwrap"; 2426cf15fc2SSascha Hauer reg = <0 0x1000d000 0 0x1000>; 2436cf15fc2SSascha Hauer reg-names = "pwrap"; 2446cf15fc2SSascha Hauer interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 2456cf15fc2SSascha Hauer resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 2466cf15fc2SSascha Hauer reset-names = "pwrap"; 2476cf15fc2SSascha Hauer clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 2486cf15fc2SSascha Hauer clock-names = "spi", "wrap"; 2496cf15fc2SSascha Hauer }; 2506cf15fc2SSascha Hauer 251b3a37248SEddie Huang sysirq: intpol-controller@10200620 { 252b3a37248SEddie Huang compatible = "mediatek,mt8173-sysirq", 253b3a37248SEddie Huang "mediatek,mt6577-sysirq"; 254b3a37248SEddie Huang interrupt-controller; 255b3a37248SEddie Huang #interrupt-cells = <3>; 256b3a37248SEddie Huang interrupt-parent = <&gic>; 257b3a37248SEddie Huang reg = <0 0x10200620 0 0x20>; 258b3a37248SEddie Huang }; 259b3a37248SEddie Huang 260f2ce7014SSascha Hauer apmixedsys: clock-controller@10209000 { 261f2ce7014SSascha Hauer compatible = "mediatek,mt8173-apmixedsys"; 262f2ce7014SSascha Hauer reg = <0 0x10209000 0 0x1000>; 263f2ce7014SSascha Hauer #clock-cells = <1>; 264f2ce7014SSascha Hauer }; 265f2ce7014SSascha Hauer 266b3a37248SEddie Huang gic: interrupt-controller@10220000 { 267b3a37248SEddie Huang compatible = "arm,gic-400"; 268b3a37248SEddie Huang #interrupt-cells = <3>; 269b3a37248SEddie Huang interrupt-parent = <&gic>; 270b3a37248SEddie Huang interrupt-controller; 271b3a37248SEddie Huang reg = <0 0x10221000 0 0x1000>, 272b3a37248SEddie Huang <0 0x10222000 0 0x2000>, 273b3a37248SEddie Huang <0 0x10224000 0 0x2000>, 274b3a37248SEddie Huang <0 0x10226000 0 0x2000>; 275b3a37248SEddie Huang interrupts = <GIC_PPI 9 276b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 277b3a37248SEddie Huang }; 278b3a37248SEddie Huang 279b3a37248SEddie Huang uart0: serial@11002000 { 280b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 281b3a37248SEddie Huang "mediatek,mt6577-uart"; 282b3a37248SEddie Huang reg = <0 0x11002000 0 0x400>; 283b3a37248SEddie Huang interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 2840e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 2850e84faa1SSascha Hauer clock-names = "baud", "bus"; 286b3a37248SEddie Huang status = "disabled"; 287b3a37248SEddie Huang }; 288b3a37248SEddie Huang 289b3a37248SEddie Huang uart1: serial@11003000 { 290b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 291b3a37248SEddie Huang "mediatek,mt6577-uart"; 292b3a37248SEddie Huang reg = <0 0x11003000 0 0x400>; 293b3a37248SEddie Huang interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 2940e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 2950e84faa1SSascha Hauer clock-names = "baud", "bus"; 296b3a37248SEddie Huang status = "disabled"; 297b3a37248SEddie Huang }; 298b3a37248SEddie Huang 299b3a37248SEddie Huang uart2: serial@11004000 { 300b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 301b3a37248SEddie Huang "mediatek,mt6577-uart"; 302b3a37248SEddie Huang reg = <0 0x11004000 0 0x400>; 303b3a37248SEddie Huang interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 3040e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 3050e84faa1SSascha Hauer clock-names = "baud", "bus"; 306b3a37248SEddie Huang status = "disabled"; 307b3a37248SEddie Huang }; 308b3a37248SEddie Huang 309b3a37248SEddie Huang uart3: serial@11005000 { 310b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 311b3a37248SEddie Huang "mediatek,mt6577-uart"; 312b3a37248SEddie Huang reg = <0 0x11005000 0 0x400>; 313b3a37248SEddie Huang interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 3140e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 3150e84faa1SSascha Hauer clock-names = "baud", "bus"; 316b3a37248SEddie Huang status = "disabled"; 317b3a37248SEddie Huang }; 318091cf598SEddie Huang 319091cf598SEddie Huang i2c0: i2c@11007000 { 320091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 321091cf598SEddie Huang reg = <0 0x11007000 0 0x70>, 322091cf598SEddie Huang <0 0x11000100 0 0x80>; 323091cf598SEddie Huang interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 324091cf598SEddie Huang clock-div = <16>; 325091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C0>, 326091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 327091cf598SEddie Huang clock-names = "main", "dma"; 328091cf598SEddie Huang pinctrl-names = "default"; 329091cf598SEddie Huang pinctrl-0 = <&i2c0_pins_a>; 330091cf598SEddie Huang #address-cells = <1>; 331091cf598SEddie Huang #size-cells = <0>; 332091cf598SEddie Huang status = "disabled"; 333091cf598SEddie Huang }; 334091cf598SEddie Huang 335091cf598SEddie Huang i2c1: i2c@11008000 { 336091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 337091cf598SEddie Huang reg = <0 0x11008000 0 0x70>, 338091cf598SEddie Huang <0 0x11000180 0 0x80>; 339091cf598SEddie Huang interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 340091cf598SEddie Huang clock-div = <16>; 341091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C1>, 342091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 343091cf598SEddie Huang clock-names = "main", "dma"; 344091cf598SEddie Huang pinctrl-names = "default"; 345091cf598SEddie Huang pinctrl-0 = <&i2c1_pins_a>; 346091cf598SEddie Huang #address-cells = <1>; 347091cf598SEddie Huang #size-cells = <0>; 348091cf598SEddie Huang status = "disabled"; 349091cf598SEddie Huang }; 350091cf598SEddie Huang 351091cf598SEddie Huang i2c2: i2c@11009000 { 352091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 353091cf598SEddie Huang reg = <0 0x11009000 0 0x70>, 354091cf598SEddie Huang <0 0x11000200 0 0x80>; 355091cf598SEddie Huang interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 356091cf598SEddie Huang clock-div = <16>; 357091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C2>, 358091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 359091cf598SEddie Huang clock-names = "main", "dma"; 360091cf598SEddie Huang pinctrl-names = "default"; 361091cf598SEddie Huang pinctrl-0 = <&i2c2_pins_a>; 362091cf598SEddie Huang #address-cells = <1>; 363091cf598SEddie Huang #size-cells = <0>; 364091cf598SEddie Huang status = "disabled"; 365091cf598SEddie Huang }; 366091cf598SEddie Huang 367091cf598SEddie Huang i2c3: i2c3@11010000 { 368091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 369091cf598SEddie Huang reg = <0 0x11010000 0 0x70>, 370091cf598SEddie Huang <0 0x11000280 0 0x80>; 371091cf598SEddie Huang interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 372091cf598SEddie Huang clock-div = <16>; 373091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C3>, 374091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 375091cf598SEddie Huang clock-names = "main", "dma"; 376091cf598SEddie Huang pinctrl-names = "default"; 377091cf598SEddie Huang pinctrl-0 = <&i2c3_pins_a>; 378091cf598SEddie Huang #address-cells = <1>; 379091cf598SEddie Huang #size-cells = <0>; 380091cf598SEddie Huang status = "disabled"; 381091cf598SEddie Huang }; 382091cf598SEddie Huang 383091cf598SEddie Huang i2c4: i2c4@11011000 { 384091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 385091cf598SEddie Huang reg = <0 0x11011000 0 0x70>, 386091cf598SEddie Huang <0 0x11000300 0 0x80>; 387091cf598SEddie Huang interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 388091cf598SEddie Huang clock-div = <16>; 389091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C4>, 390091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 391091cf598SEddie Huang clock-names = "main", "dma"; 392091cf598SEddie Huang pinctrl-names = "default"; 393091cf598SEddie Huang pinctrl-0 = <&i2c4_pins_a>; 394091cf598SEddie Huang #address-cells = <1>; 395091cf598SEddie Huang #size-cells = <0>; 396091cf598SEddie Huang status = "disabled"; 397091cf598SEddie Huang }; 398091cf598SEddie Huang 399091cf598SEddie Huang i2c6: i2c6@11013000 { 400091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 401091cf598SEddie Huang reg = <0 0x11013000 0 0x70>, 402091cf598SEddie Huang <0 0x11000080 0 0x80>; 403091cf598SEddie Huang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 404091cf598SEddie Huang clock-div = <16>; 405091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C6>, 406091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 407091cf598SEddie Huang clock-names = "main", "dma"; 408091cf598SEddie Huang pinctrl-names = "default"; 409091cf598SEddie Huang pinctrl-0 = <&i2c6_pins_a>; 410091cf598SEddie Huang #address-cells = <1>; 411091cf598SEddie Huang #size-cells = <0>; 412091cf598SEddie Huang status = "disabled"; 413091cf598SEddie Huang }; 414b3a37248SEddie Huang }; 415b3a37248SEddie Huang}; 416b3a37248SEddie Huang 417