1b3a37248SEddie Huang/* 2b3a37248SEddie Huang * Copyright (c) 2014 MediaTek Inc. 3b3a37248SEddie Huang * Author: Eddie Huang <eddie.huang@mediatek.com> 4b3a37248SEddie Huang * 5b3a37248SEddie Huang * This program is free software; you can redistribute it and/or modify 6b3a37248SEddie Huang * it under the terms of the GNU General Public License version 2 as 7b3a37248SEddie Huang * published by the Free Software Foundation. 8b3a37248SEddie Huang * 9b3a37248SEddie Huang * This program is distributed in the hope that it will be useful, 10b3a37248SEddie Huang * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11b3a37248SEddie Huang * GNU General Public License for more details. 12b3a37248SEddie Huang */ 13b3a37248SEddie Huang 14f2ce7014SSascha Hauer#include <dt-bindings/clock/mt8173-clk.h> 15b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/irq.h> 16b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/arm-gic.h> 175ff6b3a6SYong Wu#include <dt-bindings/memory/mt8173-larb-port.h> 18bfcce47aSChunfeng Yun#include <dt-bindings/phy/phy.h> 19c02e0e86SKoro Chen#include <dt-bindings/power/mt8173-power.h> 20967313e2SPhilipp Zabel#include <dt-bindings/reset/mt8173-resets.h> 21359f9365SHongzhou Yang#include "mt8173-pinfunc.h" 22b3a37248SEddie Huang 23b3a37248SEddie Huang/ { 24b3a37248SEddie Huang compatible = "mediatek,mt8173"; 25b3a37248SEddie Huang interrupt-parent = <&sysirq>; 26b3a37248SEddie Huang #address-cells = <2>; 27b3a37248SEddie Huang #size-cells = <2>; 28b3a37248SEddie Huang 2981ad4dbaSCK Hu aliases { 3081ad4dbaSCK Hu ovl0 = &ovl0; 3181ad4dbaSCK Hu ovl1 = &ovl1; 3281ad4dbaSCK Hu rdma0 = &rdma0; 3381ad4dbaSCK Hu rdma1 = &rdma1; 3481ad4dbaSCK Hu rdma2 = &rdma2; 3581ad4dbaSCK Hu wdma0 = &wdma0; 3681ad4dbaSCK Hu wdma1 = &wdma1; 3781ad4dbaSCK Hu color0 = &color0; 3881ad4dbaSCK Hu color1 = &color1; 3981ad4dbaSCK Hu split0 = &split0; 4081ad4dbaSCK Hu split1 = &split1; 4181ad4dbaSCK Hu dpi0 = &dpi0; 4281ad4dbaSCK Hu dsi0 = &dsi0; 4381ad4dbaSCK Hu dsi1 = &dsi1; 4481ad4dbaSCK Hu }; 4581ad4dbaSCK Hu 46b3a37248SEddie Huang cpus { 47b3a37248SEddie Huang #address-cells = <1>; 48b3a37248SEddie Huang #size-cells = <0>; 49b3a37248SEddie Huang 50b3a37248SEddie Huang cpu-map { 51b3a37248SEddie Huang cluster0 { 52b3a37248SEddie Huang core0 { 53b3a37248SEddie Huang cpu = <&cpu0>; 54b3a37248SEddie Huang }; 55b3a37248SEddie Huang core1 { 56b3a37248SEddie Huang cpu = <&cpu1>; 57b3a37248SEddie Huang }; 58b3a37248SEddie Huang }; 59b3a37248SEddie Huang 60b3a37248SEddie Huang cluster1 { 61b3a37248SEddie Huang core0 { 62b3a37248SEddie Huang cpu = <&cpu2>; 63b3a37248SEddie Huang }; 64b3a37248SEddie Huang core1 { 65b3a37248SEddie Huang cpu = <&cpu3>; 66b3a37248SEddie Huang }; 67b3a37248SEddie Huang }; 68b3a37248SEddie Huang }; 69b3a37248SEddie Huang 70b3a37248SEddie Huang cpu0: cpu@0 { 71b3a37248SEddie Huang device_type = "cpu"; 72b3a37248SEddie Huang compatible = "arm,cortex-a53"; 73b3a37248SEddie Huang reg = <0x000>; 74ad4df7a5SHoward Chen enable-method = "psci"; 75ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 76b3a37248SEddie Huang }; 77b3a37248SEddie Huang 78b3a37248SEddie Huang cpu1: cpu@1 { 79b3a37248SEddie Huang device_type = "cpu"; 80b3a37248SEddie Huang compatible = "arm,cortex-a53"; 81b3a37248SEddie Huang reg = <0x001>; 82b3a37248SEddie Huang enable-method = "psci"; 83ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 84b3a37248SEddie Huang }; 85b3a37248SEddie Huang 86b3a37248SEddie Huang cpu2: cpu@100 { 87b3a37248SEddie Huang device_type = "cpu"; 88b3a37248SEddie Huang compatible = "arm,cortex-a57"; 89b3a37248SEddie Huang reg = <0x100>; 90b3a37248SEddie Huang enable-method = "psci"; 91ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 92b3a37248SEddie Huang }; 93b3a37248SEddie Huang 94b3a37248SEddie Huang cpu3: cpu@101 { 95b3a37248SEddie Huang device_type = "cpu"; 96b3a37248SEddie Huang compatible = "arm,cortex-a57"; 97b3a37248SEddie Huang reg = <0x101>; 98b3a37248SEddie Huang enable-method = "psci"; 99ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 100ad4df7a5SHoward Chen }; 101ad4df7a5SHoward Chen 102ad4df7a5SHoward Chen idle-states { 103a13f18f5SLorenzo Pieralisi entry-method = "psci"; 104ad4df7a5SHoward Chen 105ad4df7a5SHoward Chen CPU_SLEEP_0: cpu-sleep-0 { 106ad4df7a5SHoward Chen compatible = "arm,idle-state"; 107ad4df7a5SHoward Chen local-timer-stop; 108ad4df7a5SHoward Chen entry-latency-us = <639>; 109ad4df7a5SHoward Chen exit-latency-us = <680>; 110ad4df7a5SHoward Chen min-residency-us = <1088>; 111ad4df7a5SHoward Chen arm,psci-suspend-param = <0x0010000>; 112ad4df7a5SHoward Chen }; 113b3a37248SEddie Huang }; 114b3a37248SEddie Huang }; 115b3a37248SEddie Huang 116b3a37248SEddie Huang psci { 11705bdabe7SFan Chen compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 118b3a37248SEddie Huang method = "smc"; 119b3a37248SEddie Huang cpu_suspend = <0x84000001>; 120b3a37248SEddie Huang cpu_off = <0x84000002>; 121b3a37248SEddie Huang cpu_on = <0x84000003>; 122b3a37248SEddie Huang }; 123b3a37248SEddie Huang 124f2ce7014SSascha Hauer clk26m: oscillator@0 { 125f2ce7014SSascha Hauer compatible = "fixed-clock"; 126f2ce7014SSascha Hauer #clock-cells = <0>; 127f2ce7014SSascha Hauer clock-frequency = <26000000>; 128f2ce7014SSascha Hauer clock-output-names = "clk26m"; 129f2ce7014SSascha Hauer }; 130f2ce7014SSascha Hauer 131f2ce7014SSascha Hauer clk32k: oscillator@1 { 132f2ce7014SSascha Hauer compatible = "fixed-clock"; 133f2ce7014SSascha Hauer #clock-cells = <0>; 134f2ce7014SSascha Hauer clock-frequency = <32000>; 135f2ce7014SSascha Hauer clock-output-names = "clk32k"; 136f2ce7014SSascha Hauer }; 137f2ce7014SSascha Hauer 13867e56c56SJames Liao cpum_ck: oscillator@2 { 13967e56c56SJames Liao compatible = "fixed-clock"; 14067e56c56SJames Liao #clock-cells = <0>; 14167e56c56SJames Liao clock-frequency = <0>; 14267e56c56SJames Liao clock-output-names = "cpum_ck"; 14367e56c56SJames Liao }; 14467e56c56SJames Liao 145962f5143Sdawei.chien@mediatek.com thermal-zones { 146962f5143Sdawei.chien@mediatek.com cpu_thermal: cpu_thermal { 147962f5143Sdawei.chien@mediatek.com polling-delay-passive = <1000>; /* milliseconds */ 148962f5143Sdawei.chien@mediatek.com polling-delay = <1000>; /* milliseconds */ 149962f5143Sdawei.chien@mediatek.com 150962f5143Sdawei.chien@mediatek.com thermal-sensors = <&thermal>; 151962f5143Sdawei.chien@mediatek.com sustainable-power = <1500>; /* milliwatts */ 152962f5143Sdawei.chien@mediatek.com 153962f5143Sdawei.chien@mediatek.com trips { 154962f5143Sdawei.chien@mediatek.com threshold: trip-point@0 { 155962f5143Sdawei.chien@mediatek.com temperature = <68000>; 156962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 157962f5143Sdawei.chien@mediatek.com type = "passive"; 158962f5143Sdawei.chien@mediatek.com }; 159962f5143Sdawei.chien@mediatek.com 160962f5143Sdawei.chien@mediatek.com target: trip-point@1 { 161962f5143Sdawei.chien@mediatek.com temperature = <85000>; 162962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 163962f5143Sdawei.chien@mediatek.com type = "passive"; 164962f5143Sdawei.chien@mediatek.com }; 165962f5143Sdawei.chien@mediatek.com 166962f5143Sdawei.chien@mediatek.com cpu_crit: cpu_crit@0 { 167962f5143Sdawei.chien@mediatek.com temperature = <115000>; 168962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 169962f5143Sdawei.chien@mediatek.com type = "critical"; 170962f5143Sdawei.chien@mediatek.com }; 171962f5143Sdawei.chien@mediatek.com }; 172962f5143Sdawei.chien@mediatek.com 173962f5143Sdawei.chien@mediatek.com cooling-maps { 174962f5143Sdawei.chien@mediatek.com map@0 { 175962f5143Sdawei.chien@mediatek.com trip = <&target>; 176962f5143Sdawei.chien@mediatek.com cooling-device = <&cpu0 0 0>; 177962f5143Sdawei.chien@mediatek.com contribution = <1024>; 178962f5143Sdawei.chien@mediatek.com }; 179962f5143Sdawei.chien@mediatek.com map@1 { 180962f5143Sdawei.chien@mediatek.com trip = <&target>; 181962f5143Sdawei.chien@mediatek.com cooling-device = <&cpu2 0 0>; 182962f5143Sdawei.chien@mediatek.com contribution = <2048>; 183962f5143Sdawei.chien@mediatek.com }; 184962f5143Sdawei.chien@mediatek.com }; 185962f5143Sdawei.chien@mediatek.com }; 186962f5143Sdawei.chien@mediatek.com }; 187962f5143Sdawei.chien@mediatek.com 188404b2819SAndrew-CT Chen reserved-memory { 189404b2819SAndrew-CT Chen #address-cells = <2>; 190404b2819SAndrew-CT Chen #size-cells = <2>; 191404b2819SAndrew-CT Chen ranges; 192404b2819SAndrew-CT Chen vpu_dma_reserved: vpu_dma_mem_region { 193404b2819SAndrew-CT Chen compatible = "shared-dma-pool"; 194404b2819SAndrew-CT Chen reg = <0 0xb7000000 0 0x500000>; 195404b2819SAndrew-CT Chen alignment = <0x1000>; 196404b2819SAndrew-CT Chen no-map; 197404b2819SAndrew-CT Chen }; 198404b2819SAndrew-CT Chen }; 199404b2819SAndrew-CT Chen 200b3a37248SEddie Huang timer { 201b3a37248SEddie Huang compatible = "arm,armv8-timer"; 202b3a37248SEddie Huang interrupt-parent = <&gic>; 203b3a37248SEddie Huang interrupts = <GIC_PPI 13 204b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 205b3a37248SEddie Huang <GIC_PPI 14 206b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 207b3a37248SEddie Huang <GIC_PPI 11 208b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 209b3a37248SEddie Huang <GIC_PPI 10 210b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 211b3a37248SEddie Huang }; 212b3a37248SEddie Huang 213b3a37248SEddie Huang soc { 214b3a37248SEddie Huang #address-cells = <2>; 215b3a37248SEddie Huang #size-cells = <2>; 216b3a37248SEddie Huang compatible = "simple-bus"; 217b3a37248SEddie Huang ranges; 218b3a37248SEddie Huang 219f2ce7014SSascha Hauer topckgen: clock-controller@10000000 { 220f2ce7014SSascha Hauer compatible = "mediatek,mt8173-topckgen"; 221f2ce7014SSascha Hauer reg = <0 0x10000000 0 0x1000>; 222f2ce7014SSascha Hauer #clock-cells = <1>; 223f2ce7014SSascha Hauer }; 224f2ce7014SSascha Hauer 225f2ce7014SSascha Hauer infracfg: power-controller@10001000 { 226f2ce7014SSascha Hauer compatible = "mediatek,mt8173-infracfg", "syscon"; 227f2ce7014SSascha Hauer reg = <0 0x10001000 0 0x1000>; 228f2ce7014SSascha Hauer #clock-cells = <1>; 229f2ce7014SSascha Hauer #reset-cells = <1>; 230f2ce7014SSascha Hauer }; 231f2ce7014SSascha Hauer 232f2ce7014SSascha Hauer pericfg: power-controller@10003000 { 233f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pericfg", "syscon"; 234f2ce7014SSascha Hauer reg = <0 0x10003000 0 0x1000>; 235f2ce7014SSascha Hauer #clock-cells = <1>; 236f2ce7014SSascha Hauer #reset-cells = <1>; 237f2ce7014SSascha Hauer }; 238f2ce7014SSascha Hauer 239f2ce7014SSascha Hauer syscfg_pctl_a: syscfg_pctl_a@10005000 { 240f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 241f2ce7014SSascha Hauer reg = <0 0x10005000 0 0x1000>; 242f2ce7014SSascha Hauer }; 243f2ce7014SSascha Hauer 244f2ce7014SSascha Hauer pio: pinctrl@0x10005000 { 245359f9365SHongzhou Yang compatible = "mediatek,mt8173-pinctrl"; 2466769b93cSYingjoe Chen reg = <0 0x1000b000 0 0x1000>; 247359f9365SHongzhou Yang mediatek,pctl-regmap = <&syscfg_pctl_a>; 248359f9365SHongzhou Yang pins-are-numbered; 249359f9365SHongzhou Yang gpio-controller; 250359f9365SHongzhou Yang #gpio-cells = <2>; 251359f9365SHongzhou Yang interrupt-controller; 252359f9365SHongzhou Yang #interrupt-cells = <2>; 253359f9365SHongzhou Yang interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 254359f9365SHongzhou Yang <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 255359f9365SHongzhou Yang <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 256091cf598SEddie Huang 257a10b57f4SCK Hu hdmi_pin: xxx { 258a10b57f4SCK Hu 259a10b57f4SCK Hu /*hdmi htplg pin*/ 260a10b57f4SCK Hu pins1 { 261a10b57f4SCK Hu pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>; 262a10b57f4SCK Hu input-enable; 263a10b57f4SCK Hu bias-pull-down; 264a10b57f4SCK Hu }; 265a10b57f4SCK Hu }; 266a10b57f4SCK Hu 267091cf598SEddie Huang i2c0_pins_a: i2c0 { 268091cf598SEddie Huang pins1 { 269091cf598SEddie Huang pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 270091cf598SEddie Huang <MT8173_PIN_46_SCL0__FUNC_SCL0>; 271091cf598SEddie Huang bias-disable; 272091cf598SEddie Huang }; 273359f9365SHongzhou Yang }; 274359f9365SHongzhou Yang 275091cf598SEddie Huang i2c1_pins_a: i2c1 { 276091cf598SEddie Huang pins1 { 277091cf598SEddie Huang pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 278091cf598SEddie Huang <MT8173_PIN_126_SCL1__FUNC_SCL1>; 279091cf598SEddie Huang bias-disable; 280091cf598SEddie Huang }; 281091cf598SEddie Huang }; 282091cf598SEddie Huang 283091cf598SEddie Huang i2c2_pins_a: i2c2 { 284091cf598SEddie Huang pins1 { 285091cf598SEddie Huang pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 286091cf598SEddie Huang <MT8173_PIN_44_SCL2__FUNC_SCL2>; 287091cf598SEddie Huang bias-disable; 288091cf598SEddie Huang }; 289091cf598SEddie Huang }; 290091cf598SEddie Huang 291091cf598SEddie Huang i2c3_pins_a: i2c3 { 292091cf598SEddie Huang pins1 { 293091cf598SEddie Huang pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 294091cf598SEddie Huang <MT8173_PIN_107_SCL3__FUNC_SCL3>; 295091cf598SEddie Huang bias-disable; 296091cf598SEddie Huang }; 297091cf598SEddie Huang }; 298091cf598SEddie Huang 299091cf598SEddie Huang i2c4_pins_a: i2c4 { 300091cf598SEddie Huang pins1 { 301091cf598SEddie Huang pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 302091cf598SEddie Huang <MT8173_PIN_134_SCL4__FUNC_SCL4>; 303091cf598SEddie Huang bias-disable; 304091cf598SEddie Huang }; 305091cf598SEddie Huang }; 306091cf598SEddie Huang 307091cf598SEddie Huang i2c6_pins_a: i2c6 { 308091cf598SEddie Huang pins1 { 309091cf598SEddie Huang pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 310091cf598SEddie Huang <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 311091cf598SEddie Huang bias-disable; 312091cf598SEddie Huang }; 313091cf598SEddie Huang }; 3146769b93cSYingjoe Chen }; 3156769b93cSYingjoe Chen 316c010ff53SSascha Hauer scpsys: scpsys@10006000 { 317c010ff53SSascha Hauer compatible = "mediatek,mt8173-scpsys"; 318c010ff53SSascha Hauer #power-domain-cells = <1>; 319c010ff53SSascha Hauer reg = <0 0x10006000 0 0x1000>; 320c010ff53SSascha Hauer clocks = <&clk26m>, 321e34573c9SJames Liao <&topckgen CLK_TOP_MM_SEL>, 322e34573c9SJames Liao <&topckgen CLK_TOP_VENC_SEL>, 323e34573c9SJames Liao <&topckgen CLK_TOP_VENC_LT_SEL>; 324e34573c9SJames Liao clock-names = "mfg", "mm", "venc", "venc_lt"; 325c010ff53SSascha Hauer infracfg = <&infracfg>; 326c010ff53SSascha Hauer }; 327c010ff53SSascha Hauer 32813421b3eSEddie Huang watchdog: watchdog@10007000 { 32913421b3eSEddie Huang compatible = "mediatek,mt8173-wdt", 33013421b3eSEddie Huang "mediatek,mt6589-wdt"; 33113421b3eSEddie Huang reg = <0 0x10007000 0 0x100>; 33213421b3eSEddie Huang }; 33313421b3eSEddie Huang 334b2c76e27SDaniel Kurtz timer: timer@10008000 { 335b2c76e27SDaniel Kurtz compatible = "mediatek,mt8173-timer", 336b2c76e27SDaniel Kurtz "mediatek,mt6577-timer"; 337b2c76e27SDaniel Kurtz reg = <0 0x10008000 0 0x1000>; 338b2c76e27SDaniel Kurtz interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 339b2c76e27SDaniel Kurtz clocks = <&infracfg CLK_INFRA_CLK_13M>, 340b2c76e27SDaniel Kurtz <&topckgen CLK_TOP_RTC_SEL>; 341b2c76e27SDaniel Kurtz }; 342b2c76e27SDaniel Kurtz 3436cf15fc2SSascha Hauer pwrap: pwrap@1000d000 { 3446cf15fc2SSascha Hauer compatible = "mediatek,mt8173-pwrap"; 3456cf15fc2SSascha Hauer reg = <0 0x1000d000 0 0x1000>; 3466cf15fc2SSascha Hauer reg-names = "pwrap"; 3476cf15fc2SSascha Hauer interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 3486cf15fc2SSascha Hauer resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 3496cf15fc2SSascha Hauer reset-names = "pwrap"; 3506cf15fc2SSascha Hauer clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 3516cf15fc2SSascha Hauer clock-names = "spi", "wrap"; 3526cf15fc2SSascha Hauer }; 3536cf15fc2SSascha Hauer 354a10b57f4SCK Hu cec: cec@10013000 { 355a10b57f4SCK Hu compatible = "mediatek,mt8173-cec"; 356a10b57f4SCK Hu reg = <0 0x10013000 0 0xbc>; 357a10b57f4SCK Hu interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; 358a10b57f4SCK Hu clocks = <&infracfg CLK_INFRA_CEC>; 359a10b57f4SCK Hu status = "disabled"; 360a10b57f4SCK Hu }; 361a10b57f4SCK Hu 362404b2819SAndrew-CT Chen vpu: vpu@10020000 { 363404b2819SAndrew-CT Chen compatible = "mediatek,mt8173-vpu"; 364404b2819SAndrew-CT Chen reg = <0 0x10020000 0 0x30000>, 365404b2819SAndrew-CT Chen <0 0x10050000 0 0x100>; 366404b2819SAndrew-CT Chen reg-names = "tcm", "cfg_reg"; 367404b2819SAndrew-CT Chen interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 368404b2819SAndrew-CT Chen clocks = <&topckgen CLK_TOP_SCP_SEL>; 369404b2819SAndrew-CT Chen clock-names = "main"; 370404b2819SAndrew-CT Chen memory-region = <&vpu_dma_reserved>; 371404b2819SAndrew-CT Chen }; 372404b2819SAndrew-CT Chen 373b3a37248SEddie Huang sysirq: intpol-controller@10200620 { 374b3a37248SEddie Huang compatible = "mediatek,mt8173-sysirq", 375b3a37248SEddie Huang "mediatek,mt6577-sysirq"; 376b3a37248SEddie Huang interrupt-controller; 377b3a37248SEddie Huang #interrupt-cells = <3>; 378b3a37248SEddie Huang interrupt-parent = <&gic>; 379b3a37248SEddie Huang reg = <0 0x10200620 0 0x20>; 380b3a37248SEddie Huang }; 381b3a37248SEddie Huang 3825ff6b3a6SYong Wu iommu: iommu@10205000 { 3835ff6b3a6SYong Wu compatible = "mediatek,mt8173-m4u"; 3845ff6b3a6SYong Wu reg = <0 0x10205000 0 0x1000>; 3855ff6b3a6SYong Wu interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 3865ff6b3a6SYong Wu clocks = <&infracfg CLK_INFRA_M4U>; 3875ff6b3a6SYong Wu clock-names = "bclk"; 3885ff6b3a6SYong Wu mediatek,larbs = <&larb0 &larb1 &larb2 3895ff6b3a6SYong Wu &larb3 &larb4 &larb5>; 3905ff6b3a6SYong Wu #iommu-cells = <1>; 3915ff6b3a6SYong Wu }; 3925ff6b3a6SYong Wu 39393e9f5eeSandrew-ct.chen@mediatek.com efuse: efuse@10206000 { 39493e9f5eeSandrew-ct.chen@mediatek.com compatible = "mediatek,mt8173-efuse"; 39593e9f5eeSandrew-ct.chen@mediatek.com reg = <0 0x10206000 0 0x1000>; 39693e9f5eeSandrew-ct.chen@mediatek.com }; 39793e9f5eeSandrew-ct.chen@mediatek.com 398f2ce7014SSascha Hauer apmixedsys: clock-controller@10209000 { 399f2ce7014SSascha Hauer compatible = "mediatek,mt8173-apmixedsys"; 400f2ce7014SSascha Hauer reg = <0 0x10209000 0 0x1000>; 401f2ce7014SSascha Hauer #clock-cells = <1>; 402f2ce7014SSascha Hauer }; 403f2ce7014SSascha Hauer 404a10b57f4SCK Hu hdmi_phy: hdmi-phy@10209100 { 405a10b57f4SCK Hu compatible = "mediatek,mt8173-hdmi-phy"; 406a10b57f4SCK Hu reg = <0 0x10209100 0 0x24>; 407a10b57f4SCK Hu clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; 408a10b57f4SCK Hu clock-names = "pll_ref"; 409a10b57f4SCK Hu clock-output-names = "hdmitx_dig_cts"; 410a10b57f4SCK Hu mediatek,ibias = <0xa>; 411a10b57f4SCK Hu mediatek,ibias_up = <0x1c>; 412a10b57f4SCK Hu #clock-cells = <0>; 413a10b57f4SCK Hu #phy-cells = <0>; 414a10b57f4SCK Hu status = "disabled"; 415a10b57f4SCK Hu }; 416a10b57f4SCK Hu 41781ad4dbaSCK Hu mipi_tx0: mipi-dphy@10215000 { 41881ad4dbaSCK Hu compatible = "mediatek,mt8173-mipi-tx"; 41981ad4dbaSCK Hu reg = <0 0x10215000 0 0x1000>; 42081ad4dbaSCK Hu clocks = <&clk26m>; 42181ad4dbaSCK Hu clock-output-names = "mipi_tx0_pll"; 42281ad4dbaSCK Hu #clock-cells = <0>; 42381ad4dbaSCK Hu #phy-cells = <0>; 42481ad4dbaSCK Hu status = "disabled"; 42581ad4dbaSCK Hu }; 42681ad4dbaSCK Hu 42781ad4dbaSCK Hu mipi_tx1: mipi-dphy@10216000 { 42881ad4dbaSCK Hu compatible = "mediatek,mt8173-mipi-tx"; 42981ad4dbaSCK Hu reg = <0 0x10216000 0 0x1000>; 43081ad4dbaSCK Hu clocks = <&clk26m>; 43181ad4dbaSCK Hu clock-output-names = "mipi_tx1_pll"; 43281ad4dbaSCK Hu #clock-cells = <0>; 43381ad4dbaSCK Hu #phy-cells = <0>; 43481ad4dbaSCK Hu status = "disabled"; 43581ad4dbaSCK Hu }; 43681ad4dbaSCK Hu 437b3a37248SEddie Huang gic: interrupt-controller@10220000 { 438b3a37248SEddie Huang compatible = "arm,gic-400"; 439b3a37248SEddie Huang #interrupt-cells = <3>; 440b3a37248SEddie Huang interrupt-parent = <&gic>; 441b3a37248SEddie Huang interrupt-controller; 442b3a37248SEddie Huang reg = <0 0x10221000 0 0x1000>, 443b3a37248SEddie Huang <0 0x10222000 0 0x2000>, 444b3a37248SEddie Huang <0 0x10224000 0 0x2000>, 445b3a37248SEddie Huang <0 0x10226000 0 0x2000>; 446b3a37248SEddie Huang interrupts = <GIC_PPI 9 447b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 448b3a37248SEddie Huang }; 449b3a37248SEddie Huang 450748c7d4dSSascha Hauer auxadc: auxadc@11001000 { 451748c7d4dSSascha Hauer compatible = "mediatek,mt8173-auxadc"; 452748c7d4dSSascha Hauer reg = <0 0x11001000 0 0x1000>; 453748c7d4dSSascha Hauer }; 454748c7d4dSSascha Hauer 455b3a37248SEddie Huang uart0: serial@11002000 { 456b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 457b3a37248SEddie Huang "mediatek,mt6577-uart"; 458b3a37248SEddie Huang reg = <0 0x11002000 0 0x400>; 459b3a37248SEddie Huang interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 4600e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 4610e84faa1SSascha Hauer clock-names = "baud", "bus"; 462b3a37248SEddie Huang status = "disabled"; 463b3a37248SEddie Huang }; 464b3a37248SEddie Huang 465b3a37248SEddie Huang uart1: serial@11003000 { 466b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 467b3a37248SEddie Huang "mediatek,mt6577-uart"; 468b3a37248SEddie Huang reg = <0 0x11003000 0 0x400>; 469b3a37248SEddie Huang interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 4700e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 4710e84faa1SSascha Hauer clock-names = "baud", "bus"; 472b3a37248SEddie Huang status = "disabled"; 473b3a37248SEddie Huang }; 474b3a37248SEddie Huang 475b3a37248SEddie Huang uart2: serial@11004000 { 476b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 477b3a37248SEddie Huang "mediatek,mt6577-uart"; 478b3a37248SEddie Huang reg = <0 0x11004000 0 0x400>; 479b3a37248SEddie Huang interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 4800e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 4810e84faa1SSascha Hauer clock-names = "baud", "bus"; 482b3a37248SEddie Huang status = "disabled"; 483b3a37248SEddie Huang }; 484b3a37248SEddie Huang 485b3a37248SEddie Huang uart3: serial@11005000 { 486b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 487b3a37248SEddie Huang "mediatek,mt6577-uart"; 488b3a37248SEddie Huang reg = <0 0x11005000 0 0x400>; 489b3a37248SEddie Huang interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 4900e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 4910e84faa1SSascha Hauer clock-names = "baud", "bus"; 492b3a37248SEddie Huang status = "disabled"; 493b3a37248SEddie Huang }; 494091cf598SEddie Huang 495091cf598SEddie Huang i2c0: i2c@11007000 { 496091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 497091cf598SEddie Huang reg = <0 0x11007000 0 0x70>, 498091cf598SEddie Huang <0 0x11000100 0 0x80>; 499091cf598SEddie Huang interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 500091cf598SEddie Huang clock-div = <16>; 501091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C0>, 502091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 503091cf598SEddie Huang clock-names = "main", "dma"; 504091cf598SEddie Huang pinctrl-names = "default"; 505091cf598SEddie Huang pinctrl-0 = <&i2c0_pins_a>; 506091cf598SEddie Huang #address-cells = <1>; 507091cf598SEddie Huang #size-cells = <0>; 508091cf598SEddie Huang status = "disabled"; 509091cf598SEddie Huang }; 510091cf598SEddie Huang 511091cf598SEddie Huang i2c1: i2c@11008000 { 512091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 513091cf598SEddie Huang reg = <0 0x11008000 0 0x70>, 514091cf598SEddie Huang <0 0x11000180 0 0x80>; 515091cf598SEddie Huang interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 516091cf598SEddie Huang clock-div = <16>; 517091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C1>, 518091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 519091cf598SEddie Huang clock-names = "main", "dma"; 520091cf598SEddie Huang pinctrl-names = "default"; 521091cf598SEddie Huang pinctrl-0 = <&i2c1_pins_a>; 522091cf598SEddie Huang #address-cells = <1>; 523091cf598SEddie Huang #size-cells = <0>; 524091cf598SEddie Huang status = "disabled"; 525091cf598SEddie Huang }; 526091cf598SEddie Huang 527091cf598SEddie Huang i2c2: i2c@11009000 { 528091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 529091cf598SEddie Huang reg = <0 0x11009000 0 0x70>, 530091cf598SEddie Huang <0 0x11000200 0 0x80>; 531091cf598SEddie Huang interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 532091cf598SEddie Huang clock-div = <16>; 533091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C2>, 534091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 535091cf598SEddie Huang clock-names = "main", "dma"; 536091cf598SEddie Huang pinctrl-names = "default"; 537091cf598SEddie Huang pinctrl-0 = <&i2c2_pins_a>; 538091cf598SEddie Huang #address-cells = <1>; 539091cf598SEddie Huang #size-cells = <0>; 540091cf598SEddie Huang status = "disabled"; 541091cf598SEddie Huang }; 542091cf598SEddie Huang 543b0c936f5SLeilk Liu spi: spi@1100a000 { 544b0c936f5SLeilk Liu compatible = "mediatek,mt8173-spi"; 545b0c936f5SLeilk Liu #address-cells = <1>; 546b0c936f5SLeilk Liu #size-cells = <0>; 547b0c936f5SLeilk Liu reg = <0 0x1100a000 0 0x1000>; 548b0c936f5SLeilk Liu interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 549b0c936f5SLeilk Liu clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 550b0c936f5SLeilk Liu <&topckgen CLK_TOP_SPI_SEL>, 551b0c936f5SLeilk Liu <&pericfg CLK_PERI_SPI0>; 552b0c936f5SLeilk Liu clock-names = "parent-clk", "sel-clk", "spi-clk"; 553b0c936f5SLeilk Liu status = "disabled"; 554b0c936f5SLeilk Liu }; 555b0c936f5SLeilk Liu 556748c7d4dSSascha Hauer thermal: thermal@1100b000 { 557748c7d4dSSascha Hauer #thermal-sensor-cells = <0>; 558748c7d4dSSascha Hauer compatible = "mediatek,mt8173-thermal"; 559748c7d4dSSascha Hauer reg = <0 0x1100b000 0 0x1000>; 560748c7d4dSSascha Hauer interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 561748c7d4dSSascha Hauer clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 562748c7d4dSSascha Hauer clock-names = "therm", "auxadc"; 563748c7d4dSSascha Hauer resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 564748c7d4dSSascha Hauer mediatek,auxadc = <&auxadc>; 565748c7d4dSSascha Hauer mediatek,apmixedsys = <&apmixedsys>; 566748c7d4dSSascha Hauer }; 567748c7d4dSSascha Hauer 56886cb8a88SBayi Cheng nor_flash: spi@1100d000 { 56986cb8a88SBayi Cheng compatible = "mediatek,mt8173-nor"; 57086cb8a88SBayi Cheng reg = <0 0x1100d000 0 0xe0>; 57186cb8a88SBayi Cheng clocks = <&pericfg CLK_PERI_SPI>, 57286cb8a88SBayi Cheng <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 57386cb8a88SBayi Cheng clock-names = "spi", "sf"; 57486cb8a88SBayi Cheng #address-cells = <1>; 57586cb8a88SBayi Cheng #size-cells = <0>; 57686cb8a88SBayi Cheng status = "disabled"; 57786cb8a88SBayi Cheng }; 57886cb8a88SBayi Cheng 5791ee35c05SYingjoe Chen i2c3: i2c@11010000 { 580091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 581091cf598SEddie Huang reg = <0 0x11010000 0 0x70>, 582091cf598SEddie Huang <0 0x11000280 0 0x80>; 583091cf598SEddie Huang interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 584091cf598SEddie Huang clock-div = <16>; 585091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C3>, 586091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 587091cf598SEddie Huang clock-names = "main", "dma"; 588091cf598SEddie Huang pinctrl-names = "default"; 589091cf598SEddie Huang pinctrl-0 = <&i2c3_pins_a>; 590091cf598SEddie Huang #address-cells = <1>; 591091cf598SEddie Huang #size-cells = <0>; 592091cf598SEddie Huang status = "disabled"; 593091cf598SEddie Huang }; 594091cf598SEddie Huang 5951ee35c05SYingjoe Chen i2c4: i2c@11011000 { 596091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 597091cf598SEddie Huang reg = <0 0x11011000 0 0x70>, 598091cf598SEddie Huang <0 0x11000300 0 0x80>; 599091cf598SEddie Huang interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 600091cf598SEddie Huang clock-div = <16>; 601091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C4>, 602091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 603091cf598SEddie Huang clock-names = "main", "dma"; 604091cf598SEddie Huang pinctrl-names = "default"; 605091cf598SEddie Huang pinctrl-0 = <&i2c4_pins_a>; 606091cf598SEddie Huang #address-cells = <1>; 607091cf598SEddie Huang #size-cells = <0>; 608091cf598SEddie Huang status = "disabled"; 609091cf598SEddie Huang }; 610091cf598SEddie Huang 611a10b57f4SCK Hu hdmiddc0: i2c@11012000 { 612a10b57f4SCK Hu compatible = "mediatek,mt8173-hdmi-ddc"; 613a10b57f4SCK Hu interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 614a10b57f4SCK Hu reg = <0 0x11012000 0 0x1C>; 615a10b57f4SCK Hu clocks = <&pericfg CLK_PERI_I2C5>; 616a10b57f4SCK Hu clock-names = "ddc-i2c"; 617a10b57f4SCK Hu }; 618a10b57f4SCK Hu 6191ee35c05SYingjoe Chen i2c6: i2c@11013000 { 620091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 621091cf598SEddie Huang reg = <0 0x11013000 0 0x70>, 622091cf598SEddie Huang <0 0x11000080 0 0x80>; 623091cf598SEddie Huang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 624091cf598SEddie Huang clock-div = <16>; 625091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C6>, 626091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 627091cf598SEddie Huang clock-names = "main", "dma"; 628091cf598SEddie Huang pinctrl-names = "default"; 629091cf598SEddie Huang pinctrl-0 = <&i2c6_pins_a>; 630091cf598SEddie Huang #address-cells = <1>; 631091cf598SEddie Huang #size-cells = <0>; 632091cf598SEddie Huang status = "disabled"; 633091cf598SEddie Huang }; 634c02e0e86SKoro Chen 635c02e0e86SKoro Chen afe: audio-controller@11220000 { 636c02e0e86SKoro Chen compatible = "mediatek,mt8173-afe-pcm"; 637c02e0e86SKoro Chen reg = <0 0x11220000 0 0x1000>; 638c02e0e86SKoro Chen interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 639c02e0e86SKoro Chen power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; 640c02e0e86SKoro Chen clocks = <&infracfg CLK_INFRA_AUDIO>, 641c02e0e86SKoro Chen <&topckgen CLK_TOP_AUDIO_SEL>, 642c02e0e86SKoro Chen <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 643c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL1_DIV0>, 644c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL2_DIV0>, 645c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S0_M_SEL>, 646c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S1_M_SEL>, 647c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S2_M_SEL>, 648c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S3_M_SEL>, 649c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S3_B_SEL>; 650c02e0e86SKoro Chen clock-names = "infra_sys_audio_clk", 651c02e0e86SKoro Chen "top_pdn_audio", 652c02e0e86SKoro Chen "top_pdn_aud_intbus", 653c02e0e86SKoro Chen "bck0", 654c02e0e86SKoro Chen "bck1", 655c02e0e86SKoro Chen "i2s0_m", 656c02e0e86SKoro Chen "i2s1_m", 657c02e0e86SKoro Chen "i2s2_m", 658c02e0e86SKoro Chen "i2s3_m", 659c02e0e86SKoro Chen "i2s3_b"; 660c02e0e86SKoro Chen assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 661c02e0e86SKoro Chen <&topckgen CLK_TOP_AUD_2_SEL>; 662c02e0e86SKoro Chen assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 663c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL2>; 664c02e0e86SKoro Chen }; 6659719fa5aSEddie Huang 6669719fa5aSEddie Huang mmc0: mmc@11230000 { 6679719fa5aSEddie Huang compatible = "mediatek,mt8173-mmc", 6689719fa5aSEddie Huang "mediatek,mt8135-mmc"; 6699719fa5aSEddie Huang reg = <0 0x11230000 0 0x1000>; 6709719fa5aSEddie Huang interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 6719719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_0>, 6729719fa5aSEddie Huang <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 6739719fa5aSEddie Huang clock-names = "source", "hclk"; 6749719fa5aSEddie Huang status = "disabled"; 6759719fa5aSEddie Huang }; 6769719fa5aSEddie Huang 6779719fa5aSEddie Huang mmc1: mmc@11240000 { 6789719fa5aSEddie Huang compatible = "mediatek,mt8173-mmc", 6799719fa5aSEddie Huang "mediatek,mt8135-mmc"; 6809719fa5aSEddie Huang reg = <0 0x11240000 0 0x1000>; 6819719fa5aSEddie Huang interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 6829719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_1>, 6839719fa5aSEddie Huang <&topckgen CLK_TOP_AXI_SEL>; 6849719fa5aSEddie Huang clock-names = "source", "hclk"; 6859719fa5aSEddie Huang status = "disabled"; 6869719fa5aSEddie Huang }; 6879719fa5aSEddie Huang 6889719fa5aSEddie Huang mmc2: mmc@11250000 { 6899719fa5aSEddie Huang compatible = "mediatek,mt8173-mmc", 6909719fa5aSEddie Huang "mediatek,mt8135-mmc"; 6919719fa5aSEddie Huang reg = <0 0x11250000 0 0x1000>; 6929719fa5aSEddie Huang interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 6939719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_2>, 6949719fa5aSEddie Huang <&topckgen CLK_TOP_AXI_SEL>; 6959719fa5aSEddie Huang clock-names = "source", "hclk"; 6969719fa5aSEddie Huang status = "disabled"; 6979719fa5aSEddie Huang }; 6989719fa5aSEddie Huang 6999719fa5aSEddie Huang mmc3: mmc@11260000 { 7009719fa5aSEddie Huang compatible = "mediatek,mt8173-mmc", 7019719fa5aSEddie Huang "mediatek,mt8135-mmc"; 7029719fa5aSEddie Huang reg = <0 0x11260000 0 0x1000>; 7039719fa5aSEddie Huang interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 7049719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_3>, 7059719fa5aSEddie Huang <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 7069719fa5aSEddie Huang clock-names = "source", "hclk"; 7079719fa5aSEddie Huang status = "disabled"; 7089719fa5aSEddie Huang }; 70967e56c56SJames Liao 710bfcce47aSChunfeng Yun usb30: usb@11270000 { 711bfcce47aSChunfeng Yun compatible = "mediatek,mt8173-xhci"; 712bfcce47aSChunfeng Yun reg = <0 0x11270000 0 0x1000>, 713bfcce47aSChunfeng Yun <0 0x11280700 0 0x0100>; 714bfcce47aSChunfeng Yun interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 715bfcce47aSChunfeng Yun power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 716bfcce47aSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>, 717bfcce47aSChunfeng Yun <&pericfg CLK_PERI_USB0>, 718bfcce47aSChunfeng Yun <&pericfg CLK_PERI_USB1>; 719bfcce47aSChunfeng Yun clock-names = "sys_ck", 720bfcce47aSChunfeng Yun "wakeup_deb_p0", 721bfcce47aSChunfeng Yun "wakeup_deb_p1"; 722bfcce47aSChunfeng Yun phys = <&phy_port0 PHY_TYPE_USB3>, 723bfcce47aSChunfeng Yun <&phy_port1 PHY_TYPE_USB2>; 724bfcce47aSChunfeng Yun mediatek,syscon-wakeup = <&pericfg>; 725bfcce47aSChunfeng Yun status = "okay"; 726bfcce47aSChunfeng Yun }; 727bfcce47aSChunfeng Yun 728bfcce47aSChunfeng Yun u3phy: usb-phy@11290000 { 729bfcce47aSChunfeng Yun compatible = "mediatek,mt8173-u3phy"; 730bfcce47aSChunfeng Yun reg = <0 0x11290000 0 0x800>; 731bfcce47aSChunfeng Yun clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 732bfcce47aSChunfeng Yun clock-names = "u3phya_ref"; 733bfcce47aSChunfeng Yun #address-cells = <2>; 734bfcce47aSChunfeng Yun #size-cells = <2>; 735bfcce47aSChunfeng Yun ranges; 736bfcce47aSChunfeng Yun status = "okay"; 737bfcce47aSChunfeng Yun 738bfcce47aSChunfeng Yun phy_port0: port@11290800 { 739bfcce47aSChunfeng Yun reg = <0 0x11290800 0 0x800>; 740bfcce47aSChunfeng Yun #phy-cells = <1>; 741bfcce47aSChunfeng Yun status = "okay"; 742bfcce47aSChunfeng Yun }; 743bfcce47aSChunfeng Yun 744bfcce47aSChunfeng Yun phy_port1: port@11291000 { 745bfcce47aSChunfeng Yun reg = <0 0x11291000 0 0x800>; 746bfcce47aSChunfeng Yun #phy-cells = <1>; 747bfcce47aSChunfeng Yun status = "okay"; 748bfcce47aSChunfeng Yun }; 749bfcce47aSChunfeng Yun }; 750bfcce47aSChunfeng Yun 75167e56c56SJames Liao mmsys: clock-controller@14000000 { 75267e56c56SJames Liao compatible = "mediatek,mt8173-mmsys", "syscon"; 75367e56c56SJames Liao reg = <0 0x14000000 0 0x1000>; 75481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 75567e56c56SJames Liao #clock-cells = <1>; 75667e56c56SJames Liao }; 75767e56c56SJames Liao 75881ad4dbaSCK Hu ovl0: ovl@1400c000 { 75981ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-ovl"; 76081ad4dbaSCK Hu reg = <0 0x1400c000 0 0x1000>; 76181ad4dbaSCK Hu interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 76281ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 76381ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_OVL0>; 76481ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_OVL0>; 76581ad4dbaSCK Hu mediatek,larb = <&larb0>; 76681ad4dbaSCK Hu }; 76781ad4dbaSCK Hu 76881ad4dbaSCK Hu ovl1: ovl@1400d000 { 76981ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-ovl"; 77081ad4dbaSCK Hu reg = <0 0x1400d000 0 0x1000>; 77181ad4dbaSCK Hu interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; 77281ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 77381ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_OVL1>; 77481ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_OVL1>; 77581ad4dbaSCK Hu mediatek,larb = <&larb4>; 77681ad4dbaSCK Hu }; 77781ad4dbaSCK Hu 77881ad4dbaSCK Hu rdma0: rdma@1400e000 { 77981ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-rdma"; 78081ad4dbaSCK Hu reg = <0 0x1400e000 0 0x1000>; 78181ad4dbaSCK Hu interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 78281ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 78381ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_RDMA0>; 78481ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_RDMA0>; 78581ad4dbaSCK Hu mediatek,larb = <&larb0>; 78681ad4dbaSCK Hu }; 78781ad4dbaSCK Hu 78881ad4dbaSCK Hu rdma1: rdma@1400f000 { 78981ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-rdma"; 79081ad4dbaSCK Hu reg = <0 0x1400f000 0 0x1000>; 79181ad4dbaSCK Hu interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; 79281ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 79381ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_RDMA1>; 79481ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_RDMA1>; 79581ad4dbaSCK Hu mediatek,larb = <&larb4>; 79681ad4dbaSCK Hu }; 79781ad4dbaSCK Hu 79881ad4dbaSCK Hu rdma2: rdma@14010000 { 79981ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-rdma"; 80081ad4dbaSCK Hu reg = <0 0x14010000 0 0x1000>; 80181ad4dbaSCK Hu interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; 80281ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 80381ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_RDMA2>; 80481ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_RDMA2>; 80581ad4dbaSCK Hu mediatek,larb = <&larb4>; 80681ad4dbaSCK Hu }; 80781ad4dbaSCK Hu 80881ad4dbaSCK Hu wdma0: wdma@14011000 { 80981ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-wdma"; 81081ad4dbaSCK Hu reg = <0 0x14011000 0 0x1000>; 81181ad4dbaSCK Hu interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 81281ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 81381ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_WDMA0>; 81481ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_WDMA0>; 81581ad4dbaSCK Hu mediatek,larb = <&larb0>; 81681ad4dbaSCK Hu }; 81781ad4dbaSCK Hu 81881ad4dbaSCK Hu wdma1: wdma@14012000 { 81981ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-wdma"; 82081ad4dbaSCK Hu reg = <0 0x14012000 0 0x1000>; 82181ad4dbaSCK Hu interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; 82281ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 82381ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_WDMA1>; 82481ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_WDMA1>; 82581ad4dbaSCK Hu mediatek,larb = <&larb4>; 82681ad4dbaSCK Hu }; 82781ad4dbaSCK Hu 82881ad4dbaSCK Hu color0: color@14013000 { 82981ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-color"; 83081ad4dbaSCK Hu reg = <0 0x14013000 0 0x1000>; 83181ad4dbaSCK Hu interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; 83281ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 83381ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_COLOR0>; 83481ad4dbaSCK Hu }; 83581ad4dbaSCK Hu 83681ad4dbaSCK Hu color1: color@14014000 { 83781ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-color"; 83881ad4dbaSCK Hu reg = <0 0x14014000 0 0x1000>; 83981ad4dbaSCK Hu interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 84081ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 84181ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_COLOR1>; 84281ad4dbaSCK Hu }; 84381ad4dbaSCK Hu 84481ad4dbaSCK Hu aal@14015000 { 84581ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-aal"; 84681ad4dbaSCK Hu reg = <0 0x14015000 0 0x1000>; 84781ad4dbaSCK Hu interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 84881ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 84981ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_AAL>; 85081ad4dbaSCK Hu }; 85181ad4dbaSCK Hu 85281ad4dbaSCK Hu gamma@14016000 { 85381ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-gamma"; 85481ad4dbaSCK Hu reg = <0 0x14016000 0 0x1000>; 85581ad4dbaSCK Hu interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 85681ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 85781ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_GAMMA>; 85881ad4dbaSCK Hu }; 85981ad4dbaSCK Hu 86081ad4dbaSCK Hu merge@14017000 { 86181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-merge"; 86281ad4dbaSCK Hu reg = <0 0x14017000 0 0x1000>; 86381ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 86481ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_MERGE>; 86581ad4dbaSCK Hu }; 86681ad4dbaSCK Hu 86781ad4dbaSCK Hu split0: split@14018000 { 86881ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-split"; 86981ad4dbaSCK Hu reg = <0 0x14018000 0 0x1000>; 87081ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 87181ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_SPLIT0>; 87281ad4dbaSCK Hu }; 87381ad4dbaSCK Hu 87481ad4dbaSCK Hu split1: split@14019000 { 87581ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-split"; 87681ad4dbaSCK Hu reg = <0 0x14019000 0 0x1000>; 87781ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 87881ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_SPLIT1>; 87981ad4dbaSCK Hu }; 88081ad4dbaSCK Hu 88181ad4dbaSCK Hu ufoe@1401a000 { 88281ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-ufoe"; 88381ad4dbaSCK Hu reg = <0 0x1401a000 0 0x1000>; 88481ad4dbaSCK Hu interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 88581ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 88681ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_UFOE>; 88781ad4dbaSCK Hu }; 88881ad4dbaSCK Hu 88981ad4dbaSCK Hu dsi0: dsi@1401b000 { 89081ad4dbaSCK Hu compatible = "mediatek,mt8173-dsi"; 89181ad4dbaSCK Hu reg = <0 0x1401b000 0 0x1000>; 89281ad4dbaSCK Hu interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 89381ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 89481ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DSI0_ENGINE>, 89581ad4dbaSCK Hu <&mmsys CLK_MM_DSI0_DIGITAL>, 89681ad4dbaSCK Hu <&mipi_tx0>; 89781ad4dbaSCK Hu clock-names = "engine", "digital", "hs"; 89881ad4dbaSCK Hu phys = <&mipi_tx0>; 89981ad4dbaSCK Hu phy-names = "dphy"; 90081ad4dbaSCK Hu status = "disabled"; 90181ad4dbaSCK Hu }; 90281ad4dbaSCK Hu 90381ad4dbaSCK Hu dsi1: dsi@1401c000 { 90481ad4dbaSCK Hu compatible = "mediatek,mt8173-dsi"; 90581ad4dbaSCK Hu reg = <0 0x1401c000 0 0x1000>; 90681ad4dbaSCK Hu interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 90781ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 90881ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DSI1_ENGINE>, 90981ad4dbaSCK Hu <&mmsys CLK_MM_DSI1_DIGITAL>, 91081ad4dbaSCK Hu <&mipi_tx1>; 91181ad4dbaSCK Hu clock-names = "engine", "digital", "hs"; 91281ad4dbaSCK Hu phy = <&mipi_tx1>; 91381ad4dbaSCK Hu phy-names = "dphy"; 91481ad4dbaSCK Hu status = "disabled"; 91581ad4dbaSCK Hu }; 91681ad4dbaSCK Hu 91781ad4dbaSCK Hu dpi0: dpi@1401d000 { 91881ad4dbaSCK Hu compatible = "mediatek,mt8173-dpi"; 91981ad4dbaSCK Hu reg = <0 0x1401d000 0 0x1000>; 92081ad4dbaSCK Hu interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 92181ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 92281ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DPI_PIXEL>, 92381ad4dbaSCK Hu <&mmsys CLK_MM_DPI_ENGINE>, 92481ad4dbaSCK Hu <&apmixedsys CLK_APMIXED_TVDPLL>; 92581ad4dbaSCK Hu clock-names = "pixel", "engine", "pll"; 92681ad4dbaSCK Hu status = "disabled"; 927a10b57f4SCK Hu 928a10b57f4SCK Hu port { 929a10b57f4SCK Hu dpi0_out: endpoint { 930a10b57f4SCK Hu remote-endpoint = <&hdmi0_in>; 931a10b57f4SCK Hu }; 932a10b57f4SCK Hu }; 93381ad4dbaSCK Hu }; 93481ad4dbaSCK Hu 93561aee934SYH Huang pwm0: pwm@1401e000 { 93661aee934SYH Huang compatible = "mediatek,mt8173-disp-pwm", 93761aee934SYH Huang "mediatek,mt6595-disp-pwm"; 93861aee934SYH Huang reg = <0 0x1401e000 0 0x1000>; 93961aee934SYH Huang #pwm-cells = <2>; 94061aee934SYH Huang clocks = <&mmsys CLK_MM_DISP_PWM026M>, 94161aee934SYH Huang <&mmsys CLK_MM_DISP_PWM0MM>; 94261aee934SYH Huang clock-names = "main", "mm"; 94361aee934SYH Huang status = "disabled"; 94461aee934SYH Huang }; 94561aee934SYH Huang 94661aee934SYH Huang pwm1: pwm@1401f000 { 94761aee934SYH Huang compatible = "mediatek,mt8173-disp-pwm", 94861aee934SYH Huang "mediatek,mt6595-disp-pwm"; 94961aee934SYH Huang reg = <0 0x1401f000 0 0x1000>; 95061aee934SYH Huang #pwm-cells = <2>; 95161aee934SYH Huang clocks = <&mmsys CLK_MM_DISP_PWM126M>, 95261aee934SYH Huang <&mmsys CLK_MM_DISP_PWM1MM>; 95361aee934SYH Huang clock-names = "main", "mm"; 95461aee934SYH Huang status = "disabled"; 95561aee934SYH Huang }; 95661aee934SYH Huang 95781ad4dbaSCK Hu mutex: mutex@14020000 { 95881ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-mutex"; 95981ad4dbaSCK Hu reg = <0 0x14020000 0 0x1000>; 96081ad4dbaSCK Hu interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 96181ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 96281ad4dbaSCK Hu clocks = <&mmsys CLK_MM_MUTEX_32K>; 96381ad4dbaSCK Hu }; 96481ad4dbaSCK Hu 9655ff6b3a6SYong Wu larb0: larb@14021000 { 9665ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 9675ff6b3a6SYong Wu reg = <0 0x14021000 0 0x1000>; 9685ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 9695ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 9705ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_LARB0>, 9715ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_LARB0>; 9725ff6b3a6SYong Wu clock-names = "apb", "smi"; 9735ff6b3a6SYong Wu }; 9745ff6b3a6SYong Wu 9755ff6b3a6SYong Wu smi_common: smi@14022000 { 9765ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-common"; 9775ff6b3a6SYong Wu reg = <0 0x14022000 0 0x1000>; 9785ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 9795ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_COMMON>, 9805ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_COMMON>; 9815ff6b3a6SYong Wu clock-names = "apb", "smi"; 9825ff6b3a6SYong Wu }; 9835ff6b3a6SYong Wu 98481ad4dbaSCK Hu od@14023000 { 98581ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-od"; 98681ad4dbaSCK Hu reg = <0 0x14023000 0 0x1000>; 98781ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_OD>; 98881ad4dbaSCK Hu }; 98981ad4dbaSCK Hu 990a10b57f4SCK Hu hdmi0: hdmi@14025000 { 991a10b57f4SCK Hu compatible = "mediatek,mt8173-hdmi"; 992a10b57f4SCK Hu reg = <0 0x14025000 0 0x400>; 993a10b57f4SCK Hu interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>; 994a10b57f4SCK Hu clocks = <&mmsys CLK_MM_HDMI_PIXEL>, 995a10b57f4SCK Hu <&mmsys CLK_MM_HDMI_PLLCK>, 996a10b57f4SCK Hu <&mmsys CLK_MM_HDMI_AUDIO>, 997a10b57f4SCK Hu <&mmsys CLK_MM_HDMI_SPDIF>; 998a10b57f4SCK Hu clock-names = "pixel", "pll", "bclk", "spdif"; 999a10b57f4SCK Hu pinctrl-names = "default"; 1000a10b57f4SCK Hu pinctrl-0 = <&hdmi_pin>; 1001a10b57f4SCK Hu phys = <&hdmi_phy>; 1002a10b57f4SCK Hu phy-names = "hdmi"; 1003a10b57f4SCK Hu mediatek,syscon-hdmi = <&mmsys 0x900>; 1004a10b57f4SCK Hu assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; 1005a10b57f4SCK Hu assigned-clock-parents = <&hdmi_phy>; 1006a10b57f4SCK Hu status = "disabled"; 1007a10b57f4SCK Hu 1008a10b57f4SCK Hu ports { 1009a10b57f4SCK Hu #address-cells = <1>; 1010a10b57f4SCK Hu #size-cells = <0>; 1011a10b57f4SCK Hu 1012a10b57f4SCK Hu port@0 { 1013a10b57f4SCK Hu reg = <0>; 1014a10b57f4SCK Hu 1015a10b57f4SCK Hu hdmi0_in: endpoint { 1016a10b57f4SCK Hu remote-endpoint = <&dpi0_out>; 1017a10b57f4SCK Hu }; 1018a10b57f4SCK Hu }; 1019a10b57f4SCK Hu }; 1020a10b57f4SCK Hu }; 1021a10b57f4SCK Hu 10225ff6b3a6SYong Wu larb4: larb@14027000 { 10235ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 10245ff6b3a6SYong Wu reg = <0 0x14027000 0 0x1000>; 10255ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 10265ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 10275ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_LARB4>, 10285ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_LARB4>; 10295ff6b3a6SYong Wu clock-names = "apb", "smi"; 10305ff6b3a6SYong Wu }; 10315ff6b3a6SYong Wu 103267e56c56SJames Liao imgsys: clock-controller@15000000 { 103367e56c56SJames Liao compatible = "mediatek,mt8173-imgsys", "syscon"; 103467e56c56SJames Liao reg = <0 0x15000000 0 0x1000>; 103567e56c56SJames Liao #clock-cells = <1>; 103667e56c56SJames Liao }; 103767e56c56SJames Liao 10385ff6b3a6SYong Wu larb2: larb@15001000 { 10395ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 10405ff6b3a6SYong Wu reg = <0 0x15001000 0 0x1000>; 10415ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 10425ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>; 10435ff6b3a6SYong Wu clocks = <&imgsys CLK_IMG_LARB2_SMI>, 10445ff6b3a6SYong Wu <&imgsys CLK_IMG_LARB2_SMI>; 10455ff6b3a6SYong Wu clock-names = "apb", "smi"; 10465ff6b3a6SYong Wu }; 10475ff6b3a6SYong Wu 104867e56c56SJames Liao vdecsys: clock-controller@16000000 { 104967e56c56SJames Liao compatible = "mediatek,mt8173-vdecsys", "syscon"; 105067e56c56SJames Liao reg = <0 0x16000000 0 0x1000>; 105167e56c56SJames Liao #clock-cells = <1>; 105267e56c56SJames Liao }; 105367e56c56SJames Liao 10545ff6b3a6SYong Wu larb1: larb@16010000 { 10555ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 10565ff6b3a6SYong Wu reg = <0 0x16010000 0 0x1000>; 10575ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 10585ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 10595ff6b3a6SYong Wu clocks = <&vdecsys CLK_VDEC_CKEN>, 10605ff6b3a6SYong Wu <&vdecsys CLK_VDEC_LARB_CKEN>; 10615ff6b3a6SYong Wu clock-names = "apb", "smi"; 10625ff6b3a6SYong Wu }; 10635ff6b3a6SYong Wu 106467e56c56SJames Liao vencsys: clock-controller@18000000 { 106567e56c56SJames Liao compatible = "mediatek,mt8173-vencsys", "syscon"; 106667e56c56SJames Liao reg = <0 0x18000000 0 0x1000>; 106767e56c56SJames Liao #clock-cells = <1>; 106867e56c56SJames Liao }; 106967e56c56SJames Liao 10705ff6b3a6SYong Wu larb3: larb@18001000 { 10715ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 10725ff6b3a6SYong Wu reg = <0 0x18001000 0 0x1000>; 10735ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 10745ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 10755ff6b3a6SYong Wu clocks = <&vencsys CLK_VENC_CKE1>, 10765ff6b3a6SYong Wu <&vencsys CLK_VENC_CKE0>; 10775ff6b3a6SYong Wu clock-names = "apb", "smi"; 10785ff6b3a6SYong Wu }; 10795ff6b3a6SYong Wu 10808eb80252STiffany Lin vcodec_enc: vcodec@18002000 { 10818eb80252STiffany Lin compatible = "mediatek,mt8173-vcodec-enc"; 10828eb80252STiffany Lin reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */ 10838eb80252STiffany Lin <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ 10848eb80252STiffany Lin interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>, 10858eb80252STiffany Lin <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; 10868eb80252STiffany Lin mediatek,larb = <&larb3>, 10878eb80252STiffany Lin <&larb5>; 10888eb80252STiffany Lin iommus = <&iommu M4U_PORT_VENC_RCPU>, 10898eb80252STiffany Lin <&iommu M4U_PORT_VENC_REC>, 10908eb80252STiffany Lin <&iommu M4U_PORT_VENC_BSDMA>, 10918eb80252STiffany Lin <&iommu M4U_PORT_VENC_SV_COMV>, 10928eb80252STiffany Lin <&iommu M4U_PORT_VENC_RD_COMV>, 10938eb80252STiffany Lin <&iommu M4U_PORT_VENC_CUR_LUMA>, 10948eb80252STiffany Lin <&iommu M4U_PORT_VENC_CUR_CHROMA>, 10958eb80252STiffany Lin <&iommu M4U_PORT_VENC_REF_LUMA>, 10968eb80252STiffany Lin <&iommu M4U_PORT_VENC_REF_CHROMA>, 10978eb80252STiffany Lin <&iommu M4U_PORT_VENC_NBM_RDMA>, 10988eb80252STiffany Lin <&iommu M4U_PORT_VENC_NBM_WDMA>, 10998eb80252STiffany Lin <&iommu M4U_PORT_VENC_RCPU_SET2>, 11008eb80252STiffany Lin <&iommu M4U_PORT_VENC_REC_FRM_SET2>, 11018eb80252STiffany Lin <&iommu M4U_PORT_VENC_BSDMA_SET2>, 11028eb80252STiffany Lin <&iommu M4U_PORT_VENC_SV_COMA_SET2>, 11038eb80252STiffany Lin <&iommu M4U_PORT_VENC_RD_COMA_SET2>, 11048eb80252STiffany Lin <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, 11058eb80252STiffany Lin <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, 11068eb80252STiffany Lin <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, 11078eb80252STiffany Lin <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; 11088eb80252STiffany Lin mediatek,vpu = <&vpu>; 11098eb80252STiffany Lin clocks = <&topckgen CLK_TOP_VENCPLL_D2>, 11108eb80252STiffany Lin <&topckgen CLK_TOP_VENC_SEL>, 11118eb80252STiffany Lin <&topckgen CLK_TOP_UNIVPLL1_D2>, 11128eb80252STiffany Lin <&topckgen CLK_TOP_VENC_LT_SEL>; 11138eb80252STiffany Lin clock-names = "venc_sel_src", 11148eb80252STiffany Lin "venc_sel", 11158eb80252STiffany Lin "venc_lt_sel_src", 11168eb80252STiffany Lin "venc_lt_sel"; 11178eb80252STiffany Lin }; 11188eb80252STiffany Lin 111967e56c56SJames Liao vencltsys: clock-controller@19000000 { 112067e56c56SJames Liao compatible = "mediatek,mt8173-vencltsys", "syscon"; 112167e56c56SJames Liao reg = <0 0x19000000 0 0x1000>; 112267e56c56SJames Liao #clock-cells = <1>; 112367e56c56SJames Liao }; 11245ff6b3a6SYong Wu 11255ff6b3a6SYong Wu larb5: larb@19001000 { 11265ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 11275ff6b3a6SYong Wu reg = <0 0x19001000 0 0x1000>; 11285ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 11295ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; 11305ff6b3a6SYong Wu clocks = <&vencltsys CLK_VENCLT_CKE1>, 11315ff6b3a6SYong Wu <&vencltsys CLK_VENCLT_CKE0>; 11325ff6b3a6SYong Wu clock-names = "apb", "smi"; 11335ff6b3a6SYong Wu }; 1134b3a37248SEddie Huang }; 1135b3a37248SEddie Huang}; 1136b3a37248SEddie Huang 1137