1b3a37248SEddie Huang/* 2b3a37248SEddie Huang * Copyright (c) 2014 MediaTek Inc. 3b3a37248SEddie Huang * Author: Eddie Huang <eddie.huang@mediatek.com> 4b3a37248SEddie Huang * 5b3a37248SEddie Huang * This program is free software; you can redistribute it and/or modify 6b3a37248SEddie Huang * it under the terms of the GNU General Public License version 2 as 7b3a37248SEddie Huang * published by the Free Software Foundation. 8b3a37248SEddie Huang * 9b3a37248SEddie Huang * This program is distributed in the hope that it will be useful, 10b3a37248SEddie Huang * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11b3a37248SEddie Huang * GNU General Public License for more details. 12b3a37248SEddie Huang */ 13b3a37248SEddie Huang 14f2ce7014SSascha Hauer#include <dt-bindings/clock/mt8173-clk.h> 15b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/irq.h> 16b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/arm-gic.h> 175ff6b3a6SYong Wu#include <dt-bindings/memory/mt8173-larb-port.h> 18bfcce47aSChunfeng Yun#include <dt-bindings/phy/phy.h> 19c02e0e86SKoro Chen#include <dt-bindings/power/mt8173-power.h> 20967313e2SPhilipp Zabel#include <dt-bindings/reset/mt8173-resets.h> 21359f9365SHongzhou Yang#include "mt8173-pinfunc.h" 22b3a37248SEddie Huang 23b3a37248SEddie Huang/ { 24b3a37248SEddie Huang compatible = "mediatek,mt8173"; 25b3a37248SEddie Huang interrupt-parent = <&sysirq>; 26b3a37248SEddie Huang #address-cells = <2>; 27b3a37248SEddie Huang #size-cells = <2>; 28b3a37248SEddie Huang 2981ad4dbaSCK Hu aliases { 3081ad4dbaSCK Hu ovl0 = &ovl0; 3181ad4dbaSCK Hu ovl1 = &ovl1; 3281ad4dbaSCK Hu rdma0 = &rdma0; 3381ad4dbaSCK Hu rdma1 = &rdma1; 3481ad4dbaSCK Hu rdma2 = &rdma2; 3581ad4dbaSCK Hu wdma0 = &wdma0; 3681ad4dbaSCK Hu wdma1 = &wdma1; 3781ad4dbaSCK Hu color0 = &color0; 3881ad4dbaSCK Hu color1 = &color1; 3981ad4dbaSCK Hu split0 = &split0; 4081ad4dbaSCK Hu split1 = &split1; 4181ad4dbaSCK Hu dpi0 = &dpi0; 4281ad4dbaSCK Hu dsi0 = &dsi0; 4381ad4dbaSCK Hu dsi1 = &dsi1; 44989b292aSMinghsiu Tsai mdp_rdma0 = &mdp_rdma0; 45989b292aSMinghsiu Tsai mdp_rdma1 = &mdp_rdma1; 46989b292aSMinghsiu Tsai mdp_rsz0 = &mdp_rsz0; 47989b292aSMinghsiu Tsai mdp_rsz1 = &mdp_rsz1; 48989b292aSMinghsiu Tsai mdp_rsz2 = &mdp_rsz2; 49989b292aSMinghsiu Tsai mdp_wdma0 = &mdp_wdma0; 50989b292aSMinghsiu Tsai mdp_wrot0 = &mdp_wrot0; 51989b292aSMinghsiu Tsai mdp_wrot1 = &mdp_wrot1; 5281ad4dbaSCK Hu }; 5381ad4dbaSCK Hu 54da85a3afSAndrew-sh Cheng cluster0_opp: opp_table0 { 55da85a3afSAndrew-sh Cheng compatible = "operating-points-v2"; 56da85a3afSAndrew-sh Cheng opp-shared; 57da85a3afSAndrew-sh Cheng opp-507000000 { 58da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <507000000>; 59da85a3afSAndrew-sh Cheng opp-microvolt = <859000>; 60da85a3afSAndrew-sh Cheng }; 61da85a3afSAndrew-sh Cheng opp-702000000 { 62da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <702000000>; 63da85a3afSAndrew-sh Cheng opp-microvolt = <908000>; 64da85a3afSAndrew-sh Cheng }; 65da85a3afSAndrew-sh Cheng opp-1001000000 { 66da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1001000000>; 67da85a3afSAndrew-sh Cheng opp-microvolt = <983000>; 68da85a3afSAndrew-sh Cheng }; 69da85a3afSAndrew-sh Cheng opp-1105000000 { 70da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1105000000>; 71da85a3afSAndrew-sh Cheng opp-microvolt = <1009000>; 72da85a3afSAndrew-sh Cheng }; 73da85a3afSAndrew-sh Cheng opp-1209000000 { 74da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1209000000>; 75da85a3afSAndrew-sh Cheng opp-microvolt = <1034000>; 76da85a3afSAndrew-sh Cheng }; 77da85a3afSAndrew-sh Cheng opp-1300000000 { 78da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1300000000>; 79da85a3afSAndrew-sh Cheng opp-microvolt = <1057000>; 80da85a3afSAndrew-sh Cheng }; 81da85a3afSAndrew-sh Cheng opp-1508000000 { 82da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1508000000>; 83da85a3afSAndrew-sh Cheng opp-microvolt = <1109000>; 84da85a3afSAndrew-sh Cheng }; 85da85a3afSAndrew-sh Cheng opp-1703000000 { 86da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1703000000>; 87da85a3afSAndrew-sh Cheng opp-microvolt = <1125000>; 88da85a3afSAndrew-sh Cheng }; 89da85a3afSAndrew-sh Cheng }; 90da85a3afSAndrew-sh Cheng 91da85a3afSAndrew-sh Cheng cluster1_opp: opp_table1 { 92da85a3afSAndrew-sh Cheng compatible = "operating-points-v2"; 93da85a3afSAndrew-sh Cheng opp-shared; 94da85a3afSAndrew-sh Cheng opp-507000000 { 95da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <507000000>; 96da85a3afSAndrew-sh Cheng opp-microvolt = <828000>; 97da85a3afSAndrew-sh Cheng }; 98da85a3afSAndrew-sh Cheng opp-702000000 { 99da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <702000000>; 100da85a3afSAndrew-sh Cheng opp-microvolt = <867000>; 101da85a3afSAndrew-sh Cheng }; 102da85a3afSAndrew-sh Cheng opp-1001000000 { 103da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1001000000>; 104da85a3afSAndrew-sh Cheng opp-microvolt = <927000>; 105da85a3afSAndrew-sh Cheng }; 106da85a3afSAndrew-sh Cheng opp-1209000000 { 107da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1209000000>; 108da85a3afSAndrew-sh Cheng opp-microvolt = <968000>; 109da85a3afSAndrew-sh Cheng }; 110da85a3afSAndrew-sh Cheng opp-1404000000 { 111da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1404000000>; 112da85a3afSAndrew-sh Cheng opp-microvolt = <1007000>; 113da85a3afSAndrew-sh Cheng }; 114da85a3afSAndrew-sh Cheng opp-1612000000 { 115da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1612000000>; 116da85a3afSAndrew-sh Cheng opp-microvolt = <1049000>; 117da85a3afSAndrew-sh Cheng }; 118da85a3afSAndrew-sh Cheng opp-1807000000 { 119da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1807000000>; 120da85a3afSAndrew-sh Cheng opp-microvolt = <1089000>; 121da85a3afSAndrew-sh Cheng }; 122da85a3afSAndrew-sh Cheng opp-2106000000 { 123da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <2106000000>; 124da85a3afSAndrew-sh Cheng opp-microvolt = <1125000>; 125da85a3afSAndrew-sh Cheng }; 126da85a3afSAndrew-sh Cheng }; 127da85a3afSAndrew-sh Cheng 128b3a37248SEddie Huang cpus { 129b3a37248SEddie Huang #address-cells = <1>; 130b3a37248SEddie Huang #size-cells = <0>; 131b3a37248SEddie Huang 132b3a37248SEddie Huang cpu-map { 133b3a37248SEddie Huang cluster0 { 134b3a37248SEddie Huang core0 { 135b3a37248SEddie Huang cpu = <&cpu0>; 136b3a37248SEddie Huang }; 137b3a37248SEddie Huang core1 { 138b3a37248SEddie Huang cpu = <&cpu1>; 139b3a37248SEddie Huang }; 140b3a37248SEddie Huang }; 141b3a37248SEddie Huang 142b3a37248SEddie Huang cluster1 { 143b3a37248SEddie Huang core0 { 144b3a37248SEddie Huang cpu = <&cpu2>; 145b3a37248SEddie Huang }; 146b3a37248SEddie Huang core1 { 147b3a37248SEddie Huang cpu = <&cpu3>; 148b3a37248SEddie Huang }; 149b3a37248SEddie Huang }; 150b3a37248SEddie Huang }; 151b3a37248SEddie Huang 152b3a37248SEddie Huang cpu0: cpu@0 { 153b3a37248SEddie Huang device_type = "cpu"; 154b3a37248SEddie Huang compatible = "arm,cortex-a53"; 155b3a37248SEddie Huang reg = <0x000>; 156ad4df7a5SHoward Chen enable-method = "psci"; 157ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 158acbf76eeSArnd Bergmann #cooling-cells = <2>; 159da85a3afSAndrew-sh Cheng clocks = <&infracfg CLK_INFRA_CA53SEL>, 160da85a3afSAndrew-sh Cheng <&apmixedsys CLK_APMIXED_MAINPLL>; 161da85a3afSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 162da85a3afSAndrew-sh Cheng operating-points-v2 = <&cluster0_opp>; 163b3a37248SEddie Huang }; 164b3a37248SEddie Huang 165b3a37248SEddie Huang cpu1: cpu@1 { 166b3a37248SEddie Huang device_type = "cpu"; 167b3a37248SEddie Huang compatible = "arm,cortex-a53"; 168b3a37248SEddie Huang reg = <0x001>; 169b3a37248SEddie Huang enable-method = "psci"; 170ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 171a06e5c05SViresh Kumar #cooling-cells = <2>; 172da85a3afSAndrew-sh Cheng clocks = <&infracfg CLK_INFRA_CA53SEL>, 173da85a3afSAndrew-sh Cheng <&apmixedsys CLK_APMIXED_MAINPLL>; 174da85a3afSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 175da85a3afSAndrew-sh Cheng operating-points-v2 = <&cluster0_opp>; 176b3a37248SEddie Huang }; 177b3a37248SEddie Huang 178b3a37248SEddie Huang cpu2: cpu@100 { 179b3a37248SEddie Huang device_type = "cpu"; 180b3a37248SEddie Huang compatible = "arm,cortex-a57"; 181b3a37248SEddie Huang reg = <0x100>; 182b3a37248SEddie Huang enable-method = "psci"; 183ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 184acbf76eeSArnd Bergmann #cooling-cells = <2>; 185da85a3afSAndrew-sh Cheng clocks = <&infracfg CLK_INFRA_CA57SEL>, 186da85a3afSAndrew-sh Cheng <&apmixedsys CLK_APMIXED_MAINPLL>; 187da85a3afSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 188da85a3afSAndrew-sh Cheng operating-points-v2 = <&cluster1_opp>; 189b3a37248SEddie Huang }; 190b3a37248SEddie Huang 191b3a37248SEddie Huang cpu3: cpu@101 { 192b3a37248SEddie Huang device_type = "cpu"; 193b3a37248SEddie Huang compatible = "arm,cortex-a57"; 194b3a37248SEddie Huang reg = <0x101>; 195b3a37248SEddie Huang enable-method = "psci"; 196ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 197a06e5c05SViresh Kumar #cooling-cells = <2>; 198da85a3afSAndrew-sh Cheng clocks = <&infracfg CLK_INFRA_CA57SEL>, 199da85a3afSAndrew-sh Cheng <&apmixedsys CLK_APMIXED_MAINPLL>; 200da85a3afSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 201da85a3afSAndrew-sh Cheng operating-points-v2 = <&cluster1_opp>; 202ad4df7a5SHoward Chen }; 203ad4df7a5SHoward Chen 204ad4df7a5SHoward Chen idle-states { 205a13f18f5SLorenzo Pieralisi entry-method = "psci"; 206ad4df7a5SHoward Chen 207ad4df7a5SHoward Chen CPU_SLEEP_0: cpu-sleep-0 { 208ad4df7a5SHoward Chen compatible = "arm,idle-state"; 209ad4df7a5SHoward Chen local-timer-stop; 210ad4df7a5SHoward Chen entry-latency-us = <639>; 211ad4df7a5SHoward Chen exit-latency-us = <680>; 212ad4df7a5SHoward Chen min-residency-us = <1088>; 213ad4df7a5SHoward Chen arm,psci-suspend-param = <0x0010000>; 214ad4df7a5SHoward Chen }; 215b3a37248SEddie Huang }; 216b3a37248SEddie Huang }; 217b3a37248SEddie Huang 218b3a37248SEddie Huang psci { 21905bdabe7SFan Chen compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 220b3a37248SEddie Huang method = "smc"; 221b3a37248SEddie Huang cpu_suspend = <0x84000001>; 222b3a37248SEddie Huang cpu_off = <0x84000002>; 223b3a37248SEddie Huang cpu_on = <0x84000003>; 224b3a37248SEddie Huang }; 225b3a37248SEddie Huang 226f2ce7014SSascha Hauer clk26m: oscillator@0 { 227f2ce7014SSascha Hauer compatible = "fixed-clock"; 228f2ce7014SSascha Hauer #clock-cells = <0>; 229f2ce7014SSascha Hauer clock-frequency = <26000000>; 230f2ce7014SSascha Hauer clock-output-names = "clk26m"; 231f2ce7014SSascha Hauer }; 232f2ce7014SSascha Hauer 233f2ce7014SSascha Hauer clk32k: oscillator@1 { 234f2ce7014SSascha Hauer compatible = "fixed-clock"; 235f2ce7014SSascha Hauer #clock-cells = <0>; 236f2ce7014SSascha Hauer clock-frequency = <32000>; 237f2ce7014SSascha Hauer clock-output-names = "clk32k"; 238f2ce7014SSascha Hauer }; 239f2ce7014SSascha Hauer 24067e56c56SJames Liao cpum_ck: oscillator@2 { 24167e56c56SJames Liao compatible = "fixed-clock"; 24267e56c56SJames Liao #clock-cells = <0>; 24367e56c56SJames Liao clock-frequency = <0>; 24467e56c56SJames Liao clock-output-names = "cpum_ck"; 24567e56c56SJames Liao }; 24667e56c56SJames Liao 247962f5143Sdawei.chien@mediatek.com thermal-zones { 248962f5143Sdawei.chien@mediatek.com cpu_thermal: cpu_thermal { 249962f5143Sdawei.chien@mediatek.com polling-delay-passive = <1000>; /* milliseconds */ 250962f5143Sdawei.chien@mediatek.com polling-delay = <1000>; /* milliseconds */ 251962f5143Sdawei.chien@mediatek.com 252962f5143Sdawei.chien@mediatek.com thermal-sensors = <&thermal>; 253962f5143Sdawei.chien@mediatek.com sustainable-power = <1500>; /* milliwatts */ 254962f5143Sdawei.chien@mediatek.com 255962f5143Sdawei.chien@mediatek.com trips { 256962f5143Sdawei.chien@mediatek.com threshold: trip-point@0 { 257962f5143Sdawei.chien@mediatek.com temperature = <68000>; 258962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 259962f5143Sdawei.chien@mediatek.com type = "passive"; 260962f5143Sdawei.chien@mediatek.com }; 261962f5143Sdawei.chien@mediatek.com 262962f5143Sdawei.chien@mediatek.com target: trip-point@1 { 263962f5143Sdawei.chien@mediatek.com temperature = <85000>; 264962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 265962f5143Sdawei.chien@mediatek.com type = "passive"; 266962f5143Sdawei.chien@mediatek.com }; 267962f5143Sdawei.chien@mediatek.com 268962f5143Sdawei.chien@mediatek.com cpu_crit: cpu_crit@0 { 269962f5143Sdawei.chien@mediatek.com temperature = <115000>; 270962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 271962f5143Sdawei.chien@mediatek.com type = "critical"; 272962f5143Sdawei.chien@mediatek.com }; 273962f5143Sdawei.chien@mediatek.com }; 274962f5143Sdawei.chien@mediatek.com 275962f5143Sdawei.chien@mediatek.com cooling-maps { 276962f5143Sdawei.chien@mediatek.com map@0 { 277962f5143Sdawei.chien@mediatek.com trip = <&target>; 278962f5143Sdawei.chien@mediatek.com cooling-device = <&cpu0 0 0>; 2797fcef92dSDaniel Kurtz contribution = <3072>; 280962f5143Sdawei.chien@mediatek.com }; 281962f5143Sdawei.chien@mediatek.com map@1 { 282962f5143Sdawei.chien@mediatek.com trip = <&target>; 283962f5143Sdawei.chien@mediatek.com cooling-device = <&cpu2 0 0>; 2847fcef92dSDaniel Kurtz contribution = <1024>; 285962f5143Sdawei.chien@mediatek.com }; 286962f5143Sdawei.chien@mediatek.com }; 287962f5143Sdawei.chien@mediatek.com }; 288962f5143Sdawei.chien@mediatek.com }; 289962f5143Sdawei.chien@mediatek.com 290404b2819SAndrew-CT Chen reserved-memory { 291404b2819SAndrew-CT Chen #address-cells = <2>; 292404b2819SAndrew-CT Chen #size-cells = <2>; 293404b2819SAndrew-CT Chen ranges; 294404b2819SAndrew-CT Chen vpu_dma_reserved: vpu_dma_mem_region { 295404b2819SAndrew-CT Chen compatible = "shared-dma-pool"; 296404b2819SAndrew-CT Chen reg = <0 0xb7000000 0 0x500000>; 297404b2819SAndrew-CT Chen alignment = <0x1000>; 298404b2819SAndrew-CT Chen no-map; 299404b2819SAndrew-CT Chen }; 300404b2819SAndrew-CT Chen }; 301404b2819SAndrew-CT Chen 302b3a37248SEddie Huang timer { 303b3a37248SEddie Huang compatible = "arm,armv8-timer"; 304b3a37248SEddie Huang interrupt-parent = <&gic>; 305b3a37248SEddie Huang interrupts = <GIC_PPI 13 306b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 307b3a37248SEddie Huang <GIC_PPI 14 308b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 309b3a37248SEddie Huang <GIC_PPI 11 310b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 311b3a37248SEddie Huang <GIC_PPI 10 312b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 313b3a37248SEddie Huang }; 314b3a37248SEddie Huang 315b3a37248SEddie Huang soc { 316b3a37248SEddie Huang #address-cells = <2>; 317b3a37248SEddie Huang #size-cells = <2>; 318b3a37248SEddie Huang compatible = "simple-bus"; 319b3a37248SEddie Huang ranges; 320b3a37248SEddie Huang 321f2ce7014SSascha Hauer topckgen: clock-controller@10000000 { 322f2ce7014SSascha Hauer compatible = "mediatek,mt8173-topckgen"; 323f2ce7014SSascha Hauer reg = <0 0x10000000 0 0x1000>; 324f2ce7014SSascha Hauer #clock-cells = <1>; 325f2ce7014SSascha Hauer }; 326f2ce7014SSascha Hauer 327f2ce7014SSascha Hauer infracfg: power-controller@10001000 { 328f2ce7014SSascha Hauer compatible = "mediatek,mt8173-infracfg", "syscon"; 329f2ce7014SSascha Hauer reg = <0 0x10001000 0 0x1000>; 330f2ce7014SSascha Hauer #clock-cells = <1>; 331f2ce7014SSascha Hauer #reset-cells = <1>; 332f2ce7014SSascha Hauer }; 333f2ce7014SSascha Hauer 334f2ce7014SSascha Hauer pericfg: power-controller@10003000 { 335f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pericfg", "syscon"; 336f2ce7014SSascha Hauer reg = <0 0x10003000 0 0x1000>; 337f2ce7014SSascha Hauer #clock-cells = <1>; 338f2ce7014SSascha Hauer #reset-cells = <1>; 339f2ce7014SSascha Hauer }; 340f2ce7014SSascha Hauer 341f2ce7014SSascha Hauer syscfg_pctl_a: syscfg_pctl_a@10005000 { 342f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 343f2ce7014SSascha Hauer reg = <0 0x10005000 0 0x1000>; 344f2ce7014SSascha Hauer }; 345f2ce7014SSascha Hauer 3469977a8c3SMathieu Malaterre pio: pinctrl@10005000 { 347359f9365SHongzhou Yang compatible = "mediatek,mt8173-pinctrl"; 3486769b93cSYingjoe Chen reg = <0 0x1000b000 0 0x1000>; 349359f9365SHongzhou Yang mediatek,pctl-regmap = <&syscfg_pctl_a>; 350359f9365SHongzhou Yang pins-are-numbered; 351359f9365SHongzhou Yang gpio-controller; 352359f9365SHongzhou Yang #gpio-cells = <2>; 353359f9365SHongzhou Yang interrupt-controller; 354359f9365SHongzhou Yang #interrupt-cells = <2>; 355359f9365SHongzhou Yang interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 356359f9365SHongzhou Yang <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 357359f9365SHongzhou Yang <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 358091cf598SEddie Huang 359a10b57f4SCK Hu hdmi_pin: xxx { 360a10b57f4SCK Hu 361a10b57f4SCK Hu /*hdmi htplg pin*/ 362a10b57f4SCK Hu pins1 { 363a10b57f4SCK Hu pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>; 364a10b57f4SCK Hu input-enable; 365a10b57f4SCK Hu bias-pull-down; 366a10b57f4SCK Hu }; 367a10b57f4SCK Hu }; 368a10b57f4SCK Hu 369091cf598SEddie Huang i2c0_pins_a: i2c0 { 370091cf598SEddie Huang pins1 { 371091cf598SEddie Huang pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 372091cf598SEddie Huang <MT8173_PIN_46_SCL0__FUNC_SCL0>; 373091cf598SEddie Huang bias-disable; 374091cf598SEddie Huang }; 375359f9365SHongzhou Yang }; 376359f9365SHongzhou Yang 377091cf598SEddie Huang i2c1_pins_a: i2c1 { 378091cf598SEddie Huang pins1 { 379091cf598SEddie Huang pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 380091cf598SEddie Huang <MT8173_PIN_126_SCL1__FUNC_SCL1>; 381091cf598SEddie Huang bias-disable; 382091cf598SEddie Huang }; 383091cf598SEddie Huang }; 384091cf598SEddie Huang 385091cf598SEddie Huang i2c2_pins_a: i2c2 { 386091cf598SEddie Huang pins1 { 387091cf598SEddie Huang pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 388091cf598SEddie Huang <MT8173_PIN_44_SCL2__FUNC_SCL2>; 389091cf598SEddie Huang bias-disable; 390091cf598SEddie Huang }; 391091cf598SEddie Huang }; 392091cf598SEddie Huang 393091cf598SEddie Huang i2c3_pins_a: i2c3 { 394091cf598SEddie Huang pins1 { 395091cf598SEddie Huang pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 396091cf598SEddie Huang <MT8173_PIN_107_SCL3__FUNC_SCL3>; 397091cf598SEddie Huang bias-disable; 398091cf598SEddie Huang }; 399091cf598SEddie Huang }; 400091cf598SEddie Huang 401091cf598SEddie Huang i2c4_pins_a: i2c4 { 402091cf598SEddie Huang pins1 { 403091cf598SEddie Huang pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 404091cf598SEddie Huang <MT8173_PIN_134_SCL4__FUNC_SCL4>; 405091cf598SEddie Huang bias-disable; 406091cf598SEddie Huang }; 407091cf598SEddie Huang }; 408091cf598SEddie Huang 409091cf598SEddie Huang i2c6_pins_a: i2c6 { 410091cf598SEddie Huang pins1 { 411091cf598SEddie Huang pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 412091cf598SEddie Huang <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 413091cf598SEddie Huang bias-disable; 414091cf598SEddie Huang }; 415091cf598SEddie Huang }; 4166769b93cSYingjoe Chen }; 4176769b93cSYingjoe Chen 418c010ff53SSascha Hauer scpsys: scpsys@10006000 { 419c010ff53SSascha Hauer compatible = "mediatek,mt8173-scpsys"; 420c010ff53SSascha Hauer #power-domain-cells = <1>; 421c010ff53SSascha Hauer reg = <0 0x10006000 0 0x1000>; 422c010ff53SSascha Hauer clocks = <&clk26m>, 423e34573c9SJames Liao <&topckgen CLK_TOP_MM_SEL>, 424e34573c9SJames Liao <&topckgen CLK_TOP_VENC_SEL>, 425e34573c9SJames Liao <&topckgen CLK_TOP_VENC_LT_SEL>; 426e34573c9SJames Liao clock-names = "mfg", "mm", "venc", "venc_lt"; 427c010ff53SSascha Hauer infracfg = <&infracfg>; 428c010ff53SSascha Hauer }; 429c010ff53SSascha Hauer 43013421b3eSEddie Huang watchdog: watchdog@10007000 { 43113421b3eSEddie Huang compatible = "mediatek,mt8173-wdt", 43213421b3eSEddie Huang "mediatek,mt6589-wdt"; 43313421b3eSEddie Huang reg = <0 0x10007000 0 0x100>; 43413421b3eSEddie Huang }; 43513421b3eSEddie Huang 436b2c76e27SDaniel Kurtz timer: timer@10008000 { 437b2c76e27SDaniel Kurtz compatible = "mediatek,mt8173-timer", 438b2c76e27SDaniel Kurtz "mediatek,mt6577-timer"; 439b2c76e27SDaniel Kurtz reg = <0 0x10008000 0 0x1000>; 440b2c76e27SDaniel Kurtz interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 441b2c76e27SDaniel Kurtz clocks = <&infracfg CLK_INFRA_CLK_13M>, 442b2c76e27SDaniel Kurtz <&topckgen CLK_TOP_RTC_SEL>; 443b2c76e27SDaniel Kurtz }; 444b2c76e27SDaniel Kurtz 4456cf15fc2SSascha Hauer pwrap: pwrap@1000d000 { 4466cf15fc2SSascha Hauer compatible = "mediatek,mt8173-pwrap"; 4476cf15fc2SSascha Hauer reg = <0 0x1000d000 0 0x1000>; 4486cf15fc2SSascha Hauer reg-names = "pwrap"; 4496cf15fc2SSascha Hauer interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 4506cf15fc2SSascha Hauer resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 4516cf15fc2SSascha Hauer reset-names = "pwrap"; 4526cf15fc2SSascha Hauer clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 4536cf15fc2SSascha Hauer clock-names = "spi", "wrap"; 4546cf15fc2SSascha Hauer }; 4556cf15fc2SSascha Hauer 456a10b57f4SCK Hu cec: cec@10013000 { 457a10b57f4SCK Hu compatible = "mediatek,mt8173-cec"; 458a10b57f4SCK Hu reg = <0 0x10013000 0 0xbc>; 459a10b57f4SCK Hu interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; 460a10b57f4SCK Hu clocks = <&infracfg CLK_INFRA_CEC>; 461a10b57f4SCK Hu status = "disabled"; 462a10b57f4SCK Hu }; 463a10b57f4SCK Hu 464404b2819SAndrew-CT Chen vpu: vpu@10020000 { 465404b2819SAndrew-CT Chen compatible = "mediatek,mt8173-vpu"; 466404b2819SAndrew-CT Chen reg = <0 0x10020000 0 0x30000>, 467404b2819SAndrew-CT Chen <0 0x10050000 0 0x100>; 468404b2819SAndrew-CT Chen reg-names = "tcm", "cfg_reg"; 469404b2819SAndrew-CT Chen interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 470404b2819SAndrew-CT Chen clocks = <&topckgen CLK_TOP_SCP_SEL>; 471404b2819SAndrew-CT Chen clock-names = "main"; 472404b2819SAndrew-CT Chen memory-region = <&vpu_dma_reserved>; 473404b2819SAndrew-CT Chen }; 474404b2819SAndrew-CT Chen 475b3a37248SEddie Huang sysirq: intpol-controller@10200620 { 476b3a37248SEddie Huang compatible = "mediatek,mt8173-sysirq", 477b3a37248SEddie Huang "mediatek,mt6577-sysirq"; 478b3a37248SEddie Huang interrupt-controller; 479b3a37248SEddie Huang #interrupt-cells = <3>; 480b3a37248SEddie Huang interrupt-parent = <&gic>; 481b3a37248SEddie Huang reg = <0 0x10200620 0 0x20>; 482b3a37248SEddie Huang }; 483b3a37248SEddie Huang 4845ff6b3a6SYong Wu iommu: iommu@10205000 { 4855ff6b3a6SYong Wu compatible = "mediatek,mt8173-m4u"; 4865ff6b3a6SYong Wu reg = <0 0x10205000 0 0x1000>; 4875ff6b3a6SYong Wu interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 4885ff6b3a6SYong Wu clocks = <&infracfg CLK_INFRA_M4U>; 4895ff6b3a6SYong Wu clock-names = "bclk"; 4905ff6b3a6SYong Wu mediatek,larbs = <&larb0 &larb1 &larb2 4915ff6b3a6SYong Wu &larb3 &larb4 &larb5>; 4925ff6b3a6SYong Wu #iommu-cells = <1>; 4935ff6b3a6SYong Wu }; 4945ff6b3a6SYong Wu 49593e9f5eeSandrew-ct.chen@mediatek.com efuse: efuse@10206000 { 49693e9f5eeSandrew-ct.chen@mediatek.com compatible = "mediatek,mt8173-efuse"; 49793e9f5eeSandrew-ct.chen@mediatek.com reg = <0 0x10206000 0 0x1000>; 4986de18454Sdawei.chien@mediatek.com #address-cells = <1>; 4996de18454Sdawei.chien@mediatek.com #size-cells = <1>; 5006de18454Sdawei.chien@mediatek.com thermal_calibration: calib@528 { 5016de18454Sdawei.chien@mediatek.com reg = <0x528 0xc>; 5026de18454Sdawei.chien@mediatek.com }; 50393e9f5eeSandrew-ct.chen@mediatek.com }; 50493e9f5eeSandrew-ct.chen@mediatek.com 505f2ce7014SSascha Hauer apmixedsys: clock-controller@10209000 { 506f2ce7014SSascha Hauer compatible = "mediatek,mt8173-apmixedsys"; 507f2ce7014SSascha Hauer reg = <0 0x10209000 0 0x1000>; 508f2ce7014SSascha Hauer #clock-cells = <1>; 509f2ce7014SSascha Hauer }; 510f2ce7014SSascha Hauer 511a10b57f4SCK Hu hdmi_phy: hdmi-phy@10209100 { 512a10b57f4SCK Hu compatible = "mediatek,mt8173-hdmi-phy"; 513a10b57f4SCK Hu reg = <0 0x10209100 0 0x24>; 514a10b57f4SCK Hu clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; 515a10b57f4SCK Hu clock-names = "pll_ref"; 516a10b57f4SCK Hu clock-output-names = "hdmitx_dig_cts"; 517a10b57f4SCK Hu mediatek,ibias = <0xa>; 518a10b57f4SCK Hu mediatek,ibias_up = <0x1c>; 519a10b57f4SCK Hu #clock-cells = <0>; 520a10b57f4SCK Hu #phy-cells = <0>; 521a10b57f4SCK Hu status = "disabled"; 522a10b57f4SCK Hu }; 523a10b57f4SCK Hu 52481ad4dbaSCK Hu mipi_tx0: mipi-dphy@10215000 { 52581ad4dbaSCK Hu compatible = "mediatek,mt8173-mipi-tx"; 52681ad4dbaSCK Hu reg = <0 0x10215000 0 0x1000>; 52781ad4dbaSCK Hu clocks = <&clk26m>; 52881ad4dbaSCK Hu clock-output-names = "mipi_tx0_pll"; 52981ad4dbaSCK Hu #clock-cells = <0>; 53081ad4dbaSCK Hu #phy-cells = <0>; 53181ad4dbaSCK Hu status = "disabled"; 53281ad4dbaSCK Hu }; 53381ad4dbaSCK Hu 53481ad4dbaSCK Hu mipi_tx1: mipi-dphy@10216000 { 53581ad4dbaSCK Hu compatible = "mediatek,mt8173-mipi-tx"; 53681ad4dbaSCK Hu reg = <0 0x10216000 0 0x1000>; 53781ad4dbaSCK Hu clocks = <&clk26m>; 53881ad4dbaSCK Hu clock-output-names = "mipi_tx1_pll"; 53981ad4dbaSCK Hu #clock-cells = <0>; 54081ad4dbaSCK Hu #phy-cells = <0>; 54181ad4dbaSCK Hu status = "disabled"; 54281ad4dbaSCK Hu }; 54381ad4dbaSCK Hu 544b3a37248SEddie Huang gic: interrupt-controller@10220000 { 545b3a37248SEddie Huang compatible = "arm,gic-400"; 546b3a37248SEddie Huang #interrupt-cells = <3>; 547b3a37248SEddie Huang interrupt-parent = <&gic>; 548b3a37248SEddie Huang interrupt-controller; 549b3a37248SEddie Huang reg = <0 0x10221000 0 0x1000>, 550b3a37248SEddie Huang <0 0x10222000 0 0x2000>, 551b3a37248SEddie Huang <0 0x10224000 0 0x2000>, 552b3a37248SEddie Huang <0 0x10226000 0 0x2000>; 553b3a37248SEddie Huang interrupts = <GIC_PPI 9 554b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 555b3a37248SEddie Huang }; 556b3a37248SEddie Huang 557748c7d4dSSascha Hauer auxadc: auxadc@11001000 { 558748c7d4dSSascha Hauer compatible = "mediatek,mt8173-auxadc"; 559748c7d4dSSascha Hauer reg = <0 0x11001000 0 0x1000>; 560a3207d64SMatthias Brugger clocks = <&pericfg CLK_PERI_AUXADC>; 561a3207d64SMatthias Brugger clock-names = "main"; 562a3207d64SMatthias Brugger #io-channel-cells = <1>; 563748c7d4dSSascha Hauer }; 564748c7d4dSSascha Hauer 565b3a37248SEddie Huang uart0: serial@11002000 { 566b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 567b3a37248SEddie Huang "mediatek,mt6577-uart"; 568b3a37248SEddie Huang reg = <0 0x11002000 0 0x400>; 569b3a37248SEddie Huang interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 5700e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 5710e84faa1SSascha Hauer clock-names = "baud", "bus"; 572b3a37248SEddie Huang status = "disabled"; 573b3a37248SEddie Huang }; 574b3a37248SEddie Huang 575b3a37248SEddie Huang uart1: serial@11003000 { 576b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 577b3a37248SEddie Huang "mediatek,mt6577-uart"; 578b3a37248SEddie Huang reg = <0 0x11003000 0 0x400>; 579b3a37248SEddie Huang interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 5800e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 5810e84faa1SSascha Hauer clock-names = "baud", "bus"; 582b3a37248SEddie Huang status = "disabled"; 583b3a37248SEddie Huang }; 584b3a37248SEddie Huang 585b3a37248SEddie Huang uart2: serial@11004000 { 586b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 587b3a37248SEddie Huang "mediatek,mt6577-uart"; 588b3a37248SEddie Huang reg = <0 0x11004000 0 0x400>; 589b3a37248SEddie Huang interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 5900e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 5910e84faa1SSascha Hauer clock-names = "baud", "bus"; 592b3a37248SEddie Huang status = "disabled"; 593b3a37248SEddie Huang }; 594b3a37248SEddie Huang 595b3a37248SEddie Huang uart3: serial@11005000 { 596b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 597b3a37248SEddie Huang "mediatek,mt6577-uart"; 598b3a37248SEddie Huang reg = <0 0x11005000 0 0x400>; 599b3a37248SEddie Huang interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 6000e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 6010e84faa1SSascha Hauer clock-names = "baud", "bus"; 602b3a37248SEddie Huang status = "disabled"; 603b3a37248SEddie Huang }; 604091cf598SEddie Huang 605091cf598SEddie Huang i2c0: i2c@11007000 { 606091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 607091cf598SEddie Huang reg = <0 0x11007000 0 0x70>, 608091cf598SEddie Huang <0 0x11000100 0 0x80>; 609091cf598SEddie Huang interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 610091cf598SEddie Huang clock-div = <16>; 611091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C0>, 612091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 613091cf598SEddie Huang clock-names = "main", "dma"; 614091cf598SEddie Huang pinctrl-names = "default"; 615091cf598SEddie Huang pinctrl-0 = <&i2c0_pins_a>; 616091cf598SEddie Huang #address-cells = <1>; 617091cf598SEddie Huang #size-cells = <0>; 618091cf598SEddie Huang status = "disabled"; 619091cf598SEddie Huang }; 620091cf598SEddie Huang 621091cf598SEddie Huang i2c1: i2c@11008000 { 622091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 623091cf598SEddie Huang reg = <0 0x11008000 0 0x70>, 624091cf598SEddie Huang <0 0x11000180 0 0x80>; 625091cf598SEddie Huang interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 626091cf598SEddie Huang clock-div = <16>; 627091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C1>, 628091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 629091cf598SEddie Huang clock-names = "main", "dma"; 630091cf598SEddie Huang pinctrl-names = "default"; 631091cf598SEddie Huang pinctrl-0 = <&i2c1_pins_a>; 632091cf598SEddie Huang #address-cells = <1>; 633091cf598SEddie Huang #size-cells = <0>; 634091cf598SEddie Huang status = "disabled"; 635091cf598SEddie Huang }; 636091cf598SEddie Huang 637091cf598SEddie Huang i2c2: i2c@11009000 { 638091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 639091cf598SEddie Huang reg = <0 0x11009000 0 0x70>, 640091cf598SEddie Huang <0 0x11000200 0 0x80>; 641091cf598SEddie Huang interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 642091cf598SEddie Huang clock-div = <16>; 643091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C2>, 644091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 645091cf598SEddie Huang clock-names = "main", "dma"; 646091cf598SEddie Huang pinctrl-names = "default"; 647091cf598SEddie Huang pinctrl-0 = <&i2c2_pins_a>; 648091cf598SEddie Huang #address-cells = <1>; 649091cf598SEddie Huang #size-cells = <0>; 650091cf598SEddie Huang status = "disabled"; 651091cf598SEddie Huang }; 652091cf598SEddie Huang 653b0c936f5SLeilk Liu spi: spi@1100a000 { 654b0c936f5SLeilk Liu compatible = "mediatek,mt8173-spi"; 655b0c936f5SLeilk Liu #address-cells = <1>; 656b0c936f5SLeilk Liu #size-cells = <0>; 657b0c936f5SLeilk Liu reg = <0 0x1100a000 0 0x1000>; 658b0c936f5SLeilk Liu interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 659b0c936f5SLeilk Liu clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 660b0c936f5SLeilk Liu <&topckgen CLK_TOP_SPI_SEL>, 661b0c936f5SLeilk Liu <&pericfg CLK_PERI_SPI0>; 662b0c936f5SLeilk Liu clock-names = "parent-clk", "sel-clk", "spi-clk"; 663b0c936f5SLeilk Liu status = "disabled"; 664b0c936f5SLeilk Liu }; 665b0c936f5SLeilk Liu 666748c7d4dSSascha Hauer thermal: thermal@1100b000 { 667748c7d4dSSascha Hauer #thermal-sensor-cells = <0>; 668748c7d4dSSascha Hauer compatible = "mediatek,mt8173-thermal"; 669748c7d4dSSascha Hauer reg = <0 0x1100b000 0 0x1000>; 670748c7d4dSSascha Hauer interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 671748c7d4dSSascha Hauer clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 672748c7d4dSSascha Hauer clock-names = "therm", "auxadc"; 673748c7d4dSSascha Hauer resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 674748c7d4dSSascha Hauer mediatek,auxadc = <&auxadc>; 675748c7d4dSSascha Hauer mediatek,apmixedsys = <&apmixedsys>; 6766de18454Sdawei.chien@mediatek.com nvmem-cells = <&thermal_calibration>; 6776de18454Sdawei.chien@mediatek.com nvmem-cell-names = "calibration-data"; 678748c7d4dSSascha Hauer }; 679748c7d4dSSascha Hauer 68086cb8a88SBayi Cheng nor_flash: spi@1100d000 { 68186cb8a88SBayi Cheng compatible = "mediatek,mt8173-nor"; 68286cb8a88SBayi Cheng reg = <0 0x1100d000 0 0xe0>; 68386cb8a88SBayi Cheng clocks = <&pericfg CLK_PERI_SPI>, 68486cb8a88SBayi Cheng <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 68586cb8a88SBayi Cheng clock-names = "spi", "sf"; 68686cb8a88SBayi Cheng #address-cells = <1>; 68786cb8a88SBayi Cheng #size-cells = <0>; 68886cb8a88SBayi Cheng status = "disabled"; 68986cb8a88SBayi Cheng }; 69086cb8a88SBayi Cheng 6911ee35c05SYingjoe Chen i2c3: i2c@11010000 { 692091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 693091cf598SEddie Huang reg = <0 0x11010000 0 0x70>, 694091cf598SEddie Huang <0 0x11000280 0 0x80>; 695091cf598SEddie Huang interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 696091cf598SEddie Huang clock-div = <16>; 697091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C3>, 698091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 699091cf598SEddie Huang clock-names = "main", "dma"; 700091cf598SEddie Huang pinctrl-names = "default"; 701091cf598SEddie Huang pinctrl-0 = <&i2c3_pins_a>; 702091cf598SEddie Huang #address-cells = <1>; 703091cf598SEddie Huang #size-cells = <0>; 704091cf598SEddie Huang status = "disabled"; 705091cf598SEddie Huang }; 706091cf598SEddie Huang 7071ee35c05SYingjoe Chen i2c4: i2c@11011000 { 708091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 709091cf598SEddie Huang reg = <0 0x11011000 0 0x70>, 710091cf598SEddie Huang <0 0x11000300 0 0x80>; 711091cf598SEddie Huang interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 712091cf598SEddie Huang clock-div = <16>; 713091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C4>, 714091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 715091cf598SEddie Huang clock-names = "main", "dma"; 716091cf598SEddie Huang pinctrl-names = "default"; 717091cf598SEddie Huang pinctrl-0 = <&i2c4_pins_a>; 718091cf598SEddie Huang #address-cells = <1>; 719091cf598SEddie Huang #size-cells = <0>; 720091cf598SEddie Huang status = "disabled"; 721091cf598SEddie Huang }; 722091cf598SEddie Huang 723a10b57f4SCK Hu hdmiddc0: i2c@11012000 { 724a10b57f4SCK Hu compatible = "mediatek,mt8173-hdmi-ddc"; 725a10b57f4SCK Hu interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 726a10b57f4SCK Hu reg = <0 0x11012000 0 0x1C>; 727a10b57f4SCK Hu clocks = <&pericfg CLK_PERI_I2C5>; 728a10b57f4SCK Hu clock-names = "ddc-i2c"; 729a10b57f4SCK Hu }; 730a10b57f4SCK Hu 7311ee35c05SYingjoe Chen i2c6: i2c@11013000 { 732091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 733091cf598SEddie Huang reg = <0 0x11013000 0 0x70>, 734091cf598SEddie Huang <0 0x11000080 0 0x80>; 735091cf598SEddie Huang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 736091cf598SEddie Huang clock-div = <16>; 737091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C6>, 738091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 739091cf598SEddie Huang clock-names = "main", "dma"; 740091cf598SEddie Huang pinctrl-names = "default"; 741091cf598SEddie Huang pinctrl-0 = <&i2c6_pins_a>; 742091cf598SEddie Huang #address-cells = <1>; 743091cf598SEddie Huang #size-cells = <0>; 744091cf598SEddie Huang status = "disabled"; 745091cf598SEddie Huang }; 746c02e0e86SKoro Chen 747c02e0e86SKoro Chen afe: audio-controller@11220000 { 748c02e0e86SKoro Chen compatible = "mediatek,mt8173-afe-pcm"; 749c02e0e86SKoro Chen reg = <0 0x11220000 0 0x1000>; 750c02e0e86SKoro Chen interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 751c02e0e86SKoro Chen power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; 752c02e0e86SKoro Chen clocks = <&infracfg CLK_INFRA_AUDIO>, 753c02e0e86SKoro Chen <&topckgen CLK_TOP_AUDIO_SEL>, 754c02e0e86SKoro Chen <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 755c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL1_DIV0>, 756c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL2_DIV0>, 757c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S0_M_SEL>, 758c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S1_M_SEL>, 759c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S2_M_SEL>, 760c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S3_M_SEL>, 761c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S3_B_SEL>; 762c02e0e86SKoro Chen clock-names = "infra_sys_audio_clk", 763c02e0e86SKoro Chen "top_pdn_audio", 764c02e0e86SKoro Chen "top_pdn_aud_intbus", 765c02e0e86SKoro Chen "bck0", 766c02e0e86SKoro Chen "bck1", 767c02e0e86SKoro Chen "i2s0_m", 768c02e0e86SKoro Chen "i2s1_m", 769c02e0e86SKoro Chen "i2s2_m", 770c02e0e86SKoro Chen "i2s3_m", 771c02e0e86SKoro Chen "i2s3_b"; 772c02e0e86SKoro Chen assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 773c02e0e86SKoro Chen <&topckgen CLK_TOP_AUD_2_SEL>; 774c02e0e86SKoro Chen assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 775c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL2>; 776c02e0e86SKoro Chen }; 7779719fa5aSEddie Huang 7789719fa5aSEddie Huang mmc0: mmc@11230000 { 779689362b3SChaotian Jing compatible = "mediatek,mt8173-mmc"; 7809719fa5aSEddie Huang reg = <0 0x11230000 0 0x1000>; 7819719fa5aSEddie Huang interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 7829719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_0>, 7839719fa5aSEddie Huang <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 7849719fa5aSEddie Huang clock-names = "source", "hclk"; 7859719fa5aSEddie Huang status = "disabled"; 7869719fa5aSEddie Huang }; 7879719fa5aSEddie Huang 7889719fa5aSEddie Huang mmc1: mmc@11240000 { 789689362b3SChaotian Jing compatible = "mediatek,mt8173-mmc"; 7909719fa5aSEddie Huang reg = <0 0x11240000 0 0x1000>; 7919719fa5aSEddie Huang interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 7929719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_1>, 7939719fa5aSEddie Huang <&topckgen CLK_TOP_AXI_SEL>; 7949719fa5aSEddie Huang clock-names = "source", "hclk"; 7959719fa5aSEddie Huang status = "disabled"; 7969719fa5aSEddie Huang }; 7979719fa5aSEddie Huang 7989719fa5aSEddie Huang mmc2: mmc@11250000 { 799689362b3SChaotian Jing compatible = "mediatek,mt8173-mmc"; 8009719fa5aSEddie Huang reg = <0 0x11250000 0 0x1000>; 8019719fa5aSEddie Huang interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 8029719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_2>, 8039719fa5aSEddie Huang <&topckgen CLK_TOP_AXI_SEL>; 8049719fa5aSEddie Huang clock-names = "source", "hclk"; 8059719fa5aSEddie Huang status = "disabled"; 8069719fa5aSEddie Huang }; 8079719fa5aSEddie Huang 8089719fa5aSEddie Huang mmc3: mmc@11260000 { 809689362b3SChaotian Jing compatible = "mediatek,mt8173-mmc"; 8109719fa5aSEddie Huang reg = <0 0x11260000 0 0x1000>; 8119719fa5aSEddie Huang interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 8129719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_3>, 8139719fa5aSEddie Huang <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 8149719fa5aSEddie Huang clock-names = "source", "hclk"; 8159719fa5aSEddie Huang status = "disabled"; 8169719fa5aSEddie Huang }; 81767e56c56SJames Liao 818c0891284SChunfeng Yun ssusb: usb@11271000 { 819c0891284SChunfeng Yun compatible = "mediatek,mt8173-mtu3"; 820c0891284SChunfeng Yun reg = <0 0x11271000 0 0x3000>, 821bfcce47aSChunfeng Yun <0 0x11280700 0 0x0100>; 822c0891284SChunfeng Yun reg-names = "mac", "ippc"; 823c0891284SChunfeng Yun interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>; 824ebf61c63Schunfeng.yun@mediatek.com phys = <&u2port0 PHY_TYPE_USB2>, 825ebf61c63Schunfeng.yun@mediatek.com <&u3port0 PHY_TYPE_USB3>, 826ebf61c63Schunfeng.yun@mediatek.com <&u2port1 PHY_TYPE_USB2>; 827bfcce47aSChunfeng Yun power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 828cf1fcd45SChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 829cf1fcd45SChunfeng Yun clock-names = "sys_ck", "ref_ck"; 830cf1fcd45SChunfeng Yun mediatek,syscon-wakeup = <&pericfg 0x400 1>; 831c0891284SChunfeng Yun #address-cells = <2>; 832c0891284SChunfeng Yun #size-cells = <2>; 833c0891284SChunfeng Yun ranges; 834c0891284SChunfeng Yun status = "disabled"; 835c0891284SChunfeng Yun 836c0891284SChunfeng Yun usb_host: xhci@11270000 { 837c0891284SChunfeng Yun compatible = "mediatek,mt8173-xhci"; 838c0891284SChunfeng Yun reg = <0 0x11270000 0 0x1000>; 839c0891284SChunfeng Yun reg-names = "mac"; 840c0891284SChunfeng Yun interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 841c0891284SChunfeng Yun power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 842cb6efc7bSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 843cb6efc7bSChunfeng Yun clock-names = "sys_ck", "ref_ck"; 844c0891284SChunfeng Yun status = "disabled"; 845c0891284SChunfeng Yun }; 846bfcce47aSChunfeng Yun }; 847bfcce47aSChunfeng Yun 848bfcce47aSChunfeng Yun u3phy: usb-phy@11290000 { 849bfcce47aSChunfeng Yun compatible = "mediatek,mt8173-u3phy"; 850bfcce47aSChunfeng Yun reg = <0 0x11290000 0 0x800>; 851bfcce47aSChunfeng Yun #address-cells = <2>; 852bfcce47aSChunfeng Yun #size-cells = <2>; 853bfcce47aSChunfeng Yun ranges; 854bfcce47aSChunfeng Yun status = "okay"; 855bfcce47aSChunfeng Yun 856ebf61c63Schunfeng.yun@mediatek.com u2port0: usb-phy@11290800 { 857ebf61c63Schunfeng.yun@mediatek.com reg = <0 0x11290800 0 0x100>; 85810f84a7aSchunfeng.yun@mediatek.com clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 85910f84a7aSchunfeng.yun@mediatek.com clock-names = "ref"; 860bfcce47aSChunfeng Yun #phy-cells = <1>; 861bfcce47aSChunfeng Yun status = "okay"; 862bfcce47aSChunfeng Yun }; 863bfcce47aSChunfeng Yun 864ebf61c63Schunfeng.yun@mediatek.com u3port0: usb-phy@11290900 { 865ebf61c63Schunfeng.yun@mediatek.com reg = <0 0x11290900 0 0x700>; 86610f84a7aSchunfeng.yun@mediatek.com clocks = <&clk26m>; 86710f84a7aSchunfeng.yun@mediatek.com clock-names = "ref"; 868ebf61c63Schunfeng.yun@mediatek.com #phy-cells = <1>; 869ebf61c63Schunfeng.yun@mediatek.com status = "okay"; 870ebf61c63Schunfeng.yun@mediatek.com }; 871ebf61c63Schunfeng.yun@mediatek.com 872ebf61c63Schunfeng.yun@mediatek.com u2port1: usb-phy@11291000 { 873ebf61c63Schunfeng.yun@mediatek.com reg = <0 0x11291000 0 0x100>; 87410f84a7aSchunfeng.yun@mediatek.com clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 87510f84a7aSchunfeng.yun@mediatek.com clock-names = "ref"; 876bfcce47aSChunfeng Yun #phy-cells = <1>; 877bfcce47aSChunfeng Yun status = "okay"; 878bfcce47aSChunfeng Yun }; 879bfcce47aSChunfeng Yun }; 880bfcce47aSChunfeng Yun 88167e56c56SJames Liao mmsys: clock-controller@14000000 { 88267e56c56SJames Liao compatible = "mediatek,mt8173-mmsys", "syscon"; 88367e56c56SJames Liao reg = <0 0x14000000 0 0x1000>; 88481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 885fc6634acSBibby Hsieh assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; 886fc6634acSBibby Hsieh assigned-clock-rates = <400000000>; 88767e56c56SJames Liao #clock-cells = <1>; 88867e56c56SJames Liao }; 88967e56c56SJames Liao 890989b292aSMinghsiu Tsai mdp_rdma0: rdma@14001000 { 8918127881fSDaniel Kurtz compatible = "mediatek,mt8173-mdp-rdma", 8928127881fSDaniel Kurtz "mediatek,mt8173-mdp"; 893989b292aSMinghsiu Tsai reg = <0 0x14001000 0 0x1000>; 894989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RDMA0>, 895989b292aSMinghsiu Tsai <&mmsys CLK_MM_MUTEX_32K>; 896989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 897989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_RDMA0>; 898989b292aSMinghsiu Tsai mediatek,larb = <&larb0>; 8998127881fSDaniel Kurtz mediatek,vpu = <&vpu>; 900989b292aSMinghsiu Tsai }; 901989b292aSMinghsiu Tsai 902989b292aSMinghsiu Tsai mdp_rdma1: rdma@14002000 { 903989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rdma"; 904989b292aSMinghsiu Tsai reg = <0 0x14002000 0 0x1000>; 905989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RDMA1>, 906989b292aSMinghsiu Tsai <&mmsys CLK_MM_MUTEX_32K>; 907989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 908989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_RDMA1>; 909989b292aSMinghsiu Tsai mediatek,larb = <&larb4>; 910989b292aSMinghsiu Tsai }; 911989b292aSMinghsiu Tsai 912989b292aSMinghsiu Tsai mdp_rsz0: rsz@14003000 { 913989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rsz"; 914989b292aSMinghsiu Tsai reg = <0 0x14003000 0 0x1000>; 915989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RSZ0>; 916989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 917989b292aSMinghsiu Tsai }; 918989b292aSMinghsiu Tsai 919989b292aSMinghsiu Tsai mdp_rsz1: rsz@14004000 { 920989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rsz"; 921989b292aSMinghsiu Tsai reg = <0 0x14004000 0 0x1000>; 922989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RSZ1>; 923989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 924989b292aSMinghsiu Tsai }; 925989b292aSMinghsiu Tsai 926989b292aSMinghsiu Tsai mdp_rsz2: rsz@14005000 { 927989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rsz"; 928989b292aSMinghsiu Tsai reg = <0 0x14005000 0 0x1000>; 929989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RSZ2>; 930989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 931989b292aSMinghsiu Tsai }; 932989b292aSMinghsiu Tsai 933989b292aSMinghsiu Tsai mdp_wdma0: wdma@14006000 { 934989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-wdma"; 935989b292aSMinghsiu Tsai reg = <0 0x14006000 0 0x1000>; 936989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_WDMA>; 937989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 938989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_WDMA>; 939989b292aSMinghsiu Tsai mediatek,larb = <&larb0>; 940989b292aSMinghsiu Tsai }; 941989b292aSMinghsiu Tsai 942989b292aSMinghsiu Tsai mdp_wrot0: wrot@14007000 { 943989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-wrot"; 944989b292aSMinghsiu Tsai reg = <0 0x14007000 0 0x1000>; 945989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_WROT0>; 946989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 947989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_WROT0>; 948989b292aSMinghsiu Tsai mediatek,larb = <&larb0>; 949989b292aSMinghsiu Tsai }; 950989b292aSMinghsiu Tsai 951989b292aSMinghsiu Tsai mdp_wrot1: wrot@14008000 { 952989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-wrot"; 953989b292aSMinghsiu Tsai reg = <0 0x14008000 0 0x1000>; 954989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_WROT1>; 955989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 956989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_WROT1>; 957989b292aSMinghsiu Tsai mediatek,larb = <&larb4>; 958989b292aSMinghsiu Tsai }; 959989b292aSMinghsiu Tsai 96081ad4dbaSCK Hu ovl0: ovl@1400c000 { 96181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-ovl"; 96281ad4dbaSCK Hu reg = <0 0x1400c000 0 0x1000>; 96381ad4dbaSCK Hu interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 96481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 96581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_OVL0>; 96681ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_OVL0>; 96781ad4dbaSCK Hu mediatek,larb = <&larb0>; 96881ad4dbaSCK Hu }; 96981ad4dbaSCK Hu 97081ad4dbaSCK Hu ovl1: ovl@1400d000 { 97181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-ovl"; 97281ad4dbaSCK Hu reg = <0 0x1400d000 0 0x1000>; 97381ad4dbaSCK Hu interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; 97481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 97581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_OVL1>; 97681ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_OVL1>; 97781ad4dbaSCK Hu mediatek,larb = <&larb4>; 97881ad4dbaSCK Hu }; 97981ad4dbaSCK Hu 98081ad4dbaSCK Hu rdma0: rdma@1400e000 { 98181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-rdma"; 98281ad4dbaSCK Hu reg = <0 0x1400e000 0 0x1000>; 98381ad4dbaSCK Hu interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 98481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 98581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_RDMA0>; 98681ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_RDMA0>; 98781ad4dbaSCK Hu mediatek,larb = <&larb0>; 98881ad4dbaSCK Hu }; 98981ad4dbaSCK Hu 99081ad4dbaSCK Hu rdma1: rdma@1400f000 { 99181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-rdma"; 99281ad4dbaSCK Hu reg = <0 0x1400f000 0 0x1000>; 99381ad4dbaSCK Hu interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; 99481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 99581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_RDMA1>; 99681ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_RDMA1>; 99781ad4dbaSCK Hu mediatek,larb = <&larb4>; 99881ad4dbaSCK Hu }; 99981ad4dbaSCK Hu 100081ad4dbaSCK Hu rdma2: rdma@14010000 { 100181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-rdma"; 100281ad4dbaSCK Hu reg = <0 0x14010000 0 0x1000>; 100381ad4dbaSCK Hu interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; 100481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 100581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_RDMA2>; 100681ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_RDMA2>; 100781ad4dbaSCK Hu mediatek,larb = <&larb4>; 100881ad4dbaSCK Hu }; 100981ad4dbaSCK Hu 101081ad4dbaSCK Hu wdma0: wdma@14011000 { 101181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-wdma"; 101281ad4dbaSCK Hu reg = <0 0x14011000 0 0x1000>; 101381ad4dbaSCK Hu interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 101481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 101581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_WDMA0>; 101681ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_WDMA0>; 101781ad4dbaSCK Hu mediatek,larb = <&larb0>; 101881ad4dbaSCK Hu }; 101981ad4dbaSCK Hu 102081ad4dbaSCK Hu wdma1: wdma@14012000 { 102181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-wdma"; 102281ad4dbaSCK Hu reg = <0 0x14012000 0 0x1000>; 102381ad4dbaSCK Hu interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; 102481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 102581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_WDMA1>; 102681ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_WDMA1>; 102781ad4dbaSCK Hu mediatek,larb = <&larb4>; 102881ad4dbaSCK Hu }; 102981ad4dbaSCK Hu 103081ad4dbaSCK Hu color0: color@14013000 { 103181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-color"; 103281ad4dbaSCK Hu reg = <0 0x14013000 0 0x1000>; 103381ad4dbaSCK Hu interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; 103481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 103581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_COLOR0>; 103681ad4dbaSCK Hu }; 103781ad4dbaSCK Hu 103881ad4dbaSCK Hu color1: color@14014000 { 103981ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-color"; 104081ad4dbaSCK Hu reg = <0 0x14014000 0 0x1000>; 104181ad4dbaSCK Hu interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 104281ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 104381ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_COLOR1>; 104481ad4dbaSCK Hu }; 104581ad4dbaSCK Hu 104681ad4dbaSCK Hu aal@14015000 { 104781ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-aal"; 104881ad4dbaSCK Hu reg = <0 0x14015000 0 0x1000>; 104981ad4dbaSCK Hu interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 105081ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 105181ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_AAL>; 105281ad4dbaSCK Hu }; 105381ad4dbaSCK Hu 105481ad4dbaSCK Hu gamma@14016000 { 105581ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-gamma"; 105681ad4dbaSCK Hu reg = <0 0x14016000 0 0x1000>; 105781ad4dbaSCK Hu interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 105881ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 105981ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_GAMMA>; 106081ad4dbaSCK Hu }; 106181ad4dbaSCK Hu 106281ad4dbaSCK Hu merge@14017000 { 106381ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-merge"; 106481ad4dbaSCK Hu reg = <0 0x14017000 0 0x1000>; 106581ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 106681ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_MERGE>; 106781ad4dbaSCK Hu }; 106881ad4dbaSCK Hu 106981ad4dbaSCK Hu split0: split@14018000 { 107081ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-split"; 107181ad4dbaSCK Hu reg = <0 0x14018000 0 0x1000>; 107281ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 107381ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_SPLIT0>; 107481ad4dbaSCK Hu }; 107581ad4dbaSCK Hu 107681ad4dbaSCK Hu split1: split@14019000 { 107781ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-split"; 107881ad4dbaSCK Hu reg = <0 0x14019000 0 0x1000>; 107981ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 108081ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_SPLIT1>; 108181ad4dbaSCK Hu }; 108281ad4dbaSCK Hu 108381ad4dbaSCK Hu ufoe@1401a000 { 108481ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-ufoe"; 108581ad4dbaSCK Hu reg = <0 0x1401a000 0 0x1000>; 108681ad4dbaSCK Hu interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 108781ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 108881ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_UFOE>; 108981ad4dbaSCK Hu }; 109081ad4dbaSCK Hu 109181ad4dbaSCK Hu dsi0: dsi@1401b000 { 109281ad4dbaSCK Hu compatible = "mediatek,mt8173-dsi"; 109381ad4dbaSCK Hu reg = <0 0x1401b000 0 0x1000>; 109481ad4dbaSCK Hu interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 109581ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 109681ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DSI0_ENGINE>, 109781ad4dbaSCK Hu <&mmsys CLK_MM_DSI0_DIGITAL>, 109881ad4dbaSCK Hu <&mipi_tx0>; 109981ad4dbaSCK Hu clock-names = "engine", "digital", "hs"; 110081ad4dbaSCK Hu phys = <&mipi_tx0>; 110181ad4dbaSCK Hu phy-names = "dphy"; 110281ad4dbaSCK Hu status = "disabled"; 110381ad4dbaSCK Hu }; 110481ad4dbaSCK Hu 110581ad4dbaSCK Hu dsi1: dsi@1401c000 { 110681ad4dbaSCK Hu compatible = "mediatek,mt8173-dsi"; 110781ad4dbaSCK Hu reg = <0 0x1401c000 0 0x1000>; 110881ad4dbaSCK Hu interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 110981ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 111081ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DSI1_ENGINE>, 111181ad4dbaSCK Hu <&mmsys CLK_MM_DSI1_DIGITAL>, 111281ad4dbaSCK Hu <&mipi_tx1>; 111381ad4dbaSCK Hu clock-names = "engine", "digital", "hs"; 111481ad4dbaSCK Hu phy = <&mipi_tx1>; 111581ad4dbaSCK Hu phy-names = "dphy"; 111681ad4dbaSCK Hu status = "disabled"; 111781ad4dbaSCK Hu }; 111881ad4dbaSCK Hu 111981ad4dbaSCK Hu dpi0: dpi@1401d000 { 112081ad4dbaSCK Hu compatible = "mediatek,mt8173-dpi"; 112181ad4dbaSCK Hu reg = <0 0x1401d000 0 0x1000>; 112281ad4dbaSCK Hu interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 112381ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 112481ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DPI_PIXEL>, 112581ad4dbaSCK Hu <&mmsys CLK_MM_DPI_ENGINE>, 112681ad4dbaSCK Hu <&apmixedsys CLK_APMIXED_TVDPLL>; 112781ad4dbaSCK Hu clock-names = "pixel", "engine", "pll"; 112881ad4dbaSCK Hu status = "disabled"; 1129a10b57f4SCK Hu 1130a10b57f4SCK Hu port { 1131a10b57f4SCK Hu dpi0_out: endpoint { 1132a10b57f4SCK Hu remote-endpoint = <&hdmi0_in>; 1133a10b57f4SCK Hu }; 1134a10b57f4SCK Hu }; 113581ad4dbaSCK Hu }; 113681ad4dbaSCK Hu 113761aee934SYH Huang pwm0: pwm@1401e000 { 113861aee934SYH Huang compatible = "mediatek,mt8173-disp-pwm", 113961aee934SYH Huang "mediatek,mt6595-disp-pwm"; 114061aee934SYH Huang reg = <0 0x1401e000 0 0x1000>; 114161aee934SYH Huang #pwm-cells = <2>; 114261aee934SYH Huang clocks = <&mmsys CLK_MM_DISP_PWM026M>, 114361aee934SYH Huang <&mmsys CLK_MM_DISP_PWM0MM>; 114461aee934SYH Huang clock-names = "main", "mm"; 114561aee934SYH Huang status = "disabled"; 114661aee934SYH Huang }; 114761aee934SYH Huang 114861aee934SYH Huang pwm1: pwm@1401f000 { 114961aee934SYH Huang compatible = "mediatek,mt8173-disp-pwm", 115061aee934SYH Huang "mediatek,mt6595-disp-pwm"; 115161aee934SYH Huang reg = <0 0x1401f000 0 0x1000>; 115261aee934SYH Huang #pwm-cells = <2>; 115361aee934SYH Huang clocks = <&mmsys CLK_MM_DISP_PWM126M>, 115461aee934SYH Huang <&mmsys CLK_MM_DISP_PWM1MM>; 115561aee934SYH Huang clock-names = "main", "mm"; 115661aee934SYH Huang status = "disabled"; 115761aee934SYH Huang }; 115861aee934SYH Huang 115981ad4dbaSCK Hu mutex: mutex@14020000 { 116081ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-mutex"; 116181ad4dbaSCK Hu reg = <0 0x14020000 0 0x1000>; 116281ad4dbaSCK Hu interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 116381ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 116481ad4dbaSCK Hu clocks = <&mmsys CLK_MM_MUTEX_32K>; 116581ad4dbaSCK Hu }; 116681ad4dbaSCK Hu 11675ff6b3a6SYong Wu larb0: larb@14021000 { 11685ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 11695ff6b3a6SYong Wu reg = <0 0x14021000 0 0x1000>; 11705ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 11715ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 11725ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_LARB0>, 11735ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_LARB0>; 11745ff6b3a6SYong Wu clock-names = "apb", "smi"; 11755ff6b3a6SYong Wu }; 11765ff6b3a6SYong Wu 11775ff6b3a6SYong Wu smi_common: smi@14022000 { 11785ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-common"; 11795ff6b3a6SYong Wu reg = <0 0x14022000 0 0x1000>; 11805ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 11815ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_COMMON>, 11825ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_COMMON>; 11835ff6b3a6SYong Wu clock-names = "apb", "smi"; 11845ff6b3a6SYong Wu }; 11855ff6b3a6SYong Wu 118681ad4dbaSCK Hu od@14023000 { 118781ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-od"; 118881ad4dbaSCK Hu reg = <0 0x14023000 0 0x1000>; 118981ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_OD>; 119081ad4dbaSCK Hu }; 119181ad4dbaSCK Hu 1192a10b57f4SCK Hu hdmi0: hdmi@14025000 { 1193a10b57f4SCK Hu compatible = "mediatek,mt8173-hdmi"; 1194a10b57f4SCK Hu reg = <0 0x14025000 0 0x400>; 1195a10b57f4SCK Hu interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>; 1196a10b57f4SCK Hu clocks = <&mmsys CLK_MM_HDMI_PIXEL>, 1197a10b57f4SCK Hu <&mmsys CLK_MM_HDMI_PLLCK>, 1198a10b57f4SCK Hu <&mmsys CLK_MM_HDMI_AUDIO>, 1199a10b57f4SCK Hu <&mmsys CLK_MM_HDMI_SPDIF>; 1200a10b57f4SCK Hu clock-names = "pixel", "pll", "bclk", "spdif"; 1201a10b57f4SCK Hu pinctrl-names = "default"; 1202a10b57f4SCK Hu pinctrl-0 = <&hdmi_pin>; 1203a10b57f4SCK Hu phys = <&hdmi_phy>; 1204a10b57f4SCK Hu phy-names = "hdmi"; 1205a10b57f4SCK Hu mediatek,syscon-hdmi = <&mmsys 0x900>; 1206a10b57f4SCK Hu assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; 1207a10b57f4SCK Hu assigned-clock-parents = <&hdmi_phy>; 1208a10b57f4SCK Hu status = "disabled"; 1209a10b57f4SCK Hu 1210a10b57f4SCK Hu ports { 1211a10b57f4SCK Hu #address-cells = <1>; 1212a10b57f4SCK Hu #size-cells = <0>; 1213a10b57f4SCK Hu 1214a10b57f4SCK Hu port@0 { 1215a10b57f4SCK Hu reg = <0>; 1216a10b57f4SCK Hu 1217a10b57f4SCK Hu hdmi0_in: endpoint { 1218a10b57f4SCK Hu remote-endpoint = <&dpi0_out>; 1219a10b57f4SCK Hu }; 1220a10b57f4SCK Hu }; 1221a10b57f4SCK Hu }; 1222a10b57f4SCK Hu }; 1223a10b57f4SCK Hu 12245ff6b3a6SYong Wu larb4: larb@14027000 { 12255ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 12265ff6b3a6SYong Wu reg = <0 0x14027000 0 0x1000>; 12275ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 12285ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 12295ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_LARB4>, 12305ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_LARB4>; 12315ff6b3a6SYong Wu clock-names = "apb", "smi"; 12325ff6b3a6SYong Wu }; 12335ff6b3a6SYong Wu 123467e56c56SJames Liao imgsys: clock-controller@15000000 { 123567e56c56SJames Liao compatible = "mediatek,mt8173-imgsys", "syscon"; 123667e56c56SJames Liao reg = <0 0x15000000 0 0x1000>; 123767e56c56SJames Liao #clock-cells = <1>; 123867e56c56SJames Liao }; 123967e56c56SJames Liao 12405ff6b3a6SYong Wu larb2: larb@15001000 { 12415ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 12425ff6b3a6SYong Wu reg = <0 0x15001000 0 0x1000>; 12435ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 12445ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>; 12455ff6b3a6SYong Wu clocks = <&imgsys CLK_IMG_LARB2_SMI>, 12465ff6b3a6SYong Wu <&imgsys CLK_IMG_LARB2_SMI>; 12475ff6b3a6SYong Wu clock-names = "apb", "smi"; 12485ff6b3a6SYong Wu }; 12495ff6b3a6SYong Wu 125067e56c56SJames Liao vdecsys: clock-controller@16000000 { 125167e56c56SJames Liao compatible = "mediatek,mt8173-vdecsys", "syscon"; 125267e56c56SJames Liao reg = <0 0x16000000 0 0x1000>; 125367e56c56SJames Liao #clock-cells = <1>; 125467e56c56SJames Liao }; 125567e56c56SJames Liao 125660eaae2bSTiffany Lin vcodec_dec: vcodec@16000000 { 125760eaae2bSTiffany Lin compatible = "mediatek,mt8173-vcodec-dec"; 125860eaae2bSTiffany Lin reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */ 125960eaae2bSTiffany Lin <0 0x16020000 0 0x1000>, /* VDEC_MISC */ 126060eaae2bSTiffany Lin <0 0x16021000 0 0x800>, /* VDEC_LD */ 126160eaae2bSTiffany Lin <0 0x16021800 0 0x800>, /* VDEC_TOP */ 126260eaae2bSTiffany Lin <0 0x16022000 0 0x1000>, /* VDEC_CM */ 126360eaae2bSTiffany Lin <0 0x16023000 0 0x1000>, /* VDEC_AD */ 126460eaae2bSTiffany Lin <0 0x16024000 0 0x1000>, /* VDEC_AV */ 126560eaae2bSTiffany Lin <0 0x16025000 0 0x1000>, /* VDEC_PP */ 126660eaae2bSTiffany Lin <0 0x16026800 0 0x800>, /* VDEC_HWD */ 126760eaae2bSTiffany Lin <0 0x16027000 0 0x800>, /* VDEC_HWQ */ 126860eaae2bSTiffany Lin <0 0x16027800 0 0x800>, /* VDEC_HWB */ 126960eaae2bSTiffany Lin <0 0x16028400 0 0x400>; /* VDEC_HWG */ 127060eaae2bSTiffany Lin interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; 127160eaae2bSTiffany Lin mediatek,larb = <&larb1>; 127260eaae2bSTiffany Lin iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, 127360eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_PP_EXT>, 127460eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, 127560eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, 127660eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, 127760eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, 127860eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, 127960eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; 128060eaae2bSTiffany Lin mediatek,vpu = <&vpu>; 128160eaae2bSTiffany Lin power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 128260eaae2bSTiffany Lin clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, 128360eaae2bSTiffany Lin <&topckgen CLK_TOP_UNIVPLL_D2>, 128460eaae2bSTiffany Lin <&topckgen CLK_TOP_CCI400_SEL>, 128560eaae2bSTiffany Lin <&topckgen CLK_TOP_VDEC_SEL>, 128660eaae2bSTiffany Lin <&topckgen CLK_TOP_VCODECPLL>, 128760eaae2bSTiffany Lin <&apmixedsys CLK_APMIXED_VENCPLL>, 128860eaae2bSTiffany Lin <&topckgen CLK_TOP_VENC_LT_SEL>, 128960eaae2bSTiffany Lin <&topckgen CLK_TOP_VCODECPLL_370P5>; 129060eaae2bSTiffany Lin clock-names = "vcodecpll", 129160eaae2bSTiffany Lin "univpll_d2", 129260eaae2bSTiffany Lin "clk_cci400_sel", 129360eaae2bSTiffany Lin "vdec_sel", 129460eaae2bSTiffany Lin "vdecpll", 129560eaae2bSTiffany Lin "vencpll", 129660eaae2bSTiffany Lin "venc_lt_sel", 129760eaae2bSTiffany Lin "vdec_bus_clk_src"; 129860eaae2bSTiffany Lin }; 129960eaae2bSTiffany Lin 13005ff6b3a6SYong Wu larb1: larb@16010000 { 13015ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 13025ff6b3a6SYong Wu reg = <0 0x16010000 0 0x1000>; 13035ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 13045ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 13055ff6b3a6SYong Wu clocks = <&vdecsys CLK_VDEC_CKEN>, 13065ff6b3a6SYong Wu <&vdecsys CLK_VDEC_LARB_CKEN>; 13075ff6b3a6SYong Wu clock-names = "apb", "smi"; 13085ff6b3a6SYong Wu }; 13095ff6b3a6SYong Wu 131067e56c56SJames Liao vencsys: clock-controller@18000000 { 131167e56c56SJames Liao compatible = "mediatek,mt8173-vencsys", "syscon"; 131267e56c56SJames Liao reg = <0 0x18000000 0 0x1000>; 131367e56c56SJames Liao #clock-cells = <1>; 131467e56c56SJames Liao }; 131567e56c56SJames Liao 13165ff6b3a6SYong Wu larb3: larb@18001000 { 13175ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 13185ff6b3a6SYong Wu reg = <0 0x18001000 0 0x1000>; 13195ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 13205ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 13215ff6b3a6SYong Wu clocks = <&vencsys CLK_VENC_CKE1>, 13225ff6b3a6SYong Wu <&vencsys CLK_VENC_CKE0>; 13235ff6b3a6SYong Wu clock-names = "apb", "smi"; 13245ff6b3a6SYong Wu }; 13255ff6b3a6SYong Wu 13268eb80252STiffany Lin vcodec_enc: vcodec@18002000 { 13278eb80252STiffany Lin compatible = "mediatek,mt8173-vcodec-enc"; 13288eb80252STiffany Lin reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */ 13298eb80252STiffany Lin <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ 13308eb80252STiffany Lin interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>, 13318eb80252STiffany Lin <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; 13328eb80252STiffany Lin mediatek,larb = <&larb3>, 13338eb80252STiffany Lin <&larb5>; 13348eb80252STiffany Lin iommus = <&iommu M4U_PORT_VENC_RCPU>, 13358eb80252STiffany Lin <&iommu M4U_PORT_VENC_REC>, 13368eb80252STiffany Lin <&iommu M4U_PORT_VENC_BSDMA>, 13378eb80252STiffany Lin <&iommu M4U_PORT_VENC_SV_COMV>, 13388eb80252STiffany Lin <&iommu M4U_PORT_VENC_RD_COMV>, 13398eb80252STiffany Lin <&iommu M4U_PORT_VENC_CUR_LUMA>, 13408eb80252STiffany Lin <&iommu M4U_PORT_VENC_CUR_CHROMA>, 13418eb80252STiffany Lin <&iommu M4U_PORT_VENC_REF_LUMA>, 13428eb80252STiffany Lin <&iommu M4U_PORT_VENC_REF_CHROMA>, 13438eb80252STiffany Lin <&iommu M4U_PORT_VENC_NBM_RDMA>, 13448eb80252STiffany Lin <&iommu M4U_PORT_VENC_NBM_WDMA>, 13458eb80252STiffany Lin <&iommu M4U_PORT_VENC_RCPU_SET2>, 13468eb80252STiffany Lin <&iommu M4U_PORT_VENC_REC_FRM_SET2>, 13478eb80252STiffany Lin <&iommu M4U_PORT_VENC_BSDMA_SET2>, 13488eb80252STiffany Lin <&iommu M4U_PORT_VENC_SV_COMA_SET2>, 13498eb80252STiffany Lin <&iommu M4U_PORT_VENC_RD_COMA_SET2>, 13508eb80252STiffany Lin <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, 13518eb80252STiffany Lin <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, 13528eb80252STiffany Lin <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, 13538eb80252STiffany Lin <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; 13548eb80252STiffany Lin mediatek,vpu = <&vpu>; 13558eb80252STiffany Lin clocks = <&topckgen CLK_TOP_VENCPLL_D2>, 13568eb80252STiffany Lin <&topckgen CLK_TOP_VENC_SEL>, 13578eb80252STiffany Lin <&topckgen CLK_TOP_UNIVPLL1_D2>, 13588eb80252STiffany Lin <&topckgen CLK_TOP_VENC_LT_SEL>; 13598eb80252STiffany Lin clock-names = "venc_sel_src", 13608eb80252STiffany Lin "venc_sel", 13618eb80252STiffany Lin "venc_lt_sel_src", 13628eb80252STiffany Lin "venc_lt_sel"; 13638eb80252STiffany Lin }; 13648eb80252STiffany Lin 136567e56c56SJames Liao vencltsys: clock-controller@19000000 { 136667e56c56SJames Liao compatible = "mediatek,mt8173-vencltsys", "syscon"; 136767e56c56SJames Liao reg = <0 0x19000000 0 0x1000>; 136867e56c56SJames Liao #clock-cells = <1>; 136967e56c56SJames Liao }; 13705ff6b3a6SYong Wu 13715ff6b3a6SYong Wu larb5: larb@19001000 { 13725ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 13735ff6b3a6SYong Wu reg = <0 0x19001000 0 0x1000>; 13745ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 13755ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; 13765ff6b3a6SYong Wu clocks = <&vencltsys CLK_VENCLT_CKE1>, 13775ff6b3a6SYong Wu <&vencltsys CLK_VENCLT_CKE0>; 13785ff6b3a6SYong Wu clock-names = "apb", "smi"; 13795ff6b3a6SYong Wu }; 1380b3a37248SEddie Huang }; 1381b3a37248SEddie Huang}; 1382b3a37248SEddie Huang 1383