1b3a37248SEddie Huang/* 2b3a37248SEddie Huang * Copyright (c) 2014 MediaTek Inc. 3b3a37248SEddie Huang * Author: Eddie Huang <eddie.huang@mediatek.com> 4b3a37248SEddie Huang * 5b3a37248SEddie Huang * This program is free software; you can redistribute it and/or modify 6b3a37248SEddie Huang * it under the terms of the GNU General Public License version 2 as 7b3a37248SEddie Huang * published by the Free Software Foundation. 8b3a37248SEddie Huang * 9b3a37248SEddie Huang * This program is distributed in the hope that it will be useful, 10b3a37248SEddie Huang * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11b3a37248SEddie Huang * GNU General Public License for more details. 12b3a37248SEddie Huang */ 13b3a37248SEddie Huang 14f2ce7014SSascha Hauer#include <dt-bindings/clock/mt8173-clk.h> 15b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/irq.h> 16b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/arm-gic.h> 175ff6b3a6SYong Wu#include <dt-bindings/memory/mt8173-larb-port.h> 18bfcce47aSChunfeng Yun#include <dt-bindings/phy/phy.h> 19c02e0e86SKoro Chen#include <dt-bindings/power/mt8173-power.h> 20967313e2SPhilipp Zabel#include <dt-bindings/reset/mt8173-resets.h> 21359f9365SHongzhou Yang#include "mt8173-pinfunc.h" 22b3a37248SEddie Huang 23b3a37248SEddie Huang/ { 24b3a37248SEddie Huang compatible = "mediatek,mt8173"; 25b3a37248SEddie Huang interrupt-parent = <&sysirq>; 26b3a37248SEddie Huang #address-cells = <2>; 27b3a37248SEddie Huang #size-cells = <2>; 28b3a37248SEddie Huang 29b3a37248SEddie Huang cpus { 30b3a37248SEddie Huang #address-cells = <1>; 31b3a37248SEddie Huang #size-cells = <0>; 32b3a37248SEddie Huang 33b3a37248SEddie Huang cpu-map { 34b3a37248SEddie Huang cluster0 { 35b3a37248SEddie Huang core0 { 36b3a37248SEddie Huang cpu = <&cpu0>; 37b3a37248SEddie Huang }; 38b3a37248SEddie Huang core1 { 39b3a37248SEddie Huang cpu = <&cpu1>; 40b3a37248SEddie Huang }; 41b3a37248SEddie Huang }; 42b3a37248SEddie Huang 43b3a37248SEddie Huang cluster1 { 44b3a37248SEddie Huang core0 { 45b3a37248SEddie Huang cpu = <&cpu2>; 46b3a37248SEddie Huang }; 47b3a37248SEddie Huang core1 { 48b3a37248SEddie Huang cpu = <&cpu3>; 49b3a37248SEddie Huang }; 50b3a37248SEddie Huang }; 51b3a37248SEddie Huang }; 52b3a37248SEddie Huang 53b3a37248SEddie Huang cpu0: cpu@0 { 54b3a37248SEddie Huang device_type = "cpu"; 55b3a37248SEddie Huang compatible = "arm,cortex-a53"; 56b3a37248SEddie Huang reg = <0x000>; 57ad4df7a5SHoward Chen enable-method = "psci"; 58ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 59b3a37248SEddie Huang }; 60b3a37248SEddie Huang 61b3a37248SEddie Huang cpu1: cpu@1 { 62b3a37248SEddie Huang device_type = "cpu"; 63b3a37248SEddie Huang compatible = "arm,cortex-a53"; 64b3a37248SEddie Huang reg = <0x001>; 65b3a37248SEddie Huang enable-method = "psci"; 66ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 67b3a37248SEddie Huang }; 68b3a37248SEddie Huang 69b3a37248SEddie Huang cpu2: cpu@100 { 70b3a37248SEddie Huang device_type = "cpu"; 71b3a37248SEddie Huang compatible = "arm,cortex-a57"; 72b3a37248SEddie Huang reg = <0x100>; 73b3a37248SEddie Huang enable-method = "psci"; 74ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 75b3a37248SEddie Huang }; 76b3a37248SEddie Huang 77b3a37248SEddie Huang cpu3: cpu@101 { 78b3a37248SEddie Huang device_type = "cpu"; 79b3a37248SEddie Huang compatible = "arm,cortex-a57"; 80b3a37248SEddie Huang reg = <0x101>; 81b3a37248SEddie Huang enable-method = "psci"; 82ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 83ad4df7a5SHoward Chen }; 84ad4df7a5SHoward Chen 85ad4df7a5SHoward Chen idle-states { 86a13f18f5SLorenzo Pieralisi entry-method = "psci"; 87ad4df7a5SHoward Chen 88ad4df7a5SHoward Chen CPU_SLEEP_0: cpu-sleep-0 { 89ad4df7a5SHoward Chen compatible = "arm,idle-state"; 90ad4df7a5SHoward Chen local-timer-stop; 91ad4df7a5SHoward Chen entry-latency-us = <639>; 92ad4df7a5SHoward Chen exit-latency-us = <680>; 93ad4df7a5SHoward Chen min-residency-us = <1088>; 94ad4df7a5SHoward Chen arm,psci-suspend-param = <0x0010000>; 95ad4df7a5SHoward Chen }; 96b3a37248SEddie Huang }; 97b3a37248SEddie Huang }; 98b3a37248SEddie Huang 99b3a37248SEddie Huang psci { 10005bdabe7SFan Chen compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 101b3a37248SEddie Huang method = "smc"; 102b3a37248SEddie Huang cpu_suspend = <0x84000001>; 103b3a37248SEddie Huang cpu_off = <0x84000002>; 104b3a37248SEddie Huang cpu_on = <0x84000003>; 105b3a37248SEddie Huang }; 106b3a37248SEddie Huang 107f2ce7014SSascha Hauer clk26m: oscillator@0 { 108f2ce7014SSascha Hauer compatible = "fixed-clock"; 109f2ce7014SSascha Hauer #clock-cells = <0>; 110f2ce7014SSascha Hauer clock-frequency = <26000000>; 111f2ce7014SSascha Hauer clock-output-names = "clk26m"; 112f2ce7014SSascha Hauer }; 113f2ce7014SSascha Hauer 114f2ce7014SSascha Hauer clk32k: oscillator@1 { 115f2ce7014SSascha Hauer compatible = "fixed-clock"; 116f2ce7014SSascha Hauer #clock-cells = <0>; 117f2ce7014SSascha Hauer clock-frequency = <32000>; 118f2ce7014SSascha Hauer clock-output-names = "clk32k"; 119f2ce7014SSascha Hauer }; 120f2ce7014SSascha Hauer 12167e56c56SJames Liao cpum_ck: oscillator@2 { 12267e56c56SJames Liao compatible = "fixed-clock"; 12367e56c56SJames Liao #clock-cells = <0>; 12467e56c56SJames Liao clock-frequency = <0>; 12567e56c56SJames Liao clock-output-names = "cpum_ck"; 12667e56c56SJames Liao }; 12767e56c56SJames Liao 128962f5143Sdawei.chien@mediatek.com thermal-zones { 129962f5143Sdawei.chien@mediatek.com cpu_thermal: cpu_thermal { 130962f5143Sdawei.chien@mediatek.com polling-delay-passive = <1000>; /* milliseconds */ 131962f5143Sdawei.chien@mediatek.com polling-delay = <1000>; /* milliseconds */ 132962f5143Sdawei.chien@mediatek.com 133962f5143Sdawei.chien@mediatek.com thermal-sensors = <&thermal>; 134962f5143Sdawei.chien@mediatek.com sustainable-power = <1500>; /* milliwatts */ 135962f5143Sdawei.chien@mediatek.com 136962f5143Sdawei.chien@mediatek.com trips { 137962f5143Sdawei.chien@mediatek.com threshold: trip-point@0 { 138962f5143Sdawei.chien@mediatek.com temperature = <68000>; 139962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 140962f5143Sdawei.chien@mediatek.com type = "passive"; 141962f5143Sdawei.chien@mediatek.com }; 142962f5143Sdawei.chien@mediatek.com 143962f5143Sdawei.chien@mediatek.com target: trip-point@1 { 144962f5143Sdawei.chien@mediatek.com temperature = <85000>; 145962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 146962f5143Sdawei.chien@mediatek.com type = "passive"; 147962f5143Sdawei.chien@mediatek.com }; 148962f5143Sdawei.chien@mediatek.com 149962f5143Sdawei.chien@mediatek.com cpu_crit: cpu_crit@0 { 150962f5143Sdawei.chien@mediatek.com temperature = <115000>; 151962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 152962f5143Sdawei.chien@mediatek.com type = "critical"; 153962f5143Sdawei.chien@mediatek.com }; 154962f5143Sdawei.chien@mediatek.com }; 155962f5143Sdawei.chien@mediatek.com 156962f5143Sdawei.chien@mediatek.com cooling-maps { 157962f5143Sdawei.chien@mediatek.com map@0 { 158962f5143Sdawei.chien@mediatek.com trip = <&target>; 159962f5143Sdawei.chien@mediatek.com cooling-device = <&cpu0 0 0>; 160962f5143Sdawei.chien@mediatek.com contribution = <1024>; 161962f5143Sdawei.chien@mediatek.com }; 162962f5143Sdawei.chien@mediatek.com map@1 { 163962f5143Sdawei.chien@mediatek.com trip = <&target>; 164962f5143Sdawei.chien@mediatek.com cooling-device = <&cpu2 0 0>; 165962f5143Sdawei.chien@mediatek.com contribution = <2048>; 166962f5143Sdawei.chien@mediatek.com }; 167962f5143Sdawei.chien@mediatek.com }; 168962f5143Sdawei.chien@mediatek.com }; 169962f5143Sdawei.chien@mediatek.com }; 170962f5143Sdawei.chien@mediatek.com 171b3a37248SEddie Huang timer { 172b3a37248SEddie Huang compatible = "arm,armv8-timer"; 173b3a37248SEddie Huang interrupt-parent = <&gic>; 174b3a37248SEddie Huang interrupts = <GIC_PPI 13 175b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 176b3a37248SEddie Huang <GIC_PPI 14 177b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 178b3a37248SEddie Huang <GIC_PPI 11 179b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 180b3a37248SEddie Huang <GIC_PPI 10 181b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 182b3a37248SEddie Huang }; 183b3a37248SEddie Huang 184b3a37248SEddie Huang soc { 185b3a37248SEddie Huang #address-cells = <2>; 186b3a37248SEddie Huang #size-cells = <2>; 187b3a37248SEddie Huang compatible = "simple-bus"; 188b3a37248SEddie Huang ranges; 189b3a37248SEddie Huang 190f2ce7014SSascha Hauer topckgen: clock-controller@10000000 { 191f2ce7014SSascha Hauer compatible = "mediatek,mt8173-topckgen"; 192f2ce7014SSascha Hauer reg = <0 0x10000000 0 0x1000>; 193f2ce7014SSascha Hauer #clock-cells = <1>; 194f2ce7014SSascha Hauer }; 195f2ce7014SSascha Hauer 196f2ce7014SSascha Hauer infracfg: power-controller@10001000 { 197f2ce7014SSascha Hauer compatible = "mediatek,mt8173-infracfg", "syscon"; 198f2ce7014SSascha Hauer reg = <0 0x10001000 0 0x1000>; 199f2ce7014SSascha Hauer #clock-cells = <1>; 200f2ce7014SSascha Hauer #reset-cells = <1>; 201f2ce7014SSascha Hauer }; 202f2ce7014SSascha Hauer 203f2ce7014SSascha Hauer pericfg: power-controller@10003000 { 204f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pericfg", "syscon"; 205f2ce7014SSascha Hauer reg = <0 0x10003000 0 0x1000>; 206f2ce7014SSascha Hauer #clock-cells = <1>; 207f2ce7014SSascha Hauer #reset-cells = <1>; 208f2ce7014SSascha Hauer }; 209f2ce7014SSascha Hauer 210f2ce7014SSascha Hauer syscfg_pctl_a: syscfg_pctl_a@10005000 { 211f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 212f2ce7014SSascha Hauer reg = <0 0x10005000 0 0x1000>; 213f2ce7014SSascha Hauer }; 214f2ce7014SSascha Hauer 215f2ce7014SSascha Hauer pio: pinctrl@0x10005000 { 216359f9365SHongzhou Yang compatible = "mediatek,mt8173-pinctrl"; 2176769b93cSYingjoe Chen reg = <0 0x1000b000 0 0x1000>; 218359f9365SHongzhou Yang mediatek,pctl-regmap = <&syscfg_pctl_a>; 219359f9365SHongzhou Yang pins-are-numbered; 220359f9365SHongzhou Yang gpio-controller; 221359f9365SHongzhou Yang #gpio-cells = <2>; 222359f9365SHongzhou Yang interrupt-controller; 223359f9365SHongzhou Yang #interrupt-cells = <2>; 224359f9365SHongzhou Yang interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 225359f9365SHongzhou Yang <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 226359f9365SHongzhou Yang <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 227091cf598SEddie Huang 228091cf598SEddie Huang i2c0_pins_a: i2c0 { 229091cf598SEddie Huang pins1 { 230091cf598SEddie Huang pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 231091cf598SEddie Huang <MT8173_PIN_46_SCL0__FUNC_SCL0>; 232091cf598SEddie Huang bias-disable; 233091cf598SEddie Huang }; 234359f9365SHongzhou Yang }; 235359f9365SHongzhou Yang 236091cf598SEddie Huang i2c1_pins_a: i2c1 { 237091cf598SEddie Huang pins1 { 238091cf598SEddie Huang pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 239091cf598SEddie Huang <MT8173_PIN_126_SCL1__FUNC_SCL1>; 240091cf598SEddie Huang bias-disable; 241091cf598SEddie Huang }; 242091cf598SEddie Huang }; 243091cf598SEddie Huang 244091cf598SEddie Huang i2c2_pins_a: i2c2 { 245091cf598SEddie Huang pins1 { 246091cf598SEddie Huang pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 247091cf598SEddie Huang <MT8173_PIN_44_SCL2__FUNC_SCL2>; 248091cf598SEddie Huang bias-disable; 249091cf598SEddie Huang }; 250091cf598SEddie Huang }; 251091cf598SEddie Huang 252091cf598SEddie Huang i2c3_pins_a: i2c3 { 253091cf598SEddie Huang pins1 { 254091cf598SEddie Huang pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 255091cf598SEddie Huang <MT8173_PIN_107_SCL3__FUNC_SCL3>; 256091cf598SEddie Huang bias-disable; 257091cf598SEddie Huang }; 258091cf598SEddie Huang }; 259091cf598SEddie Huang 260091cf598SEddie Huang i2c4_pins_a: i2c4 { 261091cf598SEddie Huang pins1 { 262091cf598SEddie Huang pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 263091cf598SEddie Huang <MT8173_PIN_134_SCL4__FUNC_SCL4>; 264091cf598SEddie Huang bias-disable; 265091cf598SEddie Huang }; 266091cf598SEddie Huang }; 267091cf598SEddie Huang 268091cf598SEddie Huang i2c6_pins_a: i2c6 { 269091cf598SEddie Huang pins1 { 270091cf598SEddie Huang pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 271091cf598SEddie Huang <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 272091cf598SEddie Huang bias-disable; 273091cf598SEddie Huang }; 274091cf598SEddie Huang }; 2756769b93cSYingjoe Chen }; 2766769b93cSYingjoe Chen 277c010ff53SSascha Hauer scpsys: scpsys@10006000 { 278c010ff53SSascha Hauer compatible = "mediatek,mt8173-scpsys"; 279c010ff53SSascha Hauer #power-domain-cells = <1>; 280c010ff53SSascha Hauer reg = <0 0x10006000 0 0x1000>; 281c010ff53SSascha Hauer clocks = <&clk26m>, 282e34573c9SJames Liao <&topckgen CLK_TOP_MM_SEL>, 283e34573c9SJames Liao <&topckgen CLK_TOP_VENC_SEL>, 284e34573c9SJames Liao <&topckgen CLK_TOP_VENC_LT_SEL>; 285e34573c9SJames Liao clock-names = "mfg", "mm", "venc", "venc_lt"; 286c010ff53SSascha Hauer infracfg = <&infracfg>; 287c010ff53SSascha Hauer }; 288c010ff53SSascha Hauer 28913421b3eSEddie Huang watchdog: watchdog@10007000 { 29013421b3eSEddie Huang compatible = "mediatek,mt8173-wdt", 29113421b3eSEddie Huang "mediatek,mt6589-wdt"; 29213421b3eSEddie Huang reg = <0 0x10007000 0 0x100>; 29313421b3eSEddie Huang }; 29413421b3eSEddie Huang 295b2c76e27SDaniel Kurtz timer: timer@10008000 { 296b2c76e27SDaniel Kurtz compatible = "mediatek,mt8173-timer", 297b2c76e27SDaniel Kurtz "mediatek,mt6577-timer"; 298b2c76e27SDaniel Kurtz reg = <0 0x10008000 0 0x1000>; 299b2c76e27SDaniel Kurtz interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 300b2c76e27SDaniel Kurtz clocks = <&infracfg CLK_INFRA_CLK_13M>, 301b2c76e27SDaniel Kurtz <&topckgen CLK_TOP_RTC_SEL>; 302b2c76e27SDaniel Kurtz }; 303b2c76e27SDaniel Kurtz 3046cf15fc2SSascha Hauer pwrap: pwrap@1000d000 { 3056cf15fc2SSascha Hauer compatible = "mediatek,mt8173-pwrap"; 3066cf15fc2SSascha Hauer reg = <0 0x1000d000 0 0x1000>; 3076cf15fc2SSascha Hauer reg-names = "pwrap"; 3086cf15fc2SSascha Hauer interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 3096cf15fc2SSascha Hauer resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 3106cf15fc2SSascha Hauer reset-names = "pwrap"; 3116cf15fc2SSascha Hauer clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 3126cf15fc2SSascha Hauer clock-names = "spi", "wrap"; 3136cf15fc2SSascha Hauer }; 3146cf15fc2SSascha Hauer 315b3a37248SEddie Huang sysirq: intpol-controller@10200620 { 316b3a37248SEddie Huang compatible = "mediatek,mt8173-sysirq", 317b3a37248SEddie Huang "mediatek,mt6577-sysirq"; 318b3a37248SEddie Huang interrupt-controller; 319b3a37248SEddie Huang #interrupt-cells = <3>; 320b3a37248SEddie Huang interrupt-parent = <&gic>; 321b3a37248SEddie Huang reg = <0 0x10200620 0 0x20>; 322b3a37248SEddie Huang }; 323b3a37248SEddie Huang 3245ff6b3a6SYong Wu iommu: iommu@10205000 { 3255ff6b3a6SYong Wu compatible = "mediatek,mt8173-m4u"; 3265ff6b3a6SYong Wu reg = <0 0x10205000 0 0x1000>; 3275ff6b3a6SYong Wu interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 3285ff6b3a6SYong Wu clocks = <&infracfg CLK_INFRA_M4U>; 3295ff6b3a6SYong Wu clock-names = "bclk"; 3305ff6b3a6SYong Wu mediatek,larbs = <&larb0 &larb1 &larb2 3315ff6b3a6SYong Wu &larb3 &larb4 &larb5>; 3325ff6b3a6SYong Wu #iommu-cells = <1>; 3335ff6b3a6SYong Wu }; 3345ff6b3a6SYong Wu 33593e9f5eeSandrew-ct.chen@mediatek.com efuse: efuse@10206000 { 33693e9f5eeSandrew-ct.chen@mediatek.com compatible = "mediatek,mt8173-efuse"; 33793e9f5eeSandrew-ct.chen@mediatek.com reg = <0 0x10206000 0 0x1000>; 33893e9f5eeSandrew-ct.chen@mediatek.com }; 33993e9f5eeSandrew-ct.chen@mediatek.com 340f2ce7014SSascha Hauer apmixedsys: clock-controller@10209000 { 341f2ce7014SSascha Hauer compatible = "mediatek,mt8173-apmixedsys"; 342f2ce7014SSascha Hauer reg = <0 0x10209000 0 0x1000>; 343f2ce7014SSascha Hauer #clock-cells = <1>; 344f2ce7014SSascha Hauer }; 345f2ce7014SSascha Hauer 346b3a37248SEddie Huang gic: interrupt-controller@10220000 { 347b3a37248SEddie Huang compatible = "arm,gic-400"; 348b3a37248SEddie Huang #interrupt-cells = <3>; 349b3a37248SEddie Huang interrupt-parent = <&gic>; 350b3a37248SEddie Huang interrupt-controller; 351b3a37248SEddie Huang reg = <0 0x10221000 0 0x1000>, 352b3a37248SEddie Huang <0 0x10222000 0 0x2000>, 353b3a37248SEddie Huang <0 0x10224000 0 0x2000>, 354b3a37248SEddie Huang <0 0x10226000 0 0x2000>; 355b3a37248SEddie Huang interrupts = <GIC_PPI 9 356b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 357b3a37248SEddie Huang }; 358b3a37248SEddie Huang 359748c7d4dSSascha Hauer auxadc: auxadc@11001000 { 360748c7d4dSSascha Hauer compatible = "mediatek,mt8173-auxadc"; 361748c7d4dSSascha Hauer reg = <0 0x11001000 0 0x1000>; 362748c7d4dSSascha Hauer }; 363748c7d4dSSascha Hauer 364b3a37248SEddie Huang uart0: serial@11002000 { 365b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 366b3a37248SEddie Huang "mediatek,mt6577-uart"; 367b3a37248SEddie Huang reg = <0 0x11002000 0 0x400>; 368b3a37248SEddie Huang interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 3690e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 3700e84faa1SSascha Hauer clock-names = "baud", "bus"; 371b3a37248SEddie Huang status = "disabled"; 372b3a37248SEddie Huang }; 373b3a37248SEddie Huang 374b3a37248SEddie Huang uart1: serial@11003000 { 375b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 376b3a37248SEddie Huang "mediatek,mt6577-uart"; 377b3a37248SEddie Huang reg = <0 0x11003000 0 0x400>; 378b3a37248SEddie Huang interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 3790e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 3800e84faa1SSascha Hauer clock-names = "baud", "bus"; 381b3a37248SEddie Huang status = "disabled"; 382b3a37248SEddie Huang }; 383b3a37248SEddie Huang 384b3a37248SEddie Huang uart2: serial@11004000 { 385b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 386b3a37248SEddie Huang "mediatek,mt6577-uart"; 387b3a37248SEddie Huang reg = <0 0x11004000 0 0x400>; 388b3a37248SEddie Huang interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 3890e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 3900e84faa1SSascha Hauer clock-names = "baud", "bus"; 391b3a37248SEddie Huang status = "disabled"; 392b3a37248SEddie Huang }; 393b3a37248SEddie Huang 394b3a37248SEddie Huang uart3: serial@11005000 { 395b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 396b3a37248SEddie Huang "mediatek,mt6577-uart"; 397b3a37248SEddie Huang reg = <0 0x11005000 0 0x400>; 398b3a37248SEddie Huang interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 3990e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 4000e84faa1SSascha Hauer clock-names = "baud", "bus"; 401b3a37248SEddie Huang status = "disabled"; 402b3a37248SEddie Huang }; 403091cf598SEddie Huang 404091cf598SEddie Huang i2c0: i2c@11007000 { 405091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 406091cf598SEddie Huang reg = <0 0x11007000 0 0x70>, 407091cf598SEddie Huang <0 0x11000100 0 0x80>; 408091cf598SEddie Huang interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 409091cf598SEddie Huang clock-div = <16>; 410091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C0>, 411091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 412091cf598SEddie Huang clock-names = "main", "dma"; 413091cf598SEddie Huang pinctrl-names = "default"; 414091cf598SEddie Huang pinctrl-0 = <&i2c0_pins_a>; 415091cf598SEddie Huang #address-cells = <1>; 416091cf598SEddie Huang #size-cells = <0>; 417091cf598SEddie Huang status = "disabled"; 418091cf598SEddie Huang }; 419091cf598SEddie Huang 420091cf598SEddie Huang i2c1: i2c@11008000 { 421091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 422091cf598SEddie Huang reg = <0 0x11008000 0 0x70>, 423091cf598SEddie Huang <0 0x11000180 0 0x80>; 424091cf598SEddie Huang interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 425091cf598SEddie Huang clock-div = <16>; 426091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C1>, 427091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 428091cf598SEddie Huang clock-names = "main", "dma"; 429091cf598SEddie Huang pinctrl-names = "default"; 430091cf598SEddie Huang pinctrl-0 = <&i2c1_pins_a>; 431091cf598SEddie Huang #address-cells = <1>; 432091cf598SEddie Huang #size-cells = <0>; 433091cf598SEddie Huang status = "disabled"; 434091cf598SEddie Huang }; 435091cf598SEddie Huang 436091cf598SEddie Huang i2c2: i2c@11009000 { 437091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 438091cf598SEddie Huang reg = <0 0x11009000 0 0x70>, 439091cf598SEddie Huang <0 0x11000200 0 0x80>; 440091cf598SEddie Huang interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 441091cf598SEddie Huang clock-div = <16>; 442091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C2>, 443091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 444091cf598SEddie Huang clock-names = "main", "dma"; 445091cf598SEddie Huang pinctrl-names = "default"; 446091cf598SEddie Huang pinctrl-0 = <&i2c2_pins_a>; 447091cf598SEddie Huang #address-cells = <1>; 448091cf598SEddie Huang #size-cells = <0>; 449091cf598SEddie Huang status = "disabled"; 450091cf598SEddie Huang }; 451091cf598SEddie Huang 452b0c936f5SLeilk Liu spi: spi@1100a000 { 453b0c936f5SLeilk Liu compatible = "mediatek,mt8173-spi"; 454b0c936f5SLeilk Liu #address-cells = <1>; 455b0c936f5SLeilk Liu #size-cells = <0>; 456b0c936f5SLeilk Liu reg = <0 0x1100a000 0 0x1000>; 457b0c936f5SLeilk Liu interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 458b0c936f5SLeilk Liu clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 459b0c936f5SLeilk Liu <&topckgen CLK_TOP_SPI_SEL>, 460b0c936f5SLeilk Liu <&pericfg CLK_PERI_SPI0>; 461b0c936f5SLeilk Liu clock-names = "parent-clk", "sel-clk", "spi-clk"; 462b0c936f5SLeilk Liu status = "disabled"; 463b0c936f5SLeilk Liu }; 464b0c936f5SLeilk Liu 465748c7d4dSSascha Hauer thermal: thermal@1100b000 { 466748c7d4dSSascha Hauer #thermal-sensor-cells = <0>; 467748c7d4dSSascha Hauer compatible = "mediatek,mt8173-thermal"; 468748c7d4dSSascha Hauer reg = <0 0x1100b000 0 0x1000>; 469748c7d4dSSascha Hauer interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 470748c7d4dSSascha Hauer clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 471748c7d4dSSascha Hauer clock-names = "therm", "auxadc"; 472748c7d4dSSascha Hauer resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 473748c7d4dSSascha Hauer mediatek,auxadc = <&auxadc>; 474748c7d4dSSascha Hauer mediatek,apmixedsys = <&apmixedsys>; 475748c7d4dSSascha Hauer }; 476748c7d4dSSascha Hauer 47786cb8a88SBayi Cheng nor_flash: spi@1100d000 { 47886cb8a88SBayi Cheng compatible = "mediatek,mt8173-nor"; 47986cb8a88SBayi Cheng reg = <0 0x1100d000 0 0xe0>; 48086cb8a88SBayi Cheng clocks = <&pericfg CLK_PERI_SPI>, 48186cb8a88SBayi Cheng <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 48286cb8a88SBayi Cheng clock-names = "spi", "sf"; 48386cb8a88SBayi Cheng #address-cells = <1>; 48486cb8a88SBayi Cheng #size-cells = <0>; 48586cb8a88SBayi Cheng status = "disabled"; 48686cb8a88SBayi Cheng }; 48786cb8a88SBayi Cheng 4881ee35c05SYingjoe Chen i2c3: i2c@11010000 { 489091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 490091cf598SEddie Huang reg = <0 0x11010000 0 0x70>, 491091cf598SEddie Huang <0 0x11000280 0 0x80>; 492091cf598SEddie Huang interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 493091cf598SEddie Huang clock-div = <16>; 494091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C3>, 495091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 496091cf598SEddie Huang clock-names = "main", "dma"; 497091cf598SEddie Huang pinctrl-names = "default"; 498091cf598SEddie Huang pinctrl-0 = <&i2c3_pins_a>; 499091cf598SEddie Huang #address-cells = <1>; 500091cf598SEddie Huang #size-cells = <0>; 501091cf598SEddie Huang status = "disabled"; 502091cf598SEddie Huang }; 503091cf598SEddie Huang 5041ee35c05SYingjoe Chen i2c4: i2c@11011000 { 505091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 506091cf598SEddie Huang reg = <0 0x11011000 0 0x70>, 507091cf598SEddie Huang <0 0x11000300 0 0x80>; 508091cf598SEddie Huang interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 509091cf598SEddie Huang clock-div = <16>; 510091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C4>, 511091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 512091cf598SEddie Huang clock-names = "main", "dma"; 513091cf598SEddie Huang pinctrl-names = "default"; 514091cf598SEddie Huang pinctrl-0 = <&i2c4_pins_a>; 515091cf598SEddie Huang #address-cells = <1>; 516091cf598SEddie Huang #size-cells = <0>; 517091cf598SEddie Huang status = "disabled"; 518091cf598SEddie Huang }; 519091cf598SEddie Huang 5201ee35c05SYingjoe Chen i2c6: i2c@11013000 { 521091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 522091cf598SEddie Huang reg = <0 0x11013000 0 0x70>, 523091cf598SEddie Huang <0 0x11000080 0 0x80>; 524091cf598SEddie Huang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 525091cf598SEddie Huang clock-div = <16>; 526091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C6>, 527091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 528091cf598SEddie Huang clock-names = "main", "dma"; 529091cf598SEddie Huang pinctrl-names = "default"; 530091cf598SEddie Huang pinctrl-0 = <&i2c6_pins_a>; 531091cf598SEddie Huang #address-cells = <1>; 532091cf598SEddie Huang #size-cells = <0>; 533091cf598SEddie Huang status = "disabled"; 534091cf598SEddie Huang }; 535c02e0e86SKoro Chen 536c02e0e86SKoro Chen afe: audio-controller@11220000 { 537c02e0e86SKoro Chen compatible = "mediatek,mt8173-afe-pcm"; 538c02e0e86SKoro Chen reg = <0 0x11220000 0 0x1000>; 539c02e0e86SKoro Chen interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 540c02e0e86SKoro Chen power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; 541c02e0e86SKoro Chen clocks = <&infracfg CLK_INFRA_AUDIO>, 542c02e0e86SKoro Chen <&topckgen CLK_TOP_AUDIO_SEL>, 543c02e0e86SKoro Chen <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 544c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL1_DIV0>, 545c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL2_DIV0>, 546c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S0_M_SEL>, 547c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S1_M_SEL>, 548c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S2_M_SEL>, 549c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S3_M_SEL>, 550c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S3_B_SEL>; 551c02e0e86SKoro Chen clock-names = "infra_sys_audio_clk", 552c02e0e86SKoro Chen "top_pdn_audio", 553c02e0e86SKoro Chen "top_pdn_aud_intbus", 554c02e0e86SKoro Chen "bck0", 555c02e0e86SKoro Chen "bck1", 556c02e0e86SKoro Chen "i2s0_m", 557c02e0e86SKoro Chen "i2s1_m", 558c02e0e86SKoro Chen "i2s2_m", 559c02e0e86SKoro Chen "i2s3_m", 560c02e0e86SKoro Chen "i2s3_b"; 561c02e0e86SKoro Chen assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 562c02e0e86SKoro Chen <&topckgen CLK_TOP_AUD_2_SEL>; 563c02e0e86SKoro Chen assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 564c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL2>; 565c02e0e86SKoro Chen }; 5669719fa5aSEddie Huang 5679719fa5aSEddie Huang mmc0: mmc@11230000 { 5689719fa5aSEddie Huang compatible = "mediatek,mt8173-mmc", 5699719fa5aSEddie Huang "mediatek,mt8135-mmc"; 5709719fa5aSEddie Huang reg = <0 0x11230000 0 0x1000>; 5719719fa5aSEddie Huang interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 5729719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_0>, 5739719fa5aSEddie Huang <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 5749719fa5aSEddie Huang clock-names = "source", "hclk"; 5759719fa5aSEddie Huang status = "disabled"; 5769719fa5aSEddie Huang }; 5779719fa5aSEddie Huang 5789719fa5aSEddie Huang mmc1: mmc@11240000 { 5799719fa5aSEddie Huang compatible = "mediatek,mt8173-mmc", 5809719fa5aSEddie Huang "mediatek,mt8135-mmc"; 5819719fa5aSEddie Huang reg = <0 0x11240000 0 0x1000>; 5829719fa5aSEddie Huang interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 5839719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_1>, 5849719fa5aSEddie Huang <&topckgen CLK_TOP_AXI_SEL>; 5859719fa5aSEddie Huang clock-names = "source", "hclk"; 5869719fa5aSEddie Huang status = "disabled"; 5879719fa5aSEddie Huang }; 5889719fa5aSEddie Huang 5899719fa5aSEddie Huang mmc2: mmc@11250000 { 5909719fa5aSEddie Huang compatible = "mediatek,mt8173-mmc", 5919719fa5aSEddie Huang "mediatek,mt8135-mmc"; 5929719fa5aSEddie Huang reg = <0 0x11250000 0 0x1000>; 5939719fa5aSEddie Huang interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 5949719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_2>, 5959719fa5aSEddie Huang <&topckgen CLK_TOP_AXI_SEL>; 5969719fa5aSEddie Huang clock-names = "source", "hclk"; 5979719fa5aSEddie Huang status = "disabled"; 5989719fa5aSEddie Huang }; 5999719fa5aSEddie Huang 6009719fa5aSEddie Huang mmc3: mmc@11260000 { 6019719fa5aSEddie Huang compatible = "mediatek,mt8173-mmc", 6029719fa5aSEddie Huang "mediatek,mt8135-mmc"; 6039719fa5aSEddie Huang reg = <0 0x11260000 0 0x1000>; 6049719fa5aSEddie Huang interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 6059719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_3>, 6069719fa5aSEddie Huang <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 6079719fa5aSEddie Huang clock-names = "source", "hclk"; 6089719fa5aSEddie Huang status = "disabled"; 6099719fa5aSEddie Huang }; 61067e56c56SJames Liao 611bfcce47aSChunfeng Yun usb30: usb@11270000 { 612bfcce47aSChunfeng Yun compatible = "mediatek,mt8173-xhci"; 613bfcce47aSChunfeng Yun reg = <0 0x11270000 0 0x1000>, 614bfcce47aSChunfeng Yun <0 0x11280700 0 0x0100>; 615bfcce47aSChunfeng Yun interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 616bfcce47aSChunfeng Yun power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 617bfcce47aSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>, 618bfcce47aSChunfeng Yun <&pericfg CLK_PERI_USB0>, 619bfcce47aSChunfeng Yun <&pericfg CLK_PERI_USB1>; 620bfcce47aSChunfeng Yun clock-names = "sys_ck", 621bfcce47aSChunfeng Yun "wakeup_deb_p0", 622bfcce47aSChunfeng Yun "wakeup_deb_p1"; 623bfcce47aSChunfeng Yun phys = <&phy_port0 PHY_TYPE_USB3>, 624bfcce47aSChunfeng Yun <&phy_port1 PHY_TYPE_USB2>; 625bfcce47aSChunfeng Yun mediatek,syscon-wakeup = <&pericfg>; 626bfcce47aSChunfeng Yun status = "okay"; 627bfcce47aSChunfeng Yun }; 628bfcce47aSChunfeng Yun 629bfcce47aSChunfeng Yun u3phy: usb-phy@11290000 { 630bfcce47aSChunfeng Yun compatible = "mediatek,mt8173-u3phy"; 631bfcce47aSChunfeng Yun reg = <0 0x11290000 0 0x800>; 632bfcce47aSChunfeng Yun clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 633bfcce47aSChunfeng Yun clock-names = "u3phya_ref"; 634bfcce47aSChunfeng Yun #address-cells = <2>; 635bfcce47aSChunfeng Yun #size-cells = <2>; 636bfcce47aSChunfeng Yun ranges; 637bfcce47aSChunfeng Yun status = "okay"; 638bfcce47aSChunfeng Yun 639bfcce47aSChunfeng Yun phy_port0: port@11290800 { 640bfcce47aSChunfeng Yun reg = <0 0x11290800 0 0x800>; 641bfcce47aSChunfeng Yun #phy-cells = <1>; 642bfcce47aSChunfeng Yun status = "okay"; 643bfcce47aSChunfeng Yun }; 644bfcce47aSChunfeng Yun 645bfcce47aSChunfeng Yun phy_port1: port@11291000 { 646bfcce47aSChunfeng Yun reg = <0 0x11291000 0 0x800>; 647bfcce47aSChunfeng Yun #phy-cells = <1>; 648bfcce47aSChunfeng Yun status = "okay"; 649bfcce47aSChunfeng Yun }; 650bfcce47aSChunfeng Yun }; 651bfcce47aSChunfeng Yun 65267e56c56SJames Liao mmsys: clock-controller@14000000 { 65367e56c56SJames Liao compatible = "mediatek,mt8173-mmsys", "syscon"; 65467e56c56SJames Liao reg = <0 0x14000000 0 0x1000>; 65567e56c56SJames Liao #clock-cells = <1>; 65667e56c56SJames Liao }; 65767e56c56SJames Liao 65861aee934SYH Huang pwm0: pwm@1401e000 { 65961aee934SYH Huang compatible = "mediatek,mt8173-disp-pwm", 66061aee934SYH Huang "mediatek,mt6595-disp-pwm"; 66161aee934SYH Huang reg = <0 0x1401e000 0 0x1000>; 66261aee934SYH Huang #pwm-cells = <2>; 66361aee934SYH Huang clocks = <&mmsys CLK_MM_DISP_PWM026M>, 66461aee934SYH Huang <&mmsys CLK_MM_DISP_PWM0MM>; 66561aee934SYH Huang clock-names = "main", "mm"; 66661aee934SYH Huang status = "disabled"; 66761aee934SYH Huang }; 66861aee934SYH Huang 66961aee934SYH Huang pwm1: pwm@1401f000 { 67061aee934SYH Huang compatible = "mediatek,mt8173-disp-pwm", 67161aee934SYH Huang "mediatek,mt6595-disp-pwm"; 67261aee934SYH Huang reg = <0 0x1401f000 0 0x1000>; 67361aee934SYH Huang #pwm-cells = <2>; 67461aee934SYH Huang clocks = <&mmsys CLK_MM_DISP_PWM126M>, 67561aee934SYH Huang <&mmsys CLK_MM_DISP_PWM1MM>; 67661aee934SYH Huang clock-names = "main", "mm"; 67761aee934SYH Huang status = "disabled"; 67861aee934SYH Huang }; 67961aee934SYH Huang 6805ff6b3a6SYong Wu larb0: larb@14021000 { 6815ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 6825ff6b3a6SYong Wu reg = <0 0x14021000 0 0x1000>; 6835ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 6845ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 6855ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_LARB0>, 6865ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_LARB0>; 6875ff6b3a6SYong Wu clock-names = "apb", "smi"; 6885ff6b3a6SYong Wu }; 6895ff6b3a6SYong Wu 6905ff6b3a6SYong Wu smi_common: smi@14022000 { 6915ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-common"; 6925ff6b3a6SYong Wu reg = <0 0x14022000 0 0x1000>; 6935ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 6945ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_COMMON>, 6955ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_COMMON>; 6965ff6b3a6SYong Wu clock-names = "apb", "smi"; 6975ff6b3a6SYong Wu }; 6985ff6b3a6SYong Wu 6995ff6b3a6SYong Wu larb4: larb@14027000 { 7005ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 7015ff6b3a6SYong Wu reg = <0 0x14027000 0 0x1000>; 7025ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 7035ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 7045ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_LARB4>, 7055ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_LARB4>; 7065ff6b3a6SYong Wu clock-names = "apb", "smi"; 7075ff6b3a6SYong Wu }; 7085ff6b3a6SYong Wu 70967e56c56SJames Liao imgsys: clock-controller@15000000 { 71067e56c56SJames Liao compatible = "mediatek,mt8173-imgsys", "syscon"; 71167e56c56SJames Liao reg = <0 0x15000000 0 0x1000>; 71267e56c56SJames Liao #clock-cells = <1>; 71367e56c56SJames Liao }; 71467e56c56SJames Liao 7155ff6b3a6SYong Wu larb2: larb@15001000 { 7165ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 7175ff6b3a6SYong Wu reg = <0 0x15001000 0 0x1000>; 7185ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 7195ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>; 7205ff6b3a6SYong Wu clocks = <&imgsys CLK_IMG_LARB2_SMI>, 7215ff6b3a6SYong Wu <&imgsys CLK_IMG_LARB2_SMI>; 7225ff6b3a6SYong Wu clock-names = "apb", "smi"; 7235ff6b3a6SYong Wu }; 7245ff6b3a6SYong Wu 72567e56c56SJames Liao vdecsys: clock-controller@16000000 { 72667e56c56SJames Liao compatible = "mediatek,mt8173-vdecsys", "syscon"; 72767e56c56SJames Liao reg = <0 0x16000000 0 0x1000>; 72867e56c56SJames Liao #clock-cells = <1>; 72967e56c56SJames Liao }; 73067e56c56SJames Liao 7315ff6b3a6SYong Wu larb1: larb@16010000 { 7325ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 7335ff6b3a6SYong Wu reg = <0 0x16010000 0 0x1000>; 7345ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 7355ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 7365ff6b3a6SYong Wu clocks = <&vdecsys CLK_VDEC_CKEN>, 7375ff6b3a6SYong Wu <&vdecsys CLK_VDEC_LARB_CKEN>; 7385ff6b3a6SYong Wu clock-names = "apb", "smi"; 7395ff6b3a6SYong Wu }; 7405ff6b3a6SYong Wu 74167e56c56SJames Liao vencsys: clock-controller@18000000 { 74267e56c56SJames Liao compatible = "mediatek,mt8173-vencsys", "syscon"; 74367e56c56SJames Liao reg = <0 0x18000000 0 0x1000>; 74467e56c56SJames Liao #clock-cells = <1>; 74567e56c56SJames Liao }; 74667e56c56SJames Liao 7475ff6b3a6SYong Wu larb3: larb@18001000 { 7485ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 7495ff6b3a6SYong Wu reg = <0 0x18001000 0 0x1000>; 7505ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 7515ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 7525ff6b3a6SYong Wu clocks = <&vencsys CLK_VENC_CKE1>, 7535ff6b3a6SYong Wu <&vencsys CLK_VENC_CKE0>; 7545ff6b3a6SYong Wu clock-names = "apb", "smi"; 7555ff6b3a6SYong Wu }; 7565ff6b3a6SYong Wu 75767e56c56SJames Liao vencltsys: clock-controller@19000000 { 75867e56c56SJames Liao compatible = "mediatek,mt8173-vencltsys", "syscon"; 75967e56c56SJames Liao reg = <0 0x19000000 0 0x1000>; 76067e56c56SJames Liao #clock-cells = <1>; 76167e56c56SJames Liao }; 7625ff6b3a6SYong Wu 7635ff6b3a6SYong Wu larb5: larb@19001000 { 7645ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 7655ff6b3a6SYong Wu reg = <0 0x19001000 0 0x1000>; 7665ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 7675ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; 7685ff6b3a6SYong Wu clocks = <&vencltsys CLK_VENCLT_CKE1>, 7695ff6b3a6SYong Wu <&vencltsys CLK_VENCLT_CKE0>; 7705ff6b3a6SYong Wu clock-names = "apb", "smi"; 7715ff6b3a6SYong Wu }; 772b3a37248SEddie Huang }; 773b3a37248SEddie Huang}; 774b3a37248SEddie Huang 775