1b3a37248SEddie Huang/* 2b3a37248SEddie Huang * Copyright (c) 2014 MediaTek Inc. 3b3a37248SEddie Huang * Author: Eddie Huang <eddie.huang@mediatek.com> 4b3a37248SEddie Huang * 5b3a37248SEddie Huang * This program is free software; you can redistribute it and/or modify 6b3a37248SEddie Huang * it under the terms of the GNU General Public License version 2 as 7b3a37248SEddie Huang * published by the Free Software Foundation. 8b3a37248SEddie Huang * 9b3a37248SEddie Huang * This program is distributed in the hope that it will be useful, 10b3a37248SEddie Huang * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11b3a37248SEddie Huang * GNU General Public License for more details. 12b3a37248SEddie Huang */ 13b3a37248SEddie Huang 14f2ce7014SSascha Hauer#include <dt-bindings/clock/mt8173-clk.h> 15b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/irq.h> 16b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/arm-gic.h> 17bfcce47aSChunfeng Yun#include <dt-bindings/phy/phy.h> 18c02e0e86SKoro Chen#include <dt-bindings/power/mt8173-power.h> 19967313e2SPhilipp Zabel#include <dt-bindings/reset/mt8173-resets.h> 20359f9365SHongzhou Yang#include "mt8173-pinfunc.h" 21b3a37248SEddie Huang 22b3a37248SEddie Huang/ { 23b3a37248SEddie Huang compatible = "mediatek,mt8173"; 24b3a37248SEddie Huang interrupt-parent = <&sysirq>; 25b3a37248SEddie Huang #address-cells = <2>; 26b3a37248SEddie Huang #size-cells = <2>; 27b3a37248SEddie Huang 28b3a37248SEddie Huang cpus { 29b3a37248SEddie Huang #address-cells = <1>; 30b3a37248SEddie Huang #size-cells = <0>; 31b3a37248SEddie Huang 32b3a37248SEddie Huang cpu-map { 33b3a37248SEddie Huang cluster0 { 34b3a37248SEddie Huang core0 { 35b3a37248SEddie Huang cpu = <&cpu0>; 36b3a37248SEddie Huang }; 37b3a37248SEddie Huang core1 { 38b3a37248SEddie Huang cpu = <&cpu1>; 39b3a37248SEddie Huang }; 40b3a37248SEddie Huang }; 41b3a37248SEddie Huang 42b3a37248SEddie Huang cluster1 { 43b3a37248SEddie Huang core0 { 44b3a37248SEddie Huang cpu = <&cpu2>; 45b3a37248SEddie Huang }; 46b3a37248SEddie Huang core1 { 47b3a37248SEddie Huang cpu = <&cpu3>; 48b3a37248SEddie Huang }; 49b3a37248SEddie Huang }; 50b3a37248SEddie Huang }; 51b3a37248SEddie Huang 52b3a37248SEddie Huang cpu0: cpu@0 { 53b3a37248SEddie Huang device_type = "cpu"; 54b3a37248SEddie Huang compatible = "arm,cortex-a53"; 55b3a37248SEddie Huang reg = <0x000>; 56ad4df7a5SHoward Chen enable-method = "psci"; 57ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 58b3a37248SEddie Huang }; 59b3a37248SEddie Huang 60b3a37248SEddie Huang cpu1: cpu@1 { 61b3a37248SEddie Huang device_type = "cpu"; 62b3a37248SEddie Huang compatible = "arm,cortex-a53"; 63b3a37248SEddie Huang reg = <0x001>; 64b3a37248SEddie Huang enable-method = "psci"; 65ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 66b3a37248SEddie Huang }; 67b3a37248SEddie Huang 68b3a37248SEddie Huang cpu2: cpu@100 { 69b3a37248SEddie Huang device_type = "cpu"; 70b3a37248SEddie Huang compatible = "arm,cortex-a57"; 71b3a37248SEddie Huang reg = <0x100>; 72b3a37248SEddie Huang enable-method = "psci"; 73ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 74b3a37248SEddie Huang }; 75b3a37248SEddie Huang 76b3a37248SEddie Huang cpu3: cpu@101 { 77b3a37248SEddie Huang device_type = "cpu"; 78b3a37248SEddie Huang compatible = "arm,cortex-a57"; 79b3a37248SEddie Huang reg = <0x101>; 80b3a37248SEddie Huang enable-method = "psci"; 81ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 82ad4df7a5SHoward Chen }; 83ad4df7a5SHoward Chen 84ad4df7a5SHoward Chen idle-states { 85a13f18f5SLorenzo Pieralisi entry-method = "psci"; 86ad4df7a5SHoward Chen 87ad4df7a5SHoward Chen CPU_SLEEP_0: cpu-sleep-0 { 88ad4df7a5SHoward Chen compatible = "arm,idle-state"; 89ad4df7a5SHoward Chen local-timer-stop; 90ad4df7a5SHoward Chen entry-latency-us = <639>; 91ad4df7a5SHoward Chen exit-latency-us = <680>; 92ad4df7a5SHoward Chen min-residency-us = <1088>; 93ad4df7a5SHoward Chen arm,psci-suspend-param = <0x0010000>; 94ad4df7a5SHoward Chen }; 95b3a37248SEddie Huang }; 96b3a37248SEddie Huang }; 97b3a37248SEddie Huang 98b3a37248SEddie Huang psci { 9905bdabe7SFan Chen compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 100b3a37248SEddie Huang method = "smc"; 101b3a37248SEddie Huang cpu_suspend = <0x84000001>; 102b3a37248SEddie Huang cpu_off = <0x84000002>; 103b3a37248SEddie Huang cpu_on = <0x84000003>; 104b3a37248SEddie Huang }; 105b3a37248SEddie Huang 106f2ce7014SSascha Hauer clk26m: oscillator@0 { 107f2ce7014SSascha Hauer compatible = "fixed-clock"; 108f2ce7014SSascha Hauer #clock-cells = <0>; 109f2ce7014SSascha Hauer clock-frequency = <26000000>; 110f2ce7014SSascha Hauer clock-output-names = "clk26m"; 111f2ce7014SSascha Hauer }; 112f2ce7014SSascha Hauer 113f2ce7014SSascha Hauer clk32k: oscillator@1 { 114f2ce7014SSascha Hauer compatible = "fixed-clock"; 115f2ce7014SSascha Hauer #clock-cells = <0>; 116f2ce7014SSascha Hauer clock-frequency = <32000>; 117f2ce7014SSascha Hauer clock-output-names = "clk32k"; 118f2ce7014SSascha Hauer }; 119f2ce7014SSascha Hauer 12067e56c56SJames Liao cpum_ck: oscillator@2 { 12167e56c56SJames Liao compatible = "fixed-clock"; 12267e56c56SJames Liao #clock-cells = <0>; 12367e56c56SJames Liao clock-frequency = <0>; 12467e56c56SJames Liao clock-output-names = "cpum_ck"; 12567e56c56SJames Liao }; 12667e56c56SJames Liao 127b3a37248SEddie Huang timer { 128b3a37248SEddie Huang compatible = "arm,armv8-timer"; 129b3a37248SEddie Huang interrupt-parent = <&gic>; 130b3a37248SEddie Huang interrupts = <GIC_PPI 13 131b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 132b3a37248SEddie Huang <GIC_PPI 14 133b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 134b3a37248SEddie Huang <GIC_PPI 11 135b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 136b3a37248SEddie Huang <GIC_PPI 10 137b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 138b3a37248SEddie Huang }; 139b3a37248SEddie Huang 140b3a37248SEddie Huang soc { 141b3a37248SEddie Huang #address-cells = <2>; 142b3a37248SEddie Huang #size-cells = <2>; 143b3a37248SEddie Huang compatible = "simple-bus"; 144b3a37248SEddie Huang ranges; 145b3a37248SEddie Huang 146f2ce7014SSascha Hauer topckgen: clock-controller@10000000 { 147f2ce7014SSascha Hauer compatible = "mediatek,mt8173-topckgen"; 148f2ce7014SSascha Hauer reg = <0 0x10000000 0 0x1000>; 149f2ce7014SSascha Hauer #clock-cells = <1>; 150f2ce7014SSascha Hauer }; 151f2ce7014SSascha Hauer 152f2ce7014SSascha Hauer infracfg: power-controller@10001000 { 153f2ce7014SSascha Hauer compatible = "mediatek,mt8173-infracfg", "syscon"; 154f2ce7014SSascha Hauer reg = <0 0x10001000 0 0x1000>; 155f2ce7014SSascha Hauer #clock-cells = <1>; 156f2ce7014SSascha Hauer #reset-cells = <1>; 157f2ce7014SSascha Hauer }; 158f2ce7014SSascha Hauer 159f2ce7014SSascha Hauer pericfg: power-controller@10003000 { 160f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pericfg", "syscon"; 161f2ce7014SSascha Hauer reg = <0 0x10003000 0 0x1000>; 162f2ce7014SSascha Hauer #clock-cells = <1>; 163f2ce7014SSascha Hauer #reset-cells = <1>; 164f2ce7014SSascha Hauer }; 165f2ce7014SSascha Hauer 166f2ce7014SSascha Hauer syscfg_pctl_a: syscfg_pctl_a@10005000 { 167f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 168f2ce7014SSascha Hauer reg = <0 0x10005000 0 0x1000>; 169f2ce7014SSascha Hauer }; 170f2ce7014SSascha Hauer 171f2ce7014SSascha Hauer pio: pinctrl@0x10005000 { 172359f9365SHongzhou Yang compatible = "mediatek,mt8173-pinctrl"; 1736769b93cSYingjoe Chen reg = <0 0x1000b000 0 0x1000>; 174359f9365SHongzhou Yang mediatek,pctl-regmap = <&syscfg_pctl_a>; 175359f9365SHongzhou Yang pins-are-numbered; 176359f9365SHongzhou Yang gpio-controller; 177359f9365SHongzhou Yang #gpio-cells = <2>; 178359f9365SHongzhou Yang interrupt-controller; 179359f9365SHongzhou Yang #interrupt-cells = <2>; 180359f9365SHongzhou Yang interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 181359f9365SHongzhou Yang <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 182359f9365SHongzhou Yang <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 183091cf598SEddie Huang 184091cf598SEddie Huang i2c0_pins_a: i2c0 { 185091cf598SEddie Huang pins1 { 186091cf598SEddie Huang pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 187091cf598SEddie Huang <MT8173_PIN_46_SCL0__FUNC_SCL0>; 188091cf598SEddie Huang bias-disable; 189091cf598SEddie Huang }; 190359f9365SHongzhou Yang }; 191359f9365SHongzhou Yang 192091cf598SEddie Huang i2c1_pins_a: i2c1 { 193091cf598SEddie Huang pins1 { 194091cf598SEddie Huang pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 195091cf598SEddie Huang <MT8173_PIN_126_SCL1__FUNC_SCL1>; 196091cf598SEddie Huang bias-disable; 197091cf598SEddie Huang }; 198091cf598SEddie Huang }; 199091cf598SEddie Huang 200091cf598SEddie Huang i2c2_pins_a: i2c2 { 201091cf598SEddie Huang pins1 { 202091cf598SEddie Huang pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 203091cf598SEddie Huang <MT8173_PIN_44_SCL2__FUNC_SCL2>; 204091cf598SEddie Huang bias-disable; 205091cf598SEddie Huang }; 206091cf598SEddie Huang }; 207091cf598SEddie Huang 208091cf598SEddie Huang i2c3_pins_a: i2c3 { 209091cf598SEddie Huang pins1 { 210091cf598SEddie Huang pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 211091cf598SEddie Huang <MT8173_PIN_107_SCL3__FUNC_SCL3>; 212091cf598SEddie Huang bias-disable; 213091cf598SEddie Huang }; 214091cf598SEddie Huang }; 215091cf598SEddie Huang 216091cf598SEddie Huang i2c4_pins_a: i2c4 { 217091cf598SEddie Huang pins1 { 218091cf598SEddie Huang pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 219091cf598SEddie Huang <MT8173_PIN_134_SCL4__FUNC_SCL4>; 220091cf598SEddie Huang bias-disable; 221091cf598SEddie Huang }; 222091cf598SEddie Huang }; 223091cf598SEddie Huang 224091cf598SEddie Huang i2c6_pins_a: i2c6 { 225091cf598SEddie Huang pins1 { 226091cf598SEddie Huang pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 227091cf598SEddie Huang <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 228091cf598SEddie Huang bias-disable; 229091cf598SEddie Huang }; 230091cf598SEddie Huang }; 2316769b93cSYingjoe Chen }; 2326769b93cSYingjoe Chen 233c010ff53SSascha Hauer scpsys: scpsys@10006000 { 234c010ff53SSascha Hauer compatible = "mediatek,mt8173-scpsys"; 235c010ff53SSascha Hauer #power-domain-cells = <1>; 236c010ff53SSascha Hauer reg = <0 0x10006000 0 0x1000>; 237c010ff53SSascha Hauer clocks = <&clk26m>, 238e34573c9SJames Liao <&topckgen CLK_TOP_MM_SEL>, 239e34573c9SJames Liao <&topckgen CLK_TOP_VENC_SEL>, 240e34573c9SJames Liao <&topckgen CLK_TOP_VENC_LT_SEL>; 241e34573c9SJames Liao clock-names = "mfg", "mm", "venc", "venc_lt"; 242c010ff53SSascha Hauer infracfg = <&infracfg>; 243c010ff53SSascha Hauer }; 244c010ff53SSascha Hauer 24513421b3eSEddie Huang watchdog: watchdog@10007000 { 24613421b3eSEddie Huang compatible = "mediatek,mt8173-wdt", 24713421b3eSEddie Huang "mediatek,mt6589-wdt"; 24813421b3eSEddie Huang reg = <0 0x10007000 0 0x100>; 24913421b3eSEddie Huang }; 25013421b3eSEddie Huang 251b2c76e27SDaniel Kurtz timer: timer@10008000 { 252b2c76e27SDaniel Kurtz compatible = "mediatek,mt8173-timer", 253b2c76e27SDaniel Kurtz "mediatek,mt6577-timer"; 254b2c76e27SDaniel Kurtz reg = <0 0x10008000 0 0x1000>; 255b2c76e27SDaniel Kurtz interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 256b2c76e27SDaniel Kurtz clocks = <&infracfg CLK_INFRA_CLK_13M>, 257b2c76e27SDaniel Kurtz <&topckgen CLK_TOP_RTC_SEL>; 258b2c76e27SDaniel Kurtz }; 259b2c76e27SDaniel Kurtz 2606cf15fc2SSascha Hauer pwrap: pwrap@1000d000 { 2616cf15fc2SSascha Hauer compatible = "mediatek,mt8173-pwrap"; 2626cf15fc2SSascha Hauer reg = <0 0x1000d000 0 0x1000>; 2636cf15fc2SSascha Hauer reg-names = "pwrap"; 2646cf15fc2SSascha Hauer interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 2656cf15fc2SSascha Hauer resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 2666cf15fc2SSascha Hauer reset-names = "pwrap"; 2676cf15fc2SSascha Hauer clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 2686cf15fc2SSascha Hauer clock-names = "spi", "wrap"; 2696cf15fc2SSascha Hauer }; 2706cf15fc2SSascha Hauer 271b3a37248SEddie Huang sysirq: intpol-controller@10200620 { 272b3a37248SEddie Huang compatible = "mediatek,mt8173-sysirq", 273b3a37248SEddie Huang "mediatek,mt6577-sysirq"; 274b3a37248SEddie Huang interrupt-controller; 275b3a37248SEddie Huang #interrupt-cells = <3>; 276b3a37248SEddie Huang interrupt-parent = <&gic>; 277b3a37248SEddie Huang reg = <0 0x10200620 0 0x20>; 278b3a37248SEddie Huang }; 279b3a37248SEddie Huang 28093e9f5eeSandrew-ct.chen@mediatek.com efuse: efuse@10206000 { 28193e9f5eeSandrew-ct.chen@mediatek.com compatible = "mediatek,mt8173-efuse"; 28293e9f5eeSandrew-ct.chen@mediatek.com reg = <0 0x10206000 0 0x1000>; 28393e9f5eeSandrew-ct.chen@mediatek.com }; 28493e9f5eeSandrew-ct.chen@mediatek.com 285f2ce7014SSascha Hauer apmixedsys: clock-controller@10209000 { 286f2ce7014SSascha Hauer compatible = "mediatek,mt8173-apmixedsys"; 287f2ce7014SSascha Hauer reg = <0 0x10209000 0 0x1000>; 288f2ce7014SSascha Hauer #clock-cells = <1>; 289f2ce7014SSascha Hauer }; 290f2ce7014SSascha Hauer 291b3a37248SEddie Huang gic: interrupt-controller@10220000 { 292b3a37248SEddie Huang compatible = "arm,gic-400"; 293b3a37248SEddie Huang #interrupt-cells = <3>; 294b3a37248SEddie Huang interrupt-parent = <&gic>; 295b3a37248SEddie Huang interrupt-controller; 296b3a37248SEddie Huang reg = <0 0x10221000 0 0x1000>, 297b3a37248SEddie Huang <0 0x10222000 0 0x2000>, 298b3a37248SEddie Huang <0 0x10224000 0 0x2000>, 299b3a37248SEddie Huang <0 0x10226000 0 0x2000>; 300b3a37248SEddie Huang interrupts = <GIC_PPI 9 301b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 302b3a37248SEddie Huang }; 303b3a37248SEddie Huang 304b3a37248SEddie Huang uart0: serial@11002000 { 305b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 306b3a37248SEddie Huang "mediatek,mt6577-uart"; 307b3a37248SEddie Huang reg = <0 0x11002000 0 0x400>; 308b3a37248SEddie Huang interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 3090e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 3100e84faa1SSascha Hauer clock-names = "baud", "bus"; 311b3a37248SEddie Huang status = "disabled"; 312b3a37248SEddie Huang }; 313b3a37248SEddie Huang 314b3a37248SEddie Huang uart1: serial@11003000 { 315b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 316b3a37248SEddie Huang "mediatek,mt6577-uart"; 317b3a37248SEddie Huang reg = <0 0x11003000 0 0x400>; 318b3a37248SEddie Huang interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 3190e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 3200e84faa1SSascha Hauer clock-names = "baud", "bus"; 321b3a37248SEddie Huang status = "disabled"; 322b3a37248SEddie Huang }; 323b3a37248SEddie Huang 324b3a37248SEddie Huang uart2: serial@11004000 { 325b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 326b3a37248SEddie Huang "mediatek,mt6577-uart"; 327b3a37248SEddie Huang reg = <0 0x11004000 0 0x400>; 328b3a37248SEddie Huang interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 3290e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 3300e84faa1SSascha Hauer clock-names = "baud", "bus"; 331b3a37248SEddie Huang status = "disabled"; 332b3a37248SEddie Huang }; 333b3a37248SEddie Huang 334b3a37248SEddie Huang uart3: serial@11005000 { 335b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 336b3a37248SEddie Huang "mediatek,mt6577-uart"; 337b3a37248SEddie Huang reg = <0 0x11005000 0 0x400>; 338b3a37248SEddie Huang interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 3390e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 3400e84faa1SSascha Hauer clock-names = "baud", "bus"; 341b3a37248SEddie Huang status = "disabled"; 342b3a37248SEddie Huang }; 343091cf598SEddie Huang 344091cf598SEddie Huang i2c0: i2c@11007000 { 345091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 346091cf598SEddie Huang reg = <0 0x11007000 0 0x70>, 347091cf598SEddie Huang <0 0x11000100 0 0x80>; 348091cf598SEddie Huang interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 349091cf598SEddie Huang clock-div = <16>; 350091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C0>, 351091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 352091cf598SEddie Huang clock-names = "main", "dma"; 353091cf598SEddie Huang pinctrl-names = "default"; 354091cf598SEddie Huang pinctrl-0 = <&i2c0_pins_a>; 355091cf598SEddie Huang #address-cells = <1>; 356091cf598SEddie Huang #size-cells = <0>; 357091cf598SEddie Huang status = "disabled"; 358091cf598SEddie Huang }; 359091cf598SEddie Huang 360091cf598SEddie Huang i2c1: i2c@11008000 { 361091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 362091cf598SEddie Huang reg = <0 0x11008000 0 0x70>, 363091cf598SEddie Huang <0 0x11000180 0 0x80>; 364091cf598SEddie Huang interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 365091cf598SEddie Huang clock-div = <16>; 366091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C1>, 367091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 368091cf598SEddie Huang clock-names = "main", "dma"; 369091cf598SEddie Huang pinctrl-names = "default"; 370091cf598SEddie Huang pinctrl-0 = <&i2c1_pins_a>; 371091cf598SEddie Huang #address-cells = <1>; 372091cf598SEddie Huang #size-cells = <0>; 373091cf598SEddie Huang status = "disabled"; 374091cf598SEddie Huang }; 375091cf598SEddie Huang 376091cf598SEddie Huang i2c2: i2c@11009000 { 377091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 378091cf598SEddie Huang reg = <0 0x11009000 0 0x70>, 379091cf598SEddie Huang <0 0x11000200 0 0x80>; 380091cf598SEddie Huang interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 381091cf598SEddie Huang clock-div = <16>; 382091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C2>, 383091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 384091cf598SEddie Huang clock-names = "main", "dma"; 385091cf598SEddie Huang pinctrl-names = "default"; 386091cf598SEddie Huang pinctrl-0 = <&i2c2_pins_a>; 387091cf598SEddie Huang #address-cells = <1>; 388091cf598SEddie Huang #size-cells = <0>; 389091cf598SEddie Huang status = "disabled"; 390091cf598SEddie Huang }; 391091cf598SEddie Huang 392b0c936f5SLeilk Liu spi: spi@1100a000 { 393b0c936f5SLeilk Liu compatible = "mediatek,mt8173-spi"; 394b0c936f5SLeilk Liu #address-cells = <1>; 395b0c936f5SLeilk Liu #size-cells = <0>; 396b0c936f5SLeilk Liu reg = <0 0x1100a000 0 0x1000>; 397b0c936f5SLeilk Liu interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 398b0c936f5SLeilk Liu clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 399b0c936f5SLeilk Liu <&topckgen CLK_TOP_SPI_SEL>, 400b0c936f5SLeilk Liu <&pericfg CLK_PERI_SPI0>; 401b0c936f5SLeilk Liu clock-names = "parent-clk", "sel-clk", "spi-clk"; 402b0c936f5SLeilk Liu status = "disabled"; 403b0c936f5SLeilk Liu }; 404b0c936f5SLeilk Liu 40586cb8a88SBayi Cheng nor_flash: spi@1100d000 { 40686cb8a88SBayi Cheng compatible = "mediatek,mt8173-nor"; 40786cb8a88SBayi Cheng reg = <0 0x1100d000 0 0xe0>; 40886cb8a88SBayi Cheng clocks = <&pericfg CLK_PERI_SPI>, 40986cb8a88SBayi Cheng <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 41086cb8a88SBayi Cheng clock-names = "spi", "sf"; 41186cb8a88SBayi Cheng #address-cells = <1>; 41286cb8a88SBayi Cheng #size-cells = <0>; 41386cb8a88SBayi Cheng status = "disabled"; 41486cb8a88SBayi Cheng }; 41586cb8a88SBayi Cheng 4161ee35c05SYingjoe Chen i2c3: i2c@11010000 { 417091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 418091cf598SEddie Huang reg = <0 0x11010000 0 0x70>, 419091cf598SEddie Huang <0 0x11000280 0 0x80>; 420091cf598SEddie Huang interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 421091cf598SEddie Huang clock-div = <16>; 422091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C3>, 423091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 424091cf598SEddie Huang clock-names = "main", "dma"; 425091cf598SEddie Huang pinctrl-names = "default"; 426091cf598SEddie Huang pinctrl-0 = <&i2c3_pins_a>; 427091cf598SEddie Huang #address-cells = <1>; 428091cf598SEddie Huang #size-cells = <0>; 429091cf598SEddie Huang status = "disabled"; 430091cf598SEddie Huang }; 431091cf598SEddie Huang 4321ee35c05SYingjoe Chen i2c4: i2c@11011000 { 433091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 434091cf598SEddie Huang reg = <0 0x11011000 0 0x70>, 435091cf598SEddie Huang <0 0x11000300 0 0x80>; 436091cf598SEddie Huang interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 437091cf598SEddie Huang clock-div = <16>; 438091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C4>, 439091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 440091cf598SEddie Huang clock-names = "main", "dma"; 441091cf598SEddie Huang pinctrl-names = "default"; 442091cf598SEddie Huang pinctrl-0 = <&i2c4_pins_a>; 443091cf598SEddie Huang #address-cells = <1>; 444091cf598SEddie Huang #size-cells = <0>; 445091cf598SEddie Huang status = "disabled"; 446091cf598SEddie Huang }; 447091cf598SEddie Huang 4481ee35c05SYingjoe Chen i2c6: i2c@11013000 { 449091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 450091cf598SEddie Huang reg = <0 0x11013000 0 0x70>, 451091cf598SEddie Huang <0 0x11000080 0 0x80>; 452091cf598SEddie Huang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 453091cf598SEddie Huang clock-div = <16>; 454091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C6>, 455091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 456091cf598SEddie Huang clock-names = "main", "dma"; 457091cf598SEddie Huang pinctrl-names = "default"; 458091cf598SEddie Huang pinctrl-0 = <&i2c6_pins_a>; 459091cf598SEddie Huang #address-cells = <1>; 460091cf598SEddie Huang #size-cells = <0>; 461091cf598SEddie Huang status = "disabled"; 462091cf598SEddie Huang }; 463c02e0e86SKoro Chen 464c02e0e86SKoro Chen afe: audio-controller@11220000 { 465c02e0e86SKoro Chen compatible = "mediatek,mt8173-afe-pcm"; 466c02e0e86SKoro Chen reg = <0 0x11220000 0 0x1000>; 467c02e0e86SKoro Chen interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 468c02e0e86SKoro Chen power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; 469c02e0e86SKoro Chen clocks = <&infracfg CLK_INFRA_AUDIO>, 470c02e0e86SKoro Chen <&topckgen CLK_TOP_AUDIO_SEL>, 471c02e0e86SKoro Chen <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 472c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL1_DIV0>, 473c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL2_DIV0>, 474c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S0_M_SEL>, 475c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S1_M_SEL>, 476c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S2_M_SEL>, 477c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S3_M_SEL>, 478c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S3_B_SEL>; 479c02e0e86SKoro Chen clock-names = "infra_sys_audio_clk", 480c02e0e86SKoro Chen "top_pdn_audio", 481c02e0e86SKoro Chen "top_pdn_aud_intbus", 482c02e0e86SKoro Chen "bck0", 483c02e0e86SKoro Chen "bck1", 484c02e0e86SKoro Chen "i2s0_m", 485c02e0e86SKoro Chen "i2s1_m", 486c02e0e86SKoro Chen "i2s2_m", 487c02e0e86SKoro Chen "i2s3_m", 488c02e0e86SKoro Chen "i2s3_b"; 489c02e0e86SKoro Chen assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 490c02e0e86SKoro Chen <&topckgen CLK_TOP_AUD_2_SEL>; 491c02e0e86SKoro Chen assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 492c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL2>; 493c02e0e86SKoro Chen }; 4949719fa5aSEddie Huang 4959719fa5aSEddie Huang mmc0: mmc@11230000 { 4969719fa5aSEddie Huang compatible = "mediatek,mt8173-mmc", 4979719fa5aSEddie Huang "mediatek,mt8135-mmc"; 4989719fa5aSEddie Huang reg = <0 0x11230000 0 0x1000>; 4999719fa5aSEddie Huang interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 5009719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_0>, 5019719fa5aSEddie Huang <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 5029719fa5aSEddie Huang clock-names = "source", "hclk"; 5039719fa5aSEddie Huang status = "disabled"; 5049719fa5aSEddie Huang }; 5059719fa5aSEddie Huang 5069719fa5aSEddie Huang mmc1: mmc@11240000 { 5079719fa5aSEddie Huang compatible = "mediatek,mt8173-mmc", 5089719fa5aSEddie Huang "mediatek,mt8135-mmc"; 5099719fa5aSEddie Huang reg = <0 0x11240000 0 0x1000>; 5109719fa5aSEddie Huang interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 5119719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_1>, 5129719fa5aSEddie Huang <&topckgen CLK_TOP_AXI_SEL>; 5139719fa5aSEddie Huang clock-names = "source", "hclk"; 5149719fa5aSEddie Huang status = "disabled"; 5159719fa5aSEddie Huang }; 5169719fa5aSEddie Huang 5179719fa5aSEddie Huang mmc2: mmc@11250000 { 5189719fa5aSEddie Huang compatible = "mediatek,mt8173-mmc", 5199719fa5aSEddie Huang "mediatek,mt8135-mmc"; 5209719fa5aSEddie Huang reg = <0 0x11250000 0 0x1000>; 5219719fa5aSEddie Huang interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 5229719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_2>, 5239719fa5aSEddie Huang <&topckgen CLK_TOP_AXI_SEL>; 5249719fa5aSEddie Huang clock-names = "source", "hclk"; 5259719fa5aSEddie Huang status = "disabled"; 5269719fa5aSEddie Huang }; 5279719fa5aSEddie Huang 5289719fa5aSEddie Huang mmc3: mmc@11260000 { 5299719fa5aSEddie Huang compatible = "mediatek,mt8173-mmc", 5309719fa5aSEddie Huang "mediatek,mt8135-mmc"; 5319719fa5aSEddie Huang reg = <0 0x11260000 0 0x1000>; 5329719fa5aSEddie Huang interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 5339719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_3>, 5349719fa5aSEddie Huang <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 5359719fa5aSEddie Huang clock-names = "source", "hclk"; 5369719fa5aSEddie Huang status = "disabled"; 5379719fa5aSEddie Huang }; 53867e56c56SJames Liao 539bfcce47aSChunfeng Yun usb30: usb@11270000 { 540bfcce47aSChunfeng Yun compatible = "mediatek,mt8173-xhci"; 541bfcce47aSChunfeng Yun reg = <0 0x11270000 0 0x1000>, 542bfcce47aSChunfeng Yun <0 0x11280700 0 0x0100>; 543bfcce47aSChunfeng Yun interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 544bfcce47aSChunfeng Yun power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 545bfcce47aSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>, 546bfcce47aSChunfeng Yun <&pericfg CLK_PERI_USB0>, 547bfcce47aSChunfeng Yun <&pericfg CLK_PERI_USB1>; 548bfcce47aSChunfeng Yun clock-names = "sys_ck", 549bfcce47aSChunfeng Yun "wakeup_deb_p0", 550bfcce47aSChunfeng Yun "wakeup_deb_p1"; 551bfcce47aSChunfeng Yun phys = <&phy_port0 PHY_TYPE_USB3>, 552bfcce47aSChunfeng Yun <&phy_port1 PHY_TYPE_USB2>; 553bfcce47aSChunfeng Yun mediatek,syscon-wakeup = <&pericfg>; 554bfcce47aSChunfeng Yun status = "okay"; 555bfcce47aSChunfeng Yun }; 556bfcce47aSChunfeng Yun 557bfcce47aSChunfeng Yun u3phy: usb-phy@11290000 { 558bfcce47aSChunfeng Yun compatible = "mediatek,mt8173-u3phy"; 559bfcce47aSChunfeng Yun reg = <0 0x11290000 0 0x800>; 560bfcce47aSChunfeng Yun clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 561bfcce47aSChunfeng Yun clock-names = "u3phya_ref"; 562bfcce47aSChunfeng Yun #address-cells = <2>; 563bfcce47aSChunfeng Yun #size-cells = <2>; 564bfcce47aSChunfeng Yun ranges; 565bfcce47aSChunfeng Yun status = "okay"; 566bfcce47aSChunfeng Yun 567bfcce47aSChunfeng Yun phy_port0: port@11290800 { 568bfcce47aSChunfeng Yun reg = <0 0x11290800 0 0x800>; 569bfcce47aSChunfeng Yun #phy-cells = <1>; 570bfcce47aSChunfeng Yun status = "okay"; 571bfcce47aSChunfeng Yun }; 572bfcce47aSChunfeng Yun 573bfcce47aSChunfeng Yun phy_port1: port@11291000 { 574bfcce47aSChunfeng Yun reg = <0 0x11291000 0 0x800>; 575bfcce47aSChunfeng Yun #phy-cells = <1>; 576bfcce47aSChunfeng Yun status = "okay"; 577bfcce47aSChunfeng Yun }; 578bfcce47aSChunfeng Yun }; 579bfcce47aSChunfeng Yun 58067e56c56SJames Liao mmsys: clock-controller@14000000 { 58167e56c56SJames Liao compatible = "mediatek,mt8173-mmsys", "syscon"; 58267e56c56SJames Liao reg = <0 0x14000000 0 0x1000>; 58367e56c56SJames Liao #clock-cells = <1>; 58467e56c56SJames Liao }; 58567e56c56SJames Liao 58661aee934SYH Huang pwm0: pwm@1401e000 { 58761aee934SYH Huang compatible = "mediatek,mt8173-disp-pwm", 58861aee934SYH Huang "mediatek,mt6595-disp-pwm"; 58961aee934SYH Huang reg = <0 0x1401e000 0 0x1000>; 59061aee934SYH Huang #pwm-cells = <2>; 59161aee934SYH Huang clocks = <&mmsys CLK_MM_DISP_PWM026M>, 59261aee934SYH Huang <&mmsys CLK_MM_DISP_PWM0MM>; 59361aee934SYH Huang clock-names = "main", "mm"; 59461aee934SYH Huang status = "disabled"; 59561aee934SYH Huang }; 59661aee934SYH Huang 59761aee934SYH Huang pwm1: pwm@1401f000 { 59861aee934SYH Huang compatible = "mediatek,mt8173-disp-pwm", 59961aee934SYH Huang "mediatek,mt6595-disp-pwm"; 60061aee934SYH Huang reg = <0 0x1401f000 0 0x1000>; 60161aee934SYH Huang #pwm-cells = <2>; 60261aee934SYH Huang clocks = <&mmsys CLK_MM_DISP_PWM126M>, 60361aee934SYH Huang <&mmsys CLK_MM_DISP_PWM1MM>; 60461aee934SYH Huang clock-names = "main", "mm"; 60561aee934SYH Huang status = "disabled"; 60661aee934SYH Huang }; 60761aee934SYH Huang 60867e56c56SJames Liao imgsys: clock-controller@15000000 { 60967e56c56SJames Liao compatible = "mediatek,mt8173-imgsys", "syscon"; 61067e56c56SJames Liao reg = <0 0x15000000 0 0x1000>; 61167e56c56SJames Liao #clock-cells = <1>; 61267e56c56SJames Liao }; 61367e56c56SJames Liao 61467e56c56SJames Liao vdecsys: clock-controller@16000000 { 61567e56c56SJames Liao compatible = "mediatek,mt8173-vdecsys", "syscon"; 61667e56c56SJames Liao reg = <0 0x16000000 0 0x1000>; 61767e56c56SJames Liao #clock-cells = <1>; 61867e56c56SJames Liao }; 61967e56c56SJames Liao 62067e56c56SJames Liao vencsys: clock-controller@18000000 { 62167e56c56SJames Liao compatible = "mediatek,mt8173-vencsys", "syscon"; 62267e56c56SJames Liao reg = <0 0x18000000 0 0x1000>; 62367e56c56SJames Liao #clock-cells = <1>; 62467e56c56SJames Liao }; 62567e56c56SJames Liao 62667e56c56SJames Liao vencltsys: clock-controller@19000000 { 62767e56c56SJames Liao compatible = "mediatek,mt8173-vencltsys", "syscon"; 62867e56c56SJames Liao reg = <0 0x19000000 0 0x1000>; 62967e56c56SJames Liao #clock-cells = <1>; 63067e56c56SJames Liao }; 631b3a37248SEddie Huang }; 632b3a37248SEddie Huang}; 633b3a37248SEddie Huang 634