1b3a37248SEddie Huang/* 2b3a37248SEddie Huang * Copyright (c) 2014 MediaTek Inc. 3b3a37248SEddie Huang * Author: Eddie Huang <eddie.huang@mediatek.com> 4b3a37248SEddie Huang * 5b3a37248SEddie Huang * This program is free software; you can redistribute it and/or modify 6b3a37248SEddie Huang * it under the terms of the GNU General Public License version 2 as 7b3a37248SEddie Huang * published by the Free Software Foundation. 8b3a37248SEddie Huang * 9b3a37248SEddie Huang * This program is distributed in the hope that it will be useful, 10b3a37248SEddie Huang * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11b3a37248SEddie Huang * GNU General Public License for more details. 12b3a37248SEddie Huang */ 13b3a37248SEddie Huang 14f2ce7014SSascha Hauer#include <dt-bindings/clock/mt8173-clk.h> 15b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/irq.h> 16b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/arm-gic.h> 175ff6b3a6SYong Wu#include <dt-bindings/memory/mt8173-larb-port.h> 18bfcce47aSChunfeng Yun#include <dt-bindings/phy/phy.h> 19c02e0e86SKoro Chen#include <dt-bindings/power/mt8173-power.h> 20967313e2SPhilipp Zabel#include <dt-bindings/reset/mt8173-resets.h> 21359f9365SHongzhou Yang#include "mt8173-pinfunc.h" 22b3a37248SEddie Huang 23b3a37248SEddie Huang/ { 24b3a37248SEddie Huang compatible = "mediatek,mt8173"; 25b3a37248SEddie Huang interrupt-parent = <&sysirq>; 26b3a37248SEddie Huang #address-cells = <2>; 27b3a37248SEddie Huang #size-cells = <2>; 28b3a37248SEddie Huang 2981ad4dbaSCK Hu aliases { 3081ad4dbaSCK Hu ovl0 = &ovl0; 3181ad4dbaSCK Hu ovl1 = &ovl1; 3281ad4dbaSCK Hu rdma0 = &rdma0; 3381ad4dbaSCK Hu rdma1 = &rdma1; 3481ad4dbaSCK Hu rdma2 = &rdma2; 3581ad4dbaSCK Hu wdma0 = &wdma0; 3681ad4dbaSCK Hu wdma1 = &wdma1; 3781ad4dbaSCK Hu color0 = &color0; 3881ad4dbaSCK Hu color1 = &color1; 3981ad4dbaSCK Hu split0 = &split0; 4081ad4dbaSCK Hu split1 = &split1; 4181ad4dbaSCK Hu dpi0 = &dpi0; 4281ad4dbaSCK Hu dsi0 = &dsi0; 4381ad4dbaSCK Hu dsi1 = &dsi1; 4481ad4dbaSCK Hu }; 4581ad4dbaSCK Hu 46b3a37248SEddie Huang cpus { 47b3a37248SEddie Huang #address-cells = <1>; 48b3a37248SEddie Huang #size-cells = <0>; 49b3a37248SEddie Huang 50b3a37248SEddie Huang cpu-map { 51b3a37248SEddie Huang cluster0 { 52b3a37248SEddie Huang core0 { 53b3a37248SEddie Huang cpu = <&cpu0>; 54b3a37248SEddie Huang }; 55b3a37248SEddie Huang core1 { 56b3a37248SEddie Huang cpu = <&cpu1>; 57b3a37248SEddie Huang }; 58b3a37248SEddie Huang }; 59b3a37248SEddie Huang 60b3a37248SEddie Huang cluster1 { 61b3a37248SEddie Huang core0 { 62b3a37248SEddie Huang cpu = <&cpu2>; 63b3a37248SEddie Huang }; 64b3a37248SEddie Huang core1 { 65b3a37248SEddie Huang cpu = <&cpu3>; 66b3a37248SEddie Huang }; 67b3a37248SEddie Huang }; 68b3a37248SEddie Huang }; 69b3a37248SEddie Huang 70b3a37248SEddie Huang cpu0: cpu@0 { 71b3a37248SEddie Huang device_type = "cpu"; 72b3a37248SEddie Huang compatible = "arm,cortex-a53"; 73b3a37248SEddie Huang reg = <0x000>; 74ad4df7a5SHoward Chen enable-method = "psci"; 75ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 76b3a37248SEddie Huang }; 77b3a37248SEddie Huang 78b3a37248SEddie Huang cpu1: cpu@1 { 79b3a37248SEddie Huang device_type = "cpu"; 80b3a37248SEddie Huang compatible = "arm,cortex-a53"; 81b3a37248SEddie Huang reg = <0x001>; 82b3a37248SEddie Huang enable-method = "psci"; 83ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 84b3a37248SEddie Huang }; 85b3a37248SEddie Huang 86b3a37248SEddie Huang cpu2: cpu@100 { 87b3a37248SEddie Huang device_type = "cpu"; 88b3a37248SEddie Huang compatible = "arm,cortex-a57"; 89b3a37248SEddie Huang reg = <0x100>; 90b3a37248SEddie Huang enable-method = "psci"; 91ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 92b3a37248SEddie Huang }; 93b3a37248SEddie Huang 94b3a37248SEddie Huang cpu3: cpu@101 { 95b3a37248SEddie Huang device_type = "cpu"; 96b3a37248SEddie Huang compatible = "arm,cortex-a57"; 97b3a37248SEddie Huang reg = <0x101>; 98b3a37248SEddie Huang enable-method = "psci"; 99ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 100ad4df7a5SHoward Chen }; 101ad4df7a5SHoward Chen 102ad4df7a5SHoward Chen idle-states { 103a13f18f5SLorenzo Pieralisi entry-method = "psci"; 104ad4df7a5SHoward Chen 105ad4df7a5SHoward Chen CPU_SLEEP_0: cpu-sleep-0 { 106ad4df7a5SHoward Chen compatible = "arm,idle-state"; 107ad4df7a5SHoward Chen local-timer-stop; 108ad4df7a5SHoward Chen entry-latency-us = <639>; 109ad4df7a5SHoward Chen exit-latency-us = <680>; 110ad4df7a5SHoward Chen min-residency-us = <1088>; 111ad4df7a5SHoward Chen arm,psci-suspend-param = <0x0010000>; 112ad4df7a5SHoward Chen }; 113b3a37248SEddie Huang }; 114b3a37248SEddie Huang }; 115b3a37248SEddie Huang 116b3a37248SEddie Huang psci { 11705bdabe7SFan Chen compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 118b3a37248SEddie Huang method = "smc"; 119b3a37248SEddie Huang cpu_suspend = <0x84000001>; 120b3a37248SEddie Huang cpu_off = <0x84000002>; 121b3a37248SEddie Huang cpu_on = <0x84000003>; 122b3a37248SEddie Huang }; 123b3a37248SEddie Huang 124f2ce7014SSascha Hauer clk26m: oscillator@0 { 125f2ce7014SSascha Hauer compatible = "fixed-clock"; 126f2ce7014SSascha Hauer #clock-cells = <0>; 127f2ce7014SSascha Hauer clock-frequency = <26000000>; 128f2ce7014SSascha Hauer clock-output-names = "clk26m"; 129f2ce7014SSascha Hauer }; 130f2ce7014SSascha Hauer 131f2ce7014SSascha Hauer clk32k: oscillator@1 { 132f2ce7014SSascha Hauer compatible = "fixed-clock"; 133f2ce7014SSascha Hauer #clock-cells = <0>; 134f2ce7014SSascha Hauer clock-frequency = <32000>; 135f2ce7014SSascha Hauer clock-output-names = "clk32k"; 136f2ce7014SSascha Hauer }; 137f2ce7014SSascha Hauer 13867e56c56SJames Liao cpum_ck: oscillator@2 { 13967e56c56SJames Liao compatible = "fixed-clock"; 14067e56c56SJames Liao #clock-cells = <0>; 14167e56c56SJames Liao clock-frequency = <0>; 14267e56c56SJames Liao clock-output-names = "cpum_ck"; 14367e56c56SJames Liao }; 14467e56c56SJames Liao 145962f5143Sdawei.chien@mediatek.com thermal-zones { 146962f5143Sdawei.chien@mediatek.com cpu_thermal: cpu_thermal { 147962f5143Sdawei.chien@mediatek.com polling-delay-passive = <1000>; /* milliseconds */ 148962f5143Sdawei.chien@mediatek.com polling-delay = <1000>; /* milliseconds */ 149962f5143Sdawei.chien@mediatek.com 150962f5143Sdawei.chien@mediatek.com thermal-sensors = <&thermal>; 151962f5143Sdawei.chien@mediatek.com sustainable-power = <1500>; /* milliwatts */ 152962f5143Sdawei.chien@mediatek.com 153962f5143Sdawei.chien@mediatek.com trips { 154962f5143Sdawei.chien@mediatek.com threshold: trip-point@0 { 155962f5143Sdawei.chien@mediatek.com temperature = <68000>; 156962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 157962f5143Sdawei.chien@mediatek.com type = "passive"; 158962f5143Sdawei.chien@mediatek.com }; 159962f5143Sdawei.chien@mediatek.com 160962f5143Sdawei.chien@mediatek.com target: trip-point@1 { 161962f5143Sdawei.chien@mediatek.com temperature = <85000>; 162962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 163962f5143Sdawei.chien@mediatek.com type = "passive"; 164962f5143Sdawei.chien@mediatek.com }; 165962f5143Sdawei.chien@mediatek.com 166962f5143Sdawei.chien@mediatek.com cpu_crit: cpu_crit@0 { 167962f5143Sdawei.chien@mediatek.com temperature = <115000>; 168962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 169962f5143Sdawei.chien@mediatek.com type = "critical"; 170962f5143Sdawei.chien@mediatek.com }; 171962f5143Sdawei.chien@mediatek.com }; 172962f5143Sdawei.chien@mediatek.com 173962f5143Sdawei.chien@mediatek.com cooling-maps { 174962f5143Sdawei.chien@mediatek.com map@0 { 175962f5143Sdawei.chien@mediatek.com trip = <&target>; 176962f5143Sdawei.chien@mediatek.com cooling-device = <&cpu0 0 0>; 177962f5143Sdawei.chien@mediatek.com contribution = <1024>; 178962f5143Sdawei.chien@mediatek.com }; 179962f5143Sdawei.chien@mediatek.com map@1 { 180962f5143Sdawei.chien@mediatek.com trip = <&target>; 181962f5143Sdawei.chien@mediatek.com cooling-device = <&cpu2 0 0>; 182962f5143Sdawei.chien@mediatek.com contribution = <2048>; 183962f5143Sdawei.chien@mediatek.com }; 184962f5143Sdawei.chien@mediatek.com }; 185962f5143Sdawei.chien@mediatek.com }; 186962f5143Sdawei.chien@mediatek.com }; 187962f5143Sdawei.chien@mediatek.com 188b3a37248SEddie Huang timer { 189b3a37248SEddie Huang compatible = "arm,armv8-timer"; 190b3a37248SEddie Huang interrupt-parent = <&gic>; 191b3a37248SEddie Huang interrupts = <GIC_PPI 13 192b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 193b3a37248SEddie Huang <GIC_PPI 14 194b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 195b3a37248SEddie Huang <GIC_PPI 11 196b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 197b3a37248SEddie Huang <GIC_PPI 10 198b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 199b3a37248SEddie Huang }; 200b3a37248SEddie Huang 201b3a37248SEddie Huang soc { 202b3a37248SEddie Huang #address-cells = <2>; 203b3a37248SEddie Huang #size-cells = <2>; 204b3a37248SEddie Huang compatible = "simple-bus"; 205b3a37248SEddie Huang ranges; 206b3a37248SEddie Huang 207f2ce7014SSascha Hauer topckgen: clock-controller@10000000 { 208f2ce7014SSascha Hauer compatible = "mediatek,mt8173-topckgen"; 209f2ce7014SSascha Hauer reg = <0 0x10000000 0 0x1000>; 210f2ce7014SSascha Hauer #clock-cells = <1>; 211f2ce7014SSascha Hauer }; 212f2ce7014SSascha Hauer 213f2ce7014SSascha Hauer infracfg: power-controller@10001000 { 214f2ce7014SSascha Hauer compatible = "mediatek,mt8173-infracfg", "syscon"; 215f2ce7014SSascha Hauer reg = <0 0x10001000 0 0x1000>; 216f2ce7014SSascha Hauer #clock-cells = <1>; 217f2ce7014SSascha Hauer #reset-cells = <1>; 218f2ce7014SSascha Hauer }; 219f2ce7014SSascha Hauer 220f2ce7014SSascha Hauer pericfg: power-controller@10003000 { 221f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pericfg", "syscon"; 222f2ce7014SSascha Hauer reg = <0 0x10003000 0 0x1000>; 223f2ce7014SSascha Hauer #clock-cells = <1>; 224f2ce7014SSascha Hauer #reset-cells = <1>; 225f2ce7014SSascha Hauer }; 226f2ce7014SSascha Hauer 227f2ce7014SSascha Hauer syscfg_pctl_a: syscfg_pctl_a@10005000 { 228f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 229f2ce7014SSascha Hauer reg = <0 0x10005000 0 0x1000>; 230f2ce7014SSascha Hauer }; 231f2ce7014SSascha Hauer 232f2ce7014SSascha Hauer pio: pinctrl@0x10005000 { 233359f9365SHongzhou Yang compatible = "mediatek,mt8173-pinctrl"; 2346769b93cSYingjoe Chen reg = <0 0x1000b000 0 0x1000>; 235359f9365SHongzhou Yang mediatek,pctl-regmap = <&syscfg_pctl_a>; 236359f9365SHongzhou Yang pins-are-numbered; 237359f9365SHongzhou Yang gpio-controller; 238359f9365SHongzhou Yang #gpio-cells = <2>; 239359f9365SHongzhou Yang interrupt-controller; 240359f9365SHongzhou Yang #interrupt-cells = <2>; 241359f9365SHongzhou Yang interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 242359f9365SHongzhou Yang <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 243359f9365SHongzhou Yang <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 244091cf598SEddie Huang 245091cf598SEddie Huang i2c0_pins_a: i2c0 { 246091cf598SEddie Huang pins1 { 247091cf598SEddie Huang pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 248091cf598SEddie Huang <MT8173_PIN_46_SCL0__FUNC_SCL0>; 249091cf598SEddie Huang bias-disable; 250091cf598SEddie Huang }; 251359f9365SHongzhou Yang }; 252359f9365SHongzhou Yang 253091cf598SEddie Huang i2c1_pins_a: i2c1 { 254091cf598SEddie Huang pins1 { 255091cf598SEddie Huang pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 256091cf598SEddie Huang <MT8173_PIN_126_SCL1__FUNC_SCL1>; 257091cf598SEddie Huang bias-disable; 258091cf598SEddie Huang }; 259091cf598SEddie Huang }; 260091cf598SEddie Huang 261091cf598SEddie Huang i2c2_pins_a: i2c2 { 262091cf598SEddie Huang pins1 { 263091cf598SEddie Huang pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 264091cf598SEddie Huang <MT8173_PIN_44_SCL2__FUNC_SCL2>; 265091cf598SEddie Huang bias-disable; 266091cf598SEddie Huang }; 267091cf598SEddie Huang }; 268091cf598SEddie Huang 269091cf598SEddie Huang i2c3_pins_a: i2c3 { 270091cf598SEddie Huang pins1 { 271091cf598SEddie Huang pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 272091cf598SEddie Huang <MT8173_PIN_107_SCL3__FUNC_SCL3>; 273091cf598SEddie Huang bias-disable; 274091cf598SEddie Huang }; 275091cf598SEddie Huang }; 276091cf598SEddie Huang 277091cf598SEddie Huang i2c4_pins_a: i2c4 { 278091cf598SEddie Huang pins1 { 279091cf598SEddie Huang pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 280091cf598SEddie Huang <MT8173_PIN_134_SCL4__FUNC_SCL4>; 281091cf598SEddie Huang bias-disable; 282091cf598SEddie Huang }; 283091cf598SEddie Huang }; 284091cf598SEddie Huang 285091cf598SEddie Huang i2c6_pins_a: i2c6 { 286091cf598SEddie Huang pins1 { 287091cf598SEddie Huang pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 288091cf598SEddie Huang <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 289091cf598SEddie Huang bias-disable; 290091cf598SEddie Huang }; 291091cf598SEddie Huang }; 2926769b93cSYingjoe Chen }; 2936769b93cSYingjoe Chen 294c010ff53SSascha Hauer scpsys: scpsys@10006000 { 295c010ff53SSascha Hauer compatible = "mediatek,mt8173-scpsys"; 296c010ff53SSascha Hauer #power-domain-cells = <1>; 297c010ff53SSascha Hauer reg = <0 0x10006000 0 0x1000>; 298c010ff53SSascha Hauer clocks = <&clk26m>, 299e34573c9SJames Liao <&topckgen CLK_TOP_MM_SEL>, 300e34573c9SJames Liao <&topckgen CLK_TOP_VENC_SEL>, 301e34573c9SJames Liao <&topckgen CLK_TOP_VENC_LT_SEL>; 302e34573c9SJames Liao clock-names = "mfg", "mm", "venc", "venc_lt"; 303c010ff53SSascha Hauer infracfg = <&infracfg>; 304c010ff53SSascha Hauer }; 305c010ff53SSascha Hauer 30613421b3eSEddie Huang watchdog: watchdog@10007000 { 30713421b3eSEddie Huang compatible = "mediatek,mt8173-wdt", 30813421b3eSEddie Huang "mediatek,mt6589-wdt"; 30913421b3eSEddie Huang reg = <0 0x10007000 0 0x100>; 31013421b3eSEddie Huang }; 31113421b3eSEddie Huang 312b2c76e27SDaniel Kurtz timer: timer@10008000 { 313b2c76e27SDaniel Kurtz compatible = "mediatek,mt8173-timer", 314b2c76e27SDaniel Kurtz "mediatek,mt6577-timer"; 315b2c76e27SDaniel Kurtz reg = <0 0x10008000 0 0x1000>; 316b2c76e27SDaniel Kurtz interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 317b2c76e27SDaniel Kurtz clocks = <&infracfg CLK_INFRA_CLK_13M>, 318b2c76e27SDaniel Kurtz <&topckgen CLK_TOP_RTC_SEL>; 319b2c76e27SDaniel Kurtz }; 320b2c76e27SDaniel Kurtz 3216cf15fc2SSascha Hauer pwrap: pwrap@1000d000 { 3226cf15fc2SSascha Hauer compatible = "mediatek,mt8173-pwrap"; 3236cf15fc2SSascha Hauer reg = <0 0x1000d000 0 0x1000>; 3246cf15fc2SSascha Hauer reg-names = "pwrap"; 3256cf15fc2SSascha Hauer interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 3266cf15fc2SSascha Hauer resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 3276cf15fc2SSascha Hauer reset-names = "pwrap"; 3286cf15fc2SSascha Hauer clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 3296cf15fc2SSascha Hauer clock-names = "spi", "wrap"; 3306cf15fc2SSascha Hauer }; 3316cf15fc2SSascha Hauer 332b3a37248SEddie Huang sysirq: intpol-controller@10200620 { 333b3a37248SEddie Huang compatible = "mediatek,mt8173-sysirq", 334b3a37248SEddie Huang "mediatek,mt6577-sysirq"; 335b3a37248SEddie Huang interrupt-controller; 336b3a37248SEddie Huang #interrupt-cells = <3>; 337b3a37248SEddie Huang interrupt-parent = <&gic>; 338b3a37248SEddie Huang reg = <0 0x10200620 0 0x20>; 339b3a37248SEddie Huang }; 340b3a37248SEddie Huang 3415ff6b3a6SYong Wu iommu: iommu@10205000 { 3425ff6b3a6SYong Wu compatible = "mediatek,mt8173-m4u"; 3435ff6b3a6SYong Wu reg = <0 0x10205000 0 0x1000>; 3445ff6b3a6SYong Wu interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 3455ff6b3a6SYong Wu clocks = <&infracfg CLK_INFRA_M4U>; 3465ff6b3a6SYong Wu clock-names = "bclk"; 3475ff6b3a6SYong Wu mediatek,larbs = <&larb0 &larb1 &larb2 3485ff6b3a6SYong Wu &larb3 &larb4 &larb5>; 3495ff6b3a6SYong Wu #iommu-cells = <1>; 3505ff6b3a6SYong Wu }; 3515ff6b3a6SYong Wu 35293e9f5eeSandrew-ct.chen@mediatek.com efuse: efuse@10206000 { 35393e9f5eeSandrew-ct.chen@mediatek.com compatible = "mediatek,mt8173-efuse"; 35493e9f5eeSandrew-ct.chen@mediatek.com reg = <0 0x10206000 0 0x1000>; 35593e9f5eeSandrew-ct.chen@mediatek.com }; 35693e9f5eeSandrew-ct.chen@mediatek.com 357f2ce7014SSascha Hauer apmixedsys: clock-controller@10209000 { 358f2ce7014SSascha Hauer compatible = "mediatek,mt8173-apmixedsys"; 359f2ce7014SSascha Hauer reg = <0 0x10209000 0 0x1000>; 360f2ce7014SSascha Hauer #clock-cells = <1>; 361f2ce7014SSascha Hauer }; 362f2ce7014SSascha Hauer 36381ad4dbaSCK Hu mipi_tx0: mipi-dphy@10215000 { 36481ad4dbaSCK Hu compatible = "mediatek,mt8173-mipi-tx"; 36581ad4dbaSCK Hu reg = <0 0x10215000 0 0x1000>; 36681ad4dbaSCK Hu clocks = <&clk26m>; 36781ad4dbaSCK Hu clock-output-names = "mipi_tx0_pll"; 36881ad4dbaSCK Hu #clock-cells = <0>; 36981ad4dbaSCK Hu #phy-cells = <0>; 37081ad4dbaSCK Hu status = "disabled"; 37181ad4dbaSCK Hu }; 37281ad4dbaSCK Hu 37381ad4dbaSCK Hu mipi_tx1: mipi-dphy@10216000 { 37481ad4dbaSCK Hu compatible = "mediatek,mt8173-mipi-tx"; 37581ad4dbaSCK Hu reg = <0 0x10216000 0 0x1000>; 37681ad4dbaSCK Hu clocks = <&clk26m>; 37781ad4dbaSCK Hu clock-output-names = "mipi_tx1_pll"; 37881ad4dbaSCK Hu #clock-cells = <0>; 37981ad4dbaSCK Hu #phy-cells = <0>; 38081ad4dbaSCK Hu status = "disabled"; 38181ad4dbaSCK Hu }; 38281ad4dbaSCK Hu 383b3a37248SEddie Huang gic: interrupt-controller@10220000 { 384b3a37248SEddie Huang compatible = "arm,gic-400"; 385b3a37248SEddie Huang #interrupt-cells = <3>; 386b3a37248SEddie Huang interrupt-parent = <&gic>; 387b3a37248SEddie Huang interrupt-controller; 388b3a37248SEddie Huang reg = <0 0x10221000 0 0x1000>, 389b3a37248SEddie Huang <0 0x10222000 0 0x2000>, 390b3a37248SEddie Huang <0 0x10224000 0 0x2000>, 391b3a37248SEddie Huang <0 0x10226000 0 0x2000>; 392b3a37248SEddie Huang interrupts = <GIC_PPI 9 393b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 394b3a37248SEddie Huang }; 395b3a37248SEddie Huang 396748c7d4dSSascha Hauer auxadc: auxadc@11001000 { 397748c7d4dSSascha Hauer compatible = "mediatek,mt8173-auxadc"; 398748c7d4dSSascha Hauer reg = <0 0x11001000 0 0x1000>; 399748c7d4dSSascha Hauer }; 400748c7d4dSSascha Hauer 401b3a37248SEddie Huang uart0: serial@11002000 { 402b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 403b3a37248SEddie Huang "mediatek,mt6577-uart"; 404b3a37248SEddie Huang reg = <0 0x11002000 0 0x400>; 405b3a37248SEddie Huang interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 4060e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 4070e84faa1SSascha Hauer clock-names = "baud", "bus"; 408b3a37248SEddie Huang status = "disabled"; 409b3a37248SEddie Huang }; 410b3a37248SEddie Huang 411b3a37248SEddie Huang uart1: serial@11003000 { 412b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 413b3a37248SEddie Huang "mediatek,mt6577-uart"; 414b3a37248SEddie Huang reg = <0 0x11003000 0 0x400>; 415b3a37248SEddie Huang interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 4160e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 4170e84faa1SSascha Hauer clock-names = "baud", "bus"; 418b3a37248SEddie Huang status = "disabled"; 419b3a37248SEddie Huang }; 420b3a37248SEddie Huang 421b3a37248SEddie Huang uart2: serial@11004000 { 422b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 423b3a37248SEddie Huang "mediatek,mt6577-uart"; 424b3a37248SEddie Huang reg = <0 0x11004000 0 0x400>; 425b3a37248SEddie Huang interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 4260e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 4270e84faa1SSascha Hauer clock-names = "baud", "bus"; 428b3a37248SEddie Huang status = "disabled"; 429b3a37248SEddie Huang }; 430b3a37248SEddie Huang 431b3a37248SEddie Huang uart3: serial@11005000 { 432b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 433b3a37248SEddie Huang "mediatek,mt6577-uart"; 434b3a37248SEddie Huang reg = <0 0x11005000 0 0x400>; 435b3a37248SEddie Huang interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 4360e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 4370e84faa1SSascha Hauer clock-names = "baud", "bus"; 438b3a37248SEddie Huang status = "disabled"; 439b3a37248SEddie Huang }; 440091cf598SEddie Huang 441091cf598SEddie Huang i2c0: i2c@11007000 { 442091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 443091cf598SEddie Huang reg = <0 0x11007000 0 0x70>, 444091cf598SEddie Huang <0 0x11000100 0 0x80>; 445091cf598SEddie Huang interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 446091cf598SEddie Huang clock-div = <16>; 447091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C0>, 448091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 449091cf598SEddie Huang clock-names = "main", "dma"; 450091cf598SEddie Huang pinctrl-names = "default"; 451091cf598SEddie Huang pinctrl-0 = <&i2c0_pins_a>; 452091cf598SEddie Huang #address-cells = <1>; 453091cf598SEddie Huang #size-cells = <0>; 454091cf598SEddie Huang status = "disabled"; 455091cf598SEddie Huang }; 456091cf598SEddie Huang 457091cf598SEddie Huang i2c1: i2c@11008000 { 458091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 459091cf598SEddie Huang reg = <0 0x11008000 0 0x70>, 460091cf598SEddie Huang <0 0x11000180 0 0x80>; 461091cf598SEddie Huang interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 462091cf598SEddie Huang clock-div = <16>; 463091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C1>, 464091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 465091cf598SEddie Huang clock-names = "main", "dma"; 466091cf598SEddie Huang pinctrl-names = "default"; 467091cf598SEddie Huang pinctrl-0 = <&i2c1_pins_a>; 468091cf598SEddie Huang #address-cells = <1>; 469091cf598SEddie Huang #size-cells = <0>; 470091cf598SEddie Huang status = "disabled"; 471091cf598SEddie Huang }; 472091cf598SEddie Huang 473091cf598SEddie Huang i2c2: i2c@11009000 { 474091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 475091cf598SEddie Huang reg = <0 0x11009000 0 0x70>, 476091cf598SEddie Huang <0 0x11000200 0 0x80>; 477091cf598SEddie Huang interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 478091cf598SEddie Huang clock-div = <16>; 479091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C2>, 480091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 481091cf598SEddie Huang clock-names = "main", "dma"; 482091cf598SEddie Huang pinctrl-names = "default"; 483091cf598SEddie Huang pinctrl-0 = <&i2c2_pins_a>; 484091cf598SEddie Huang #address-cells = <1>; 485091cf598SEddie Huang #size-cells = <0>; 486091cf598SEddie Huang status = "disabled"; 487091cf598SEddie Huang }; 488091cf598SEddie Huang 489b0c936f5SLeilk Liu spi: spi@1100a000 { 490b0c936f5SLeilk Liu compatible = "mediatek,mt8173-spi"; 491b0c936f5SLeilk Liu #address-cells = <1>; 492b0c936f5SLeilk Liu #size-cells = <0>; 493b0c936f5SLeilk Liu reg = <0 0x1100a000 0 0x1000>; 494b0c936f5SLeilk Liu interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 495b0c936f5SLeilk Liu clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 496b0c936f5SLeilk Liu <&topckgen CLK_TOP_SPI_SEL>, 497b0c936f5SLeilk Liu <&pericfg CLK_PERI_SPI0>; 498b0c936f5SLeilk Liu clock-names = "parent-clk", "sel-clk", "spi-clk"; 499b0c936f5SLeilk Liu status = "disabled"; 500b0c936f5SLeilk Liu }; 501b0c936f5SLeilk Liu 502748c7d4dSSascha Hauer thermal: thermal@1100b000 { 503748c7d4dSSascha Hauer #thermal-sensor-cells = <0>; 504748c7d4dSSascha Hauer compatible = "mediatek,mt8173-thermal"; 505748c7d4dSSascha Hauer reg = <0 0x1100b000 0 0x1000>; 506748c7d4dSSascha Hauer interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 507748c7d4dSSascha Hauer clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 508748c7d4dSSascha Hauer clock-names = "therm", "auxadc"; 509748c7d4dSSascha Hauer resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 510748c7d4dSSascha Hauer mediatek,auxadc = <&auxadc>; 511748c7d4dSSascha Hauer mediatek,apmixedsys = <&apmixedsys>; 512748c7d4dSSascha Hauer }; 513748c7d4dSSascha Hauer 51486cb8a88SBayi Cheng nor_flash: spi@1100d000 { 51586cb8a88SBayi Cheng compatible = "mediatek,mt8173-nor"; 51686cb8a88SBayi Cheng reg = <0 0x1100d000 0 0xe0>; 51786cb8a88SBayi Cheng clocks = <&pericfg CLK_PERI_SPI>, 51886cb8a88SBayi Cheng <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 51986cb8a88SBayi Cheng clock-names = "spi", "sf"; 52086cb8a88SBayi Cheng #address-cells = <1>; 52186cb8a88SBayi Cheng #size-cells = <0>; 52286cb8a88SBayi Cheng status = "disabled"; 52386cb8a88SBayi Cheng }; 52486cb8a88SBayi Cheng 5251ee35c05SYingjoe Chen i2c3: i2c@11010000 { 526091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 527091cf598SEddie Huang reg = <0 0x11010000 0 0x70>, 528091cf598SEddie Huang <0 0x11000280 0 0x80>; 529091cf598SEddie Huang interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 530091cf598SEddie Huang clock-div = <16>; 531091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C3>, 532091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 533091cf598SEddie Huang clock-names = "main", "dma"; 534091cf598SEddie Huang pinctrl-names = "default"; 535091cf598SEddie Huang pinctrl-0 = <&i2c3_pins_a>; 536091cf598SEddie Huang #address-cells = <1>; 537091cf598SEddie Huang #size-cells = <0>; 538091cf598SEddie Huang status = "disabled"; 539091cf598SEddie Huang }; 540091cf598SEddie Huang 5411ee35c05SYingjoe Chen i2c4: i2c@11011000 { 542091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 543091cf598SEddie Huang reg = <0 0x11011000 0 0x70>, 544091cf598SEddie Huang <0 0x11000300 0 0x80>; 545091cf598SEddie Huang interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 546091cf598SEddie Huang clock-div = <16>; 547091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C4>, 548091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 549091cf598SEddie Huang clock-names = "main", "dma"; 550091cf598SEddie Huang pinctrl-names = "default"; 551091cf598SEddie Huang pinctrl-0 = <&i2c4_pins_a>; 552091cf598SEddie Huang #address-cells = <1>; 553091cf598SEddie Huang #size-cells = <0>; 554091cf598SEddie Huang status = "disabled"; 555091cf598SEddie Huang }; 556091cf598SEddie Huang 5571ee35c05SYingjoe Chen i2c6: i2c@11013000 { 558091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 559091cf598SEddie Huang reg = <0 0x11013000 0 0x70>, 560091cf598SEddie Huang <0 0x11000080 0 0x80>; 561091cf598SEddie Huang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 562091cf598SEddie Huang clock-div = <16>; 563091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C6>, 564091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 565091cf598SEddie Huang clock-names = "main", "dma"; 566091cf598SEddie Huang pinctrl-names = "default"; 567091cf598SEddie Huang pinctrl-0 = <&i2c6_pins_a>; 568091cf598SEddie Huang #address-cells = <1>; 569091cf598SEddie Huang #size-cells = <0>; 570091cf598SEddie Huang status = "disabled"; 571091cf598SEddie Huang }; 572c02e0e86SKoro Chen 573c02e0e86SKoro Chen afe: audio-controller@11220000 { 574c02e0e86SKoro Chen compatible = "mediatek,mt8173-afe-pcm"; 575c02e0e86SKoro Chen reg = <0 0x11220000 0 0x1000>; 576c02e0e86SKoro Chen interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 577c02e0e86SKoro Chen power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; 578c02e0e86SKoro Chen clocks = <&infracfg CLK_INFRA_AUDIO>, 579c02e0e86SKoro Chen <&topckgen CLK_TOP_AUDIO_SEL>, 580c02e0e86SKoro Chen <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 581c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL1_DIV0>, 582c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL2_DIV0>, 583c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S0_M_SEL>, 584c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S1_M_SEL>, 585c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S2_M_SEL>, 586c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S3_M_SEL>, 587c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S3_B_SEL>; 588c02e0e86SKoro Chen clock-names = "infra_sys_audio_clk", 589c02e0e86SKoro Chen "top_pdn_audio", 590c02e0e86SKoro Chen "top_pdn_aud_intbus", 591c02e0e86SKoro Chen "bck0", 592c02e0e86SKoro Chen "bck1", 593c02e0e86SKoro Chen "i2s0_m", 594c02e0e86SKoro Chen "i2s1_m", 595c02e0e86SKoro Chen "i2s2_m", 596c02e0e86SKoro Chen "i2s3_m", 597c02e0e86SKoro Chen "i2s3_b"; 598c02e0e86SKoro Chen assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 599c02e0e86SKoro Chen <&topckgen CLK_TOP_AUD_2_SEL>; 600c02e0e86SKoro Chen assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 601c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL2>; 602c02e0e86SKoro Chen }; 6039719fa5aSEddie Huang 6049719fa5aSEddie Huang mmc0: mmc@11230000 { 6059719fa5aSEddie Huang compatible = "mediatek,mt8173-mmc", 6069719fa5aSEddie Huang "mediatek,mt8135-mmc"; 6079719fa5aSEddie Huang reg = <0 0x11230000 0 0x1000>; 6089719fa5aSEddie Huang interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 6099719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_0>, 6109719fa5aSEddie Huang <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 6119719fa5aSEddie Huang clock-names = "source", "hclk"; 6129719fa5aSEddie Huang status = "disabled"; 6139719fa5aSEddie Huang }; 6149719fa5aSEddie Huang 6159719fa5aSEddie Huang mmc1: mmc@11240000 { 6169719fa5aSEddie Huang compatible = "mediatek,mt8173-mmc", 6179719fa5aSEddie Huang "mediatek,mt8135-mmc"; 6189719fa5aSEddie Huang reg = <0 0x11240000 0 0x1000>; 6199719fa5aSEddie Huang interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 6209719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_1>, 6219719fa5aSEddie Huang <&topckgen CLK_TOP_AXI_SEL>; 6229719fa5aSEddie Huang clock-names = "source", "hclk"; 6239719fa5aSEddie Huang status = "disabled"; 6249719fa5aSEddie Huang }; 6259719fa5aSEddie Huang 6269719fa5aSEddie Huang mmc2: mmc@11250000 { 6279719fa5aSEddie Huang compatible = "mediatek,mt8173-mmc", 6289719fa5aSEddie Huang "mediatek,mt8135-mmc"; 6299719fa5aSEddie Huang reg = <0 0x11250000 0 0x1000>; 6309719fa5aSEddie Huang interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 6319719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_2>, 6329719fa5aSEddie Huang <&topckgen CLK_TOP_AXI_SEL>; 6339719fa5aSEddie Huang clock-names = "source", "hclk"; 6349719fa5aSEddie Huang status = "disabled"; 6359719fa5aSEddie Huang }; 6369719fa5aSEddie Huang 6379719fa5aSEddie Huang mmc3: mmc@11260000 { 6389719fa5aSEddie Huang compatible = "mediatek,mt8173-mmc", 6399719fa5aSEddie Huang "mediatek,mt8135-mmc"; 6409719fa5aSEddie Huang reg = <0 0x11260000 0 0x1000>; 6419719fa5aSEddie Huang interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 6429719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_3>, 6439719fa5aSEddie Huang <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 6449719fa5aSEddie Huang clock-names = "source", "hclk"; 6459719fa5aSEddie Huang status = "disabled"; 6469719fa5aSEddie Huang }; 64767e56c56SJames Liao 648bfcce47aSChunfeng Yun usb30: usb@11270000 { 649bfcce47aSChunfeng Yun compatible = "mediatek,mt8173-xhci"; 650bfcce47aSChunfeng Yun reg = <0 0x11270000 0 0x1000>, 651bfcce47aSChunfeng Yun <0 0x11280700 0 0x0100>; 652bfcce47aSChunfeng Yun interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 653bfcce47aSChunfeng Yun power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 654bfcce47aSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>, 655bfcce47aSChunfeng Yun <&pericfg CLK_PERI_USB0>, 656bfcce47aSChunfeng Yun <&pericfg CLK_PERI_USB1>; 657bfcce47aSChunfeng Yun clock-names = "sys_ck", 658bfcce47aSChunfeng Yun "wakeup_deb_p0", 659bfcce47aSChunfeng Yun "wakeup_deb_p1"; 660bfcce47aSChunfeng Yun phys = <&phy_port0 PHY_TYPE_USB3>, 661bfcce47aSChunfeng Yun <&phy_port1 PHY_TYPE_USB2>; 662bfcce47aSChunfeng Yun mediatek,syscon-wakeup = <&pericfg>; 663bfcce47aSChunfeng Yun status = "okay"; 664bfcce47aSChunfeng Yun }; 665bfcce47aSChunfeng Yun 666bfcce47aSChunfeng Yun u3phy: usb-phy@11290000 { 667bfcce47aSChunfeng Yun compatible = "mediatek,mt8173-u3phy"; 668bfcce47aSChunfeng Yun reg = <0 0x11290000 0 0x800>; 669bfcce47aSChunfeng Yun clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 670bfcce47aSChunfeng Yun clock-names = "u3phya_ref"; 671bfcce47aSChunfeng Yun #address-cells = <2>; 672bfcce47aSChunfeng Yun #size-cells = <2>; 673bfcce47aSChunfeng Yun ranges; 674bfcce47aSChunfeng Yun status = "okay"; 675bfcce47aSChunfeng Yun 676bfcce47aSChunfeng Yun phy_port0: port@11290800 { 677bfcce47aSChunfeng Yun reg = <0 0x11290800 0 0x800>; 678bfcce47aSChunfeng Yun #phy-cells = <1>; 679bfcce47aSChunfeng Yun status = "okay"; 680bfcce47aSChunfeng Yun }; 681bfcce47aSChunfeng Yun 682bfcce47aSChunfeng Yun phy_port1: port@11291000 { 683bfcce47aSChunfeng Yun reg = <0 0x11291000 0 0x800>; 684bfcce47aSChunfeng Yun #phy-cells = <1>; 685bfcce47aSChunfeng Yun status = "okay"; 686bfcce47aSChunfeng Yun }; 687bfcce47aSChunfeng Yun }; 688bfcce47aSChunfeng Yun 68967e56c56SJames Liao mmsys: clock-controller@14000000 { 69067e56c56SJames Liao compatible = "mediatek,mt8173-mmsys", "syscon"; 69167e56c56SJames Liao reg = <0 0x14000000 0 0x1000>; 69281ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 69367e56c56SJames Liao #clock-cells = <1>; 69467e56c56SJames Liao }; 69567e56c56SJames Liao 69681ad4dbaSCK Hu ovl0: ovl@1400c000 { 69781ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-ovl"; 69881ad4dbaSCK Hu reg = <0 0x1400c000 0 0x1000>; 69981ad4dbaSCK Hu interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 70081ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 70181ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_OVL0>; 70281ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_OVL0>; 70381ad4dbaSCK Hu mediatek,larb = <&larb0>; 70481ad4dbaSCK Hu }; 70581ad4dbaSCK Hu 70681ad4dbaSCK Hu ovl1: ovl@1400d000 { 70781ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-ovl"; 70881ad4dbaSCK Hu reg = <0 0x1400d000 0 0x1000>; 70981ad4dbaSCK Hu interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; 71081ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 71181ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_OVL1>; 71281ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_OVL1>; 71381ad4dbaSCK Hu mediatek,larb = <&larb4>; 71481ad4dbaSCK Hu }; 71581ad4dbaSCK Hu 71681ad4dbaSCK Hu rdma0: rdma@1400e000 { 71781ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-rdma"; 71881ad4dbaSCK Hu reg = <0 0x1400e000 0 0x1000>; 71981ad4dbaSCK Hu interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 72081ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 72181ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_RDMA0>; 72281ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_RDMA0>; 72381ad4dbaSCK Hu mediatek,larb = <&larb0>; 72481ad4dbaSCK Hu }; 72581ad4dbaSCK Hu 72681ad4dbaSCK Hu rdma1: rdma@1400f000 { 72781ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-rdma"; 72881ad4dbaSCK Hu reg = <0 0x1400f000 0 0x1000>; 72981ad4dbaSCK Hu interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; 73081ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 73181ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_RDMA1>; 73281ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_RDMA1>; 73381ad4dbaSCK Hu mediatek,larb = <&larb4>; 73481ad4dbaSCK Hu }; 73581ad4dbaSCK Hu 73681ad4dbaSCK Hu rdma2: rdma@14010000 { 73781ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-rdma"; 73881ad4dbaSCK Hu reg = <0 0x14010000 0 0x1000>; 73981ad4dbaSCK Hu interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; 74081ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 74181ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_RDMA2>; 74281ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_RDMA2>; 74381ad4dbaSCK Hu mediatek,larb = <&larb4>; 74481ad4dbaSCK Hu }; 74581ad4dbaSCK Hu 74681ad4dbaSCK Hu wdma0: wdma@14011000 { 74781ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-wdma"; 74881ad4dbaSCK Hu reg = <0 0x14011000 0 0x1000>; 74981ad4dbaSCK Hu interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 75081ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 75181ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_WDMA0>; 75281ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_WDMA0>; 75381ad4dbaSCK Hu mediatek,larb = <&larb0>; 75481ad4dbaSCK Hu }; 75581ad4dbaSCK Hu 75681ad4dbaSCK Hu wdma1: wdma@14012000 { 75781ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-wdma"; 75881ad4dbaSCK Hu reg = <0 0x14012000 0 0x1000>; 75981ad4dbaSCK Hu interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; 76081ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 76181ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_WDMA1>; 76281ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_WDMA1>; 76381ad4dbaSCK Hu mediatek,larb = <&larb4>; 76481ad4dbaSCK Hu }; 76581ad4dbaSCK Hu 76681ad4dbaSCK Hu color0: color@14013000 { 76781ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-color"; 76881ad4dbaSCK Hu reg = <0 0x14013000 0 0x1000>; 76981ad4dbaSCK Hu interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; 77081ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 77181ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_COLOR0>; 77281ad4dbaSCK Hu }; 77381ad4dbaSCK Hu 77481ad4dbaSCK Hu color1: color@14014000 { 77581ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-color"; 77681ad4dbaSCK Hu reg = <0 0x14014000 0 0x1000>; 77781ad4dbaSCK Hu interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 77881ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 77981ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_COLOR1>; 78081ad4dbaSCK Hu }; 78181ad4dbaSCK Hu 78281ad4dbaSCK Hu aal@14015000 { 78381ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-aal"; 78481ad4dbaSCK Hu reg = <0 0x14015000 0 0x1000>; 78581ad4dbaSCK Hu interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 78681ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 78781ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_AAL>; 78881ad4dbaSCK Hu }; 78981ad4dbaSCK Hu 79081ad4dbaSCK Hu gamma@14016000 { 79181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-gamma"; 79281ad4dbaSCK Hu reg = <0 0x14016000 0 0x1000>; 79381ad4dbaSCK Hu interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 79481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 79581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_GAMMA>; 79681ad4dbaSCK Hu }; 79781ad4dbaSCK Hu 79881ad4dbaSCK Hu merge@14017000 { 79981ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-merge"; 80081ad4dbaSCK Hu reg = <0 0x14017000 0 0x1000>; 80181ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 80281ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_MERGE>; 80381ad4dbaSCK Hu }; 80481ad4dbaSCK Hu 80581ad4dbaSCK Hu split0: split@14018000 { 80681ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-split"; 80781ad4dbaSCK Hu reg = <0 0x14018000 0 0x1000>; 80881ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 80981ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_SPLIT0>; 81081ad4dbaSCK Hu }; 81181ad4dbaSCK Hu 81281ad4dbaSCK Hu split1: split@14019000 { 81381ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-split"; 81481ad4dbaSCK Hu reg = <0 0x14019000 0 0x1000>; 81581ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 81681ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_SPLIT1>; 81781ad4dbaSCK Hu }; 81881ad4dbaSCK Hu 81981ad4dbaSCK Hu ufoe@1401a000 { 82081ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-ufoe"; 82181ad4dbaSCK Hu reg = <0 0x1401a000 0 0x1000>; 82281ad4dbaSCK Hu interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 82381ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 82481ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_UFOE>; 82581ad4dbaSCK Hu }; 82681ad4dbaSCK Hu 82781ad4dbaSCK Hu dsi0: dsi@1401b000 { 82881ad4dbaSCK Hu compatible = "mediatek,mt8173-dsi"; 82981ad4dbaSCK Hu reg = <0 0x1401b000 0 0x1000>; 83081ad4dbaSCK Hu interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 83181ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 83281ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DSI0_ENGINE>, 83381ad4dbaSCK Hu <&mmsys CLK_MM_DSI0_DIGITAL>, 83481ad4dbaSCK Hu <&mipi_tx0>; 83581ad4dbaSCK Hu clock-names = "engine", "digital", "hs"; 83681ad4dbaSCK Hu phys = <&mipi_tx0>; 83781ad4dbaSCK Hu phy-names = "dphy"; 83881ad4dbaSCK Hu status = "disabled"; 83981ad4dbaSCK Hu }; 84081ad4dbaSCK Hu 84181ad4dbaSCK Hu dsi1: dsi@1401c000 { 84281ad4dbaSCK Hu compatible = "mediatek,mt8173-dsi"; 84381ad4dbaSCK Hu reg = <0 0x1401c000 0 0x1000>; 84481ad4dbaSCK Hu interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 84581ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 84681ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DSI1_ENGINE>, 84781ad4dbaSCK Hu <&mmsys CLK_MM_DSI1_DIGITAL>, 84881ad4dbaSCK Hu <&mipi_tx1>; 84981ad4dbaSCK Hu clock-names = "engine", "digital", "hs"; 85081ad4dbaSCK Hu phy = <&mipi_tx1>; 85181ad4dbaSCK Hu phy-names = "dphy"; 85281ad4dbaSCK Hu status = "disabled"; 85381ad4dbaSCK Hu }; 85481ad4dbaSCK Hu 85581ad4dbaSCK Hu dpi0: dpi@1401d000 { 85681ad4dbaSCK Hu compatible = "mediatek,mt8173-dpi"; 85781ad4dbaSCK Hu reg = <0 0x1401d000 0 0x1000>; 85881ad4dbaSCK Hu interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 85981ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 86081ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DPI_PIXEL>, 86181ad4dbaSCK Hu <&mmsys CLK_MM_DPI_ENGINE>, 86281ad4dbaSCK Hu <&apmixedsys CLK_APMIXED_TVDPLL>; 86381ad4dbaSCK Hu clock-names = "pixel", "engine", "pll"; 86481ad4dbaSCK Hu status = "disabled"; 86581ad4dbaSCK Hu }; 86681ad4dbaSCK Hu 86761aee934SYH Huang pwm0: pwm@1401e000 { 86861aee934SYH Huang compatible = "mediatek,mt8173-disp-pwm", 86961aee934SYH Huang "mediatek,mt6595-disp-pwm"; 87061aee934SYH Huang reg = <0 0x1401e000 0 0x1000>; 87161aee934SYH Huang #pwm-cells = <2>; 87261aee934SYH Huang clocks = <&mmsys CLK_MM_DISP_PWM026M>, 87361aee934SYH Huang <&mmsys CLK_MM_DISP_PWM0MM>; 87461aee934SYH Huang clock-names = "main", "mm"; 87561aee934SYH Huang status = "disabled"; 87661aee934SYH Huang }; 87761aee934SYH Huang 87861aee934SYH Huang pwm1: pwm@1401f000 { 87961aee934SYH Huang compatible = "mediatek,mt8173-disp-pwm", 88061aee934SYH Huang "mediatek,mt6595-disp-pwm"; 88161aee934SYH Huang reg = <0 0x1401f000 0 0x1000>; 88261aee934SYH Huang #pwm-cells = <2>; 88361aee934SYH Huang clocks = <&mmsys CLK_MM_DISP_PWM126M>, 88461aee934SYH Huang <&mmsys CLK_MM_DISP_PWM1MM>; 88561aee934SYH Huang clock-names = "main", "mm"; 88661aee934SYH Huang status = "disabled"; 88761aee934SYH Huang }; 88861aee934SYH Huang 88981ad4dbaSCK Hu mutex: mutex@14020000 { 89081ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-mutex"; 89181ad4dbaSCK Hu reg = <0 0x14020000 0 0x1000>; 89281ad4dbaSCK Hu interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 89381ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 89481ad4dbaSCK Hu clocks = <&mmsys CLK_MM_MUTEX_32K>; 89581ad4dbaSCK Hu }; 89681ad4dbaSCK Hu 8975ff6b3a6SYong Wu larb0: larb@14021000 { 8985ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 8995ff6b3a6SYong Wu reg = <0 0x14021000 0 0x1000>; 9005ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 9015ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 9025ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_LARB0>, 9035ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_LARB0>; 9045ff6b3a6SYong Wu clock-names = "apb", "smi"; 9055ff6b3a6SYong Wu }; 9065ff6b3a6SYong Wu 9075ff6b3a6SYong Wu smi_common: smi@14022000 { 9085ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-common"; 9095ff6b3a6SYong Wu reg = <0 0x14022000 0 0x1000>; 9105ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 9115ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_COMMON>, 9125ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_COMMON>; 9135ff6b3a6SYong Wu clock-names = "apb", "smi"; 9145ff6b3a6SYong Wu }; 9155ff6b3a6SYong Wu 91681ad4dbaSCK Hu od@14023000 { 91781ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-od"; 91881ad4dbaSCK Hu reg = <0 0x14023000 0 0x1000>; 91981ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_OD>; 92081ad4dbaSCK Hu }; 92181ad4dbaSCK Hu 9225ff6b3a6SYong Wu larb4: larb@14027000 { 9235ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 9245ff6b3a6SYong Wu reg = <0 0x14027000 0 0x1000>; 9255ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 9265ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 9275ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_LARB4>, 9285ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_LARB4>; 9295ff6b3a6SYong Wu clock-names = "apb", "smi"; 9305ff6b3a6SYong Wu }; 9315ff6b3a6SYong Wu 93267e56c56SJames Liao imgsys: clock-controller@15000000 { 93367e56c56SJames Liao compatible = "mediatek,mt8173-imgsys", "syscon"; 93467e56c56SJames Liao reg = <0 0x15000000 0 0x1000>; 93567e56c56SJames Liao #clock-cells = <1>; 93667e56c56SJames Liao }; 93767e56c56SJames Liao 9385ff6b3a6SYong Wu larb2: larb@15001000 { 9395ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 9405ff6b3a6SYong Wu reg = <0 0x15001000 0 0x1000>; 9415ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 9425ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>; 9435ff6b3a6SYong Wu clocks = <&imgsys CLK_IMG_LARB2_SMI>, 9445ff6b3a6SYong Wu <&imgsys CLK_IMG_LARB2_SMI>; 9455ff6b3a6SYong Wu clock-names = "apb", "smi"; 9465ff6b3a6SYong Wu }; 9475ff6b3a6SYong Wu 94867e56c56SJames Liao vdecsys: clock-controller@16000000 { 94967e56c56SJames Liao compatible = "mediatek,mt8173-vdecsys", "syscon"; 95067e56c56SJames Liao reg = <0 0x16000000 0 0x1000>; 95167e56c56SJames Liao #clock-cells = <1>; 95267e56c56SJames Liao }; 95367e56c56SJames Liao 9545ff6b3a6SYong Wu larb1: larb@16010000 { 9555ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 9565ff6b3a6SYong Wu reg = <0 0x16010000 0 0x1000>; 9575ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 9585ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 9595ff6b3a6SYong Wu clocks = <&vdecsys CLK_VDEC_CKEN>, 9605ff6b3a6SYong Wu <&vdecsys CLK_VDEC_LARB_CKEN>; 9615ff6b3a6SYong Wu clock-names = "apb", "smi"; 9625ff6b3a6SYong Wu }; 9635ff6b3a6SYong Wu 96467e56c56SJames Liao vencsys: clock-controller@18000000 { 96567e56c56SJames Liao compatible = "mediatek,mt8173-vencsys", "syscon"; 96667e56c56SJames Liao reg = <0 0x18000000 0 0x1000>; 96767e56c56SJames Liao #clock-cells = <1>; 96867e56c56SJames Liao }; 96967e56c56SJames Liao 9705ff6b3a6SYong Wu larb3: larb@18001000 { 9715ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 9725ff6b3a6SYong Wu reg = <0 0x18001000 0 0x1000>; 9735ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 9745ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 9755ff6b3a6SYong Wu clocks = <&vencsys CLK_VENC_CKE1>, 9765ff6b3a6SYong Wu <&vencsys CLK_VENC_CKE0>; 9775ff6b3a6SYong Wu clock-names = "apb", "smi"; 9785ff6b3a6SYong Wu }; 9795ff6b3a6SYong Wu 98067e56c56SJames Liao vencltsys: clock-controller@19000000 { 98167e56c56SJames Liao compatible = "mediatek,mt8173-vencltsys", "syscon"; 98267e56c56SJames Liao reg = <0 0x19000000 0 0x1000>; 98367e56c56SJames Liao #clock-cells = <1>; 98467e56c56SJames Liao }; 9855ff6b3a6SYong Wu 9865ff6b3a6SYong Wu larb5: larb@19001000 { 9875ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 9885ff6b3a6SYong Wu reg = <0 0x19001000 0 0x1000>; 9895ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 9905ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; 9915ff6b3a6SYong Wu clocks = <&vencltsys CLK_VENCLT_CKE1>, 9925ff6b3a6SYong Wu <&vencltsys CLK_VENCLT_CKE0>; 9935ff6b3a6SYong Wu clock-names = "apb", "smi"; 9945ff6b3a6SYong Wu }; 995b3a37248SEddie Huang }; 996b3a37248SEddie Huang}; 997b3a37248SEddie Huang 998