1b3a37248SEddie Huang/* 2b3a37248SEddie Huang * Copyright (c) 2014 MediaTek Inc. 3b3a37248SEddie Huang * Author: Eddie Huang <eddie.huang@mediatek.com> 4b3a37248SEddie Huang * 5b3a37248SEddie Huang * This program is free software; you can redistribute it and/or modify 6b3a37248SEddie Huang * it under the terms of the GNU General Public License version 2 as 7b3a37248SEddie Huang * published by the Free Software Foundation. 8b3a37248SEddie Huang * 9b3a37248SEddie Huang * This program is distributed in the hope that it will be useful, 10b3a37248SEddie Huang * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11b3a37248SEddie Huang * GNU General Public License for more details. 12b3a37248SEddie Huang */ 13b3a37248SEddie Huang 14f2ce7014SSascha Hauer#include <dt-bindings/clock/mt8173-clk.h> 15b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/irq.h> 16b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/arm-gic.h> 175ff6b3a6SYong Wu#include <dt-bindings/memory/mt8173-larb-port.h> 18bfcce47aSChunfeng Yun#include <dt-bindings/phy/phy.h> 19c02e0e86SKoro Chen#include <dt-bindings/power/mt8173-power.h> 20967313e2SPhilipp Zabel#include <dt-bindings/reset/mt8173-resets.h> 21359f9365SHongzhou Yang#include "mt8173-pinfunc.h" 22b3a37248SEddie Huang 23b3a37248SEddie Huang/ { 24b3a37248SEddie Huang compatible = "mediatek,mt8173"; 25b3a37248SEddie Huang interrupt-parent = <&sysirq>; 26b3a37248SEddie Huang #address-cells = <2>; 27b3a37248SEddie Huang #size-cells = <2>; 28b3a37248SEddie Huang 29b3a37248SEddie Huang cpus { 30b3a37248SEddie Huang #address-cells = <1>; 31b3a37248SEddie Huang #size-cells = <0>; 32b3a37248SEddie Huang 33b3a37248SEddie Huang cpu-map { 34b3a37248SEddie Huang cluster0 { 35b3a37248SEddie Huang core0 { 36b3a37248SEddie Huang cpu = <&cpu0>; 37b3a37248SEddie Huang }; 38b3a37248SEddie Huang core1 { 39b3a37248SEddie Huang cpu = <&cpu1>; 40b3a37248SEddie Huang }; 41b3a37248SEddie Huang }; 42b3a37248SEddie Huang 43b3a37248SEddie Huang cluster1 { 44b3a37248SEddie Huang core0 { 45b3a37248SEddie Huang cpu = <&cpu2>; 46b3a37248SEddie Huang }; 47b3a37248SEddie Huang core1 { 48b3a37248SEddie Huang cpu = <&cpu3>; 49b3a37248SEddie Huang }; 50b3a37248SEddie Huang }; 51b3a37248SEddie Huang }; 52b3a37248SEddie Huang 53b3a37248SEddie Huang cpu0: cpu@0 { 54b3a37248SEddie Huang device_type = "cpu"; 55b3a37248SEddie Huang compatible = "arm,cortex-a53"; 56b3a37248SEddie Huang reg = <0x000>; 57ad4df7a5SHoward Chen enable-method = "psci"; 58ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 59b3a37248SEddie Huang }; 60b3a37248SEddie Huang 61b3a37248SEddie Huang cpu1: cpu@1 { 62b3a37248SEddie Huang device_type = "cpu"; 63b3a37248SEddie Huang compatible = "arm,cortex-a53"; 64b3a37248SEddie Huang reg = <0x001>; 65b3a37248SEddie Huang enable-method = "psci"; 66ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 67b3a37248SEddie Huang }; 68b3a37248SEddie Huang 69b3a37248SEddie Huang cpu2: cpu@100 { 70b3a37248SEddie Huang device_type = "cpu"; 71b3a37248SEddie Huang compatible = "arm,cortex-a57"; 72b3a37248SEddie Huang reg = <0x100>; 73b3a37248SEddie Huang enable-method = "psci"; 74ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 75b3a37248SEddie Huang }; 76b3a37248SEddie Huang 77b3a37248SEddie Huang cpu3: cpu@101 { 78b3a37248SEddie Huang device_type = "cpu"; 79b3a37248SEddie Huang compatible = "arm,cortex-a57"; 80b3a37248SEddie Huang reg = <0x101>; 81b3a37248SEddie Huang enable-method = "psci"; 82ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 83ad4df7a5SHoward Chen }; 84ad4df7a5SHoward Chen 85ad4df7a5SHoward Chen idle-states { 86a13f18f5SLorenzo Pieralisi entry-method = "psci"; 87ad4df7a5SHoward Chen 88ad4df7a5SHoward Chen CPU_SLEEP_0: cpu-sleep-0 { 89ad4df7a5SHoward Chen compatible = "arm,idle-state"; 90ad4df7a5SHoward Chen local-timer-stop; 91ad4df7a5SHoward Chen entry-latency-us = <639>; 92ad4df7a5SHoward Chen exit-latency-us = <680>; 93ad4df7a5SHoward Chen min-residency-us = <1088>; 94ad4df7a5SHoward Chen arm,psci-suspend-param = <0x0010000>; 95ad4df7a5SHoward Chen }; 96b3a37248SEddie Huang }; 97b3a37248SEddie Huang }; 98b3a37248SEddie Huang 99b3a37248SEddie Huang psci { 10005bdabe7SFan Chen compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 101b3a37248SEddie Huang method = "smc"; 102b3a37248SEddie Huang cpu_suspend = <0x84000001>; 103b3a37248SEddie Huang cpu_off = <0x84000002>; 104b3a37248SEddie Huang cpu_on = <0x84000003>; 105b3a37248SEddie Huang }; 106b3a37248SEddie Huang 107f2ce7014SSascha Hauer clk26m: oscillator@0 { 108f2ce7014SSascha Hauer compatible = "fixed-clock"; 109f2ce7014SSascha Hauer #clock-cells = <0>; 110f2ce7014SSascha Hauer clock-frequency = <26000000>; 111f2ce7014SSascha Hauer clock-output-names = "clk26m"; 112f2ce7014SSascha Hauer }; 113f2ce7014SSascha Hauer 114f2ce7014SSascha Hauer clk32k: oscillator@1 { 115f2ce7014SSascha Hauer compatible = "fixed-clock"; 116f2ce7014SSascha Hauer #clock-cells = <0>; 117f2ce7014SSascha Hauer clock-frequency = <32000>; 118f2ce7014SSascha Hauer clock-output-names = "clk32k"; 119f2ce7014SSascha Hauer }; 120f2ce7014SSascha Hauer 12167e56c56SJames Liao cpum_ck: oscillator@2 { 12267e56c56SJames Liao compatible = "fixed-clock"; 12367e56c56SJames Liao #clock-cells = <0>; 12467e56c56SJames Liao clock-frequency = <0>; 12567e56c56SJames Liao clock-output-names = "cpum_ck"; 12667e56c56SJames Liao }; 12767e56c56SJames Liao 128b3a37248SEddie Huang timer { 129b3a37248SEddie Huang compatible = "arm,armv8-timer"; 130b3a37248SEddie Huang interrupt-parent = <&gic>; 131b3a37248SEddie Huang interrupts = <GIC_PPI 13 132b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 133b3a37248SEddie Huang <GIC_PPI 14 134b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 135b3a37248SEddie Huang <GIC_PPI 11 136b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 137b3a37248SEddie Huang <GIC_PPI 10 138b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 139b3a37248SEddie Huang }; 140b3a37248SEddie Huang 141b3a37248SEddie Huang soc { 142b3a37248SEddie Huang #address-cells = <2>; 143b3a37248SEddie Huang #size-cells = <2>; 144b3a37248SEddie Huang compatible = "simple-bus"; 145b3a37248SEddie Huang ranges; 146b3a37248SEddie Huang 147f2ce7014SSascha Hauer topckgen: clock-controller@10000000 { 148f2ce7014SSascha Hauer compatible = "mediatek,mt8173-topckgen"; 149f2ce7014SSascha Hauer reg = <0 0x10000000 0 0x1000>; 150f2ce7014SSascha Hauer #clock-cells = <1>; 151f2ce7014SSascha Hauer }; 152f2ce7014SSascha Hauer 153f2ce7014SSascha Hauer infracfg: power-controller@10001000 { 154f2ce7014SSascha Hauer compatible = "mediatek,mt8173-infracfg", "syscon"; 155f2ce7014SSascha Hauer reg = <0 0x10001000 0 0x1000>; 156f2ce7014SSascha Hauer #clock-cells = <1>; 157f2ce7014SSascha Hauer #reset-cells = <1>; 158f2ce7014SSascha Hauer }; 159f2ce7014SSascha Hauer 160f2ce7014SSascha Hauer pericfg: power-controller@10003000 { 161f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pericfg", "syscon"; 162f2ce7014SSascha Hauer reg = <0 0x10003000 0 0x1000>; 163f2ce7014SSascha Hauer #clock-cells = <1>; 164f2ce7014SSascha Hauer #reset-cells = <1>; 165f2ce7014SSascha Hauer }; 166f2ce7014SSascha Hauer 167f2ce7014SSascha Hauer syscfg_pctl_a: syscfg_pctl_a@10005000 { 168f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 169f2ce7014SSascha Hauer reg = <0 0x10005000 0 0x1000>; 170f2ce7014SSascha Hauer }; 171f2ce7014SSascha Hauer 172f2ce7014SSascha Hauer pio: pinctrl@0x10005000 { 173359f9365SHongzhou Yang compatible = "mediatek,mt8173-pinctrl"; 1746769b93cSYingjoe Chen reg = <0 0x1000b000 0 0x1000>; 175359f9365SHongzhou Yang mediatek,pctl-regmap = <&syscfg_pctl_a>; 176359f9365SHongzhou Yang pins-are-numbered; 177359f9365SHongzhou Yang gpio-controller; 178359f9365SHongzhou Yang #gpio-cells = <2>; 179359f9365SHongzhou Yang interrupt-controller; 180359f9365SHongzhou Yang #interrupt-cells = <2>; 181359f9365SHongzhou Yang interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 182359f9365SHongzhou Yang <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 183359f9365SHongzhou Yang <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 184091cf598SEddie Huang 185091cf598SEddie Huang i2c0_pins_a: i2c0 { 186091cf598SEddie Huang pins1 { 187091cf598SEddie Huang pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 188091cf598SEddie Huang <MT8173_PIN_46_SCL0__FUNC_SCL0>; 189091cf598SEddie Huang bias-disable; 190091cf598SEddie Huang }; 191359f9365SHongzhou Yang }; 192359f9365SHongzhou Yang 193091cf598SEddie Huang i2c1_pins_a: i2c1 { 194091cf598SEddie Huang pins1 { 195091cf598SEddie Huang pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 196091cf598SEddie Huang <MT8173_PIN_126_SCL1__FUNC_SCL1>; 197091cf598SEddie Huang bias-disable; 198091cf598SEddie Huang }; 199091cf598SEddie Huang }; 200091cf598SEddie Huang 201091cf598SEddie Huang i2c2_pins_a: i2c2 { 202091cf598SEddie Huang pins1 { 203091cf598SEddie Huang pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 204091cf598SEddie Huang <MT8173_PIN_44_SCL2__FUNC_SCL2>; 205091cf598SEddie Huang bias-disable; 206091cf598SEddie Huang }; 207091cf598SEddie Huang }; 208091cf598SEddie Huang 209091cf598SEddie Huang i2c3_pins_a: i2c3 { 210091cf598SEddie Huang pins1 { 211091cf598SEddie Huang pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 212091cf598SEddie Huang <MT8173_PIN_107_SCL3__FUNC_SCL3>; 213091cf598SEddie Huang bias-disable; 214091cf598SEddie Huang }; 215091cf598SEddie Huang }; 216091cf598SEddie Huang 217091cf598SEddie Huang i2c4_pins_a: i2c4 { 218091cf598SEddie Huang pins1 { 219091cf598SEddie Huang pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 220091cf598SEddie Huang <MT8173_PIN_134_SCL4__FUNC_SCL4>; 221091cf598SEddie Huang bias-disable; 222091cf598SEddie Huang }; 223091cf598SEddie Huang }; 224091cf598SEddie Huang 225091cf598SEddie Huang i2c6_pins_a: i2c6 { 226091cf598SEddie Huang pins1 { 227091cf598SEddie Huang pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 228091cf598SEddie Huang <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 229091cf598SEddie Huang bias-disable; 230091cf598SEddie Huang }; 231091cf598SEddie Huang }; 2326769b93cSYingjoe Chen }; 2336769b93cSYingjoe Chen 234c010ff53SSascha Hauer scpsys: scpsys@10006000 { 235c010ff53SSascha Hauer compatible = "mediatek,mt8173-scpsys"; 236c010ff53SSascha Hauer #power-domain-cells = <1>; 237c010ff53SSascha Hauer reg = <0 0x10006000 0 0x1000>; 238c010ff53SSascha Hauer clocks = <&clk26m>, 239e34573c9SJames Liao <&topckgen CLK_TOP_MM_SEL>, 240e34573c9SJames Liao <&topckgen CLK_TOP_VENC_SEL>, 241e34573c9SJames Liao <&topckgen CLK_TOP_VENC_LT_SEL>; 242e34573c9SJames Liao clock-names = "mfg", "mm", "venc", "venc_lt"; 243c010ff53SSascha Hauer infracfg = <&infracfg>; 244c010ff53SSascha Hauer }; 245c010ff53SSascha Hauer 24613421b3eSEddie Huang watchdog: watchdog@10007000 { 24713421b3eSEddie Huang compatible = "mediatek,mt8173-wdt", 24813421b3eSEddie Huang "mediatek,mt6589-wdt"; 24913421b3eSEddie Huang reg = <0 0x10007000 0 0x100>; 25013421b3eSEddie Huang }; 25113421b3eSEddie Huang 252b2c76e27SDaniel Kurtz timer: timer@10008000 { 253b2c76e27SDaniel Kurtz compatible = "mediatek,mt8173-timer", 254b2c76e27SDaniel Kurtz "mediatek,mt6577-timer"; 255b2c76e27SDaniel Kurtz reg = <0 0x10008000 0 0x1000>; 256b2c76e27SDaniel Kurtz interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 257b2c76e27SDaniel Kurtz clocks = <&infracfg CLK_INFRA_CLK_13M>, 258b2c76e27SDaniel Kurtz <&topckgen CLK_TOP_RTC_SEL>; 259b2c76e27SDaniel Kurtz }; 260b2c76e27SDaniel Kurtz 2616cf15fc2SSascha Hauer pwrap: pwrap@1000d000 { 2626cf15fc2SSascha Hauer compatible = "mediatek,mt8173-pwrap"; 2636cf15fc2SSascha Hauer reg = <0 0x1000d000 0 0x1000>; 2646cf15fc2SSascha Hauer reg-names = "pwrap"; 2656cf15fc2SSascha Hauer interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 2666cf15fc2SSascha Hauer resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 2676cf15fc2SSascha Hauer reset-names = "pwrap"; 2686cf15fc2SSascha Hauer clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 2696cf15fc2SSascha Hauer clock-names = "spi", "wrap"; 2706cf15fc2SSascha Hauer }; 2716cf15fc2SSascha Hauer 272b3a37248SEddie Huang sysirq: intpol-controller@10200620 { 273b3a37248SEddie Huang compatible = "mediatek,mt8173-sysirq", 274b3a37248SEddie Huang "mediatek,mt6577-sysirq"; 275b3a37248SEddie Huang interrupt-controller; 276b3a37248SEddie Huang #interrupt-cells = <3>; 277b3a37248SEddie Huang interrupt-parent = <&gic>; 278b3a37248SEddie Huang reg = <0 0x10200620 0 0x20>; 279b3a37248SEddie Huang }; 280b3a37248SEddie Huang 2815ff6b3a6SYong Wu iommu: iommu@10205000 { 2825ff6b3a6SYong Wu compatible = "mediatek,mt8173-m4u"; 2835ff6b3a6SYong Wu reg = <0 0x10205000 0 0x1000>; 2845ff6b3a6SYong Wu interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 2855ff6b3a6SYong Wu clocks = <&infracfg CLK_INFRA_M4U>; 2865ff6b3a6SYong Wu clock-names = "bclk"; 2875ff6b3a6SYong Wu mediatek,larbs = <&larb0 &larb1 &larb2 2885ff6b3a6SYong Wu &larb3 &larb4 &larb5>; 2895ff6b3a6SYong Wu #iommu-cells = <1>; 2905ff6b3a6SYong Wu }; 2915ff6b3a6SYong Wu 29293e9f5eeSandrew-ct.chen@mediatek.com efuse: efuse@10206000 { 29393e9f5eeSandrew-ct.chen@mediatek.com compatible = "mediatek,mt8173-efuse"; 29493e9f5eeSandrew-ct.chen@mediatek.com reg = <0 0x10206000 0 0x1000>; 29593e9f5eeSandrew-ct.chen@mediatek.com }; 29693e9f5eeSandrew-ct.chen@mediatek.com 297f2ce7014SSascha Hauer apmixedsys: clock-controller@10209000 { 298f2ce7014SSascha Hauer compatible = "mediatek,mt8173-apmixedsys"; 299f2ce7014SSascha Hauer reg = <0 0x10209000 0 0x1000>; 300f2ce7014SSascha Hauer #clock-cells = <1>; 301f2ce7014SSascha Hauer }; 302f2ce7014SSascha Hauer 303b3a37248SEddie Huang gic: interrupt-controller@10220000 { 304b3a37248SEddie Huang compatible = "arm,gic-400"; 305b3a37248SEddie Huang #interrupt-cells = <3>; 306b3a37248SEddie Huang interrupt-parent = <&gic>; 307b3a37248SEddie Huang interrupt-controller; 308b3a37248SEddie Huang reg = <0 0x10221000 0 0x1000>, 309b3a37248SEddie Huang <0 0x10222000 0 0x2000>, 310b3a37248SEddie Huang <0 0x10224000 0 0x2000>, 311b3a37248SEddie Huang <0 0x10226000 0 0x2000>; 312b3a37248SEddie Huang interrupts = <GIC_PPI 9 313b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 314b3a37248SEddie Huang }; 315b3a37248SEddie Huang 316748c7d4dSSascha Hauer auxadc: auxadc@11001000 { 317748c7d4dSSascha Hauer compatible = "mediatek,mt8173-auxadc"; 318748c7d4dSSascha Hauer reg = <0 0x11001000 0 0x1000>; 319748c7d4dSSascha Hauer }; 320748c7d4dSSascha Hauer 321b3a37248SEddie Huang uart0: serial@11002000 { 322b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 323b3a37248SEddie Huang "mediatek,mt6577-uart"; 324b3a37248SEddie Huang reg = <0 0x11002000 0 0x400>; 325b3a37248SEddie Huang interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 3260e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 3270e84faa1SSascha Hauer clock-names = "baud", "bus"; 328b3a37248SEddie Huang status = "disabled"; 329b3a37248SEddie Huang }; 330b3a37248SEddie Huang 331b3a37248SEddie Huang uart1: serial@11003000 { 332b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 333b3a37248SEddie Huang "mediatek,mt6577-uart"; 334b3a37248SEddie Huang reg = <0 0x11003000 0 0x400>; 335b3a37248SEddie Huang interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 3360e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 3370e84faa1SSascha Hauer clock-names = "baud", "bus"; 338b3a37248SEddie Huang status = "disabled"; 339b3a37248SEddie Huang }; 340b3a37248SEddie Huang 341b3a37248SEddie Huang uart2: serial@11004000 { 342b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 343b3a37248SEddie Huang "mediatek,mt6577-uart"; 344b3a37248SEddie Huang reg = <0 0x11004000 0 0x400>; 345b3a37248SEddie Huang interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 3460e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 3470e84faa1SSascha Hauer clock-names = "baud", "bus"; 348b3a37248SEddie Huang status = "disabled"; 349b3a37248SEddie Huang }; 350b3a37248SEddie Huang 351b3a37248SEddie Huang uart3: serial@11005000 { 352b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 353b3a37248SEddie Huang "mediatek,mt6577-uart"; 354b3a37248SEddie Huang reg = <0 0x11005000 0 0x400>; 355b3a37248SEddie Huang interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 3560e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 3570e84faa1SSascha Hauer clock-names = "baud", "bus"; 358b3a37248SEddie Huang status = "disabled"; 359b3a37248SEddie Huang }; 360091cf598SEddie Huang 361091cf598SEddie Huang i2c0: i2c@11007000 { 362091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 363091cf598SEddie Huang reg = <0 0x11007000 0 0x70>, 364091cf598SEddie Huang <0 0x11000100 0 0x80>; 365091cf598SEddie Huang interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 366091cf598SEddie Huang clock-div = <16>; 367091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C0>, 368091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 369091cf598SEddie Huang clock-names = "main", "dma"; 370091cf598SEddie Huang pinctrl-names = "default"; 371091cf598SEddie Huang pinctrl-0 = <&i2c0_pins_a>; 372091cf598SEddie Huang #address-cells = <1>; 373091cf598SEddie Huang #size-cells = <0>; 374091cf598SEddie Huang status = "disabled"; 375091cf598SEddie Huang }; 376091cf598SEddie Huang 377091cf598SEddie Huang i2c1: i2c@11008000 { 378091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 379091cf598SEddie Huang reg = <0 0x11008000 0 0x70>, 380091cf598SEddie Huang <0 0x11000180 0 0x80>; 381091cf598SEddie Huang interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 382091cf598SEddie Huang clock-div = <16>; 383091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C1>, 384091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 385091cf598SEddie Huang clock-names = "main", "dma"; 386091cf598SEddie Huang pinctrl-names = "default"; 387091cf598SEddie Huang pinctrl-0 = <&i2c1_pins_a>; 388091cf598SEddie Huang #address-cells = <1>; 389091cf598SEddie Huang #size-cells = <0>; 390091cf598SEddie Huang status = "disabled"; 391091cf598SEddie Huang }; 392091cf598SEddie Huang 393091cf598SEddie Huang i2c2: i2c@11009000 { 394091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 395091cf598SEddie Huang reg = <0 0x11009000 0 0x70>, 396091cf598SEddie Huang <0 0x11000200 0 0x80>; 397091cf598SEddie Huang interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 398091cf598SEddie Huang clock-div = <16>; 399091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C2>, 400091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 401091cf598SEddie Huang clock-names = "main", "dma"; 402091cf598SEddie Huang pinctrl-names = "default"; 403091cf598SEddie Huang pinctrl-0 = <&i2c2_pins_a>; 404091cf598SEddie Huang #address-cells = <1>; 405091cf598SEddie Huang #size-cells = <0>; 406091cf598SEddie Huang status = "disabled"; 407091cf598SEddie Huang }; 408091cf598SEddie Huang 409b0c936f5SLeilk Liu spi: spi@1100a000 { 410b0c936f5SLeilk Liu compatible = "mediatek,mt8173-spi"; 411b0c936f5SLeilk Liu #address-cells = <1>; 412b0c936f5SLeilk Liu #size-cells = <0>; 413b0c936f5SLeilk Liu reg = <0 0x1100a000 0 0x1000>; 414b0c936f5SLeilk Liu interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 415b0c936f5SLeilk Liu clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 416b0c936f5SLeilk Liu <&topckgen CLK_TOP_SPI_SEL>, 417b0c936f5SLeilk Liu <&pericfg CLK_PERI_SPI0>; 418b0c936f5SLeilk Liu clock-names = "parent-clk", "sel-clk", "spi-clk"; 419b0c936f5SLeilk Liu status = "disabled"; 420b0c936f5SLeilk Liu }; 421b0c936f5SLeilk Liu 422748c7d4dSSascha Hauer thermal: thermal@1100b000 { 423748c7d4dSSascha Hauer #thermal-sensor-cells = <0>; 424748c7d4dSSascha Hauer compatible = "mediatek,mt8173-thermal"; 425748c7d4dSSascha Hauer reg = <0 0x1100b000 0 0x1000>; 426748c7d4dSSascha Hauer interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 427748c7d4dSSascha Hauer clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 428748c7d4dSSascha Hauer clock-names = "therm", "auxadc"; 429748c7d4dSSascha Hauer resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 430748c7d4dSSascha Hauer mediatek,auxadc = <&auxadc>; 431748c7d4dSSascha Hauer mediatek,apmixedsys = <&apmixedsys>; 432748c7d4dSSascha Hauer }; 433748c7d4dSSascha Hauer 43486cb8a88SBayi Cheng nor_flash: spi@1100d000 { 43586cb8a88SBayi Cheng compatible = "mediatek,mt8173-nor"; 43686cb8a88SBayi Cheng reg = <0 0x1100d000 0 0xe0>; 43786cb8a88SBayi Cheng clocks = <&pericfg CLK_PERI_SPI>, 43886cb8a88SBayi Cheng <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 43986cb8a88SBayi Cheng clock-names = "spi", "sf"; 44086cb8a88SBayi Cheng #address-cells = <1>; 44186cb8a88SBayi Cheng #size-cells = <0>; 44286cb8a88SBayi Cheng status = "disabled"; 44386cb8a88SBayi Cheng }; 44486cb8a88SBayi Cheng 4451ee35c05SYingjoe Chen i2c3: i2c@11010000 { 446091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 447091cf598SEddie Huang reg = <0 0x11010000 0 0x70>, 448091cf598SEddie Huang <0 0x11000280 0 0x80>; 449091cf598SEddie Huang interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 450091cf598SEddie Huang clock-div = <16>; 451091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C3>, 452091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 453091cf598SEddie Huang clock-names = "main", "dma"; 454091cf598SEddie Huang pinctrl-names = "default"; 455091cf598SEddie Huang pinctrl-0 = <&i2c3_pins_a>; 456091cf598SEddie Huang #address-cells = <1>; 457091cf598SEddie Huang #size-cells = <0>; 458091cf598SEddie Huang status = "disabled"; 459091cf598SEddie Huang }; 460091cf598SEddie Huang 4611ee35c05SYingjoe Chen i2c4: i2c@11011000 { 462091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 463091cf598SEddie Huang reg = <0 0x11011000 0 0x70>, 464091cf598SEddie Huang <0 0x11000300 0 0x80>; 465091cf598SEddie Huang interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 466091cf598SEddie Huang clock-div = <16>; 467091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C4>, 468091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 469091cf598SEddie Huang clock-names = "main", "dma"; 470091cf598SEddie Huang pinctrl-names = "default"; 471091cf598SEddie Huang pinctrl-0 = <&i2c4_pins_a>; 472091cf598SEddie Huang #address-cells = <1>; 473091cf598SEddie Huang #size-cells = <0>; 474091cf598SEddie Huang status = "disabled"; 475091cf598SEddie Huang }; 476091cf598SEddie Huang 4771ee35c05SYingjoe Chen i2c6: i2c@11013000 { 478091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 479091cf598SEddie Huang reg = <0 0x11013000 0 0x70>, 480091cf598SEddie Huang <0 0x11000080 0 0x80>; 481091cf598SEddie Huang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 482091cf598SEddie Huang clock-div = <16>; 483091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C6>, 484091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 485091cf598SEddie Huang clock-names = "main", "dma"; 486091cf598SEddie Huang pinctrl-names = "default"; 487091cf598SEddie Huang pinctrl-0 = <&i2c6_pins_a>; 488091cf598SEddie Huang #address-cells = <1>; 489091cf598SEddie Huang #size-cells = <0>; 490091cf598SEddie Huang status = "disabled"; 491091cf598SEddie Huang }; 492c02e0e86SKoro Chen 493c02e0e86SKoro Chen afe: audio-controller@11220000 { 494c02e0e86SKoro Chen compatible = "mediatek,mt8173-afe-pcm"; 495c02e0e86SKoro Chen reg = <0 0x11220000 0 0x1000>; 496c02e0e86SKoro Chen interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 497c02e0e86SKoro Chen power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; 498c02e0e86SKoro Chen clocks = <&infracfg CLK_INFRA_AUDIO>, 499c02e0e86SKoro Chen <&topckgen CLK_TOP_AUDIO_SEL>, 500c02e0e86SKoro Chen <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 501c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL1_DIV0>, 502c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL2_DIV0>, 503c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S0_M_SEL>, 504c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S1_M_SEL>, 505c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S2_M_SEL>, 506c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S3_M_SEL>, 507c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S3_B_SEL>; 508c02e0e86SKoro Chen clock-names = "infra_sys_audio_clk", 509c02e0e86SKoro Chen "top_pdn_audio", 510c02e0e86SKoro Chen "top_pdn_aud_intbus", 511c02e0e86SKoro Chen "bck0", 512c02e0e86SKoro Chen "bck1", 513c02e0e86SKoro Chen "i2s0_m", 514c02e0e86SKoro Chen "i2s1_m", 515c02e0e86SKoro Chen "i2s2_m", 516c02e0e86SKoro Chen "i2s3_m", 517c02e0e86SKoro Chen "i2s3_b"; 518c02e0e86SKoro Chen assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 519c02e0e86SKoro Chen <&topckgen CLK_TOP_AUD_2_SEL>; 520c02e0e86SKoro Chen assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 521c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL2>; 522c02e0e86SKoro Chen }; 5239719fa5aSEddie Huang 5249719fa5aSEddie Huang mmc0: mmc@11230000 { 5259719fa5aSEddie Huang compatible = "mediatek,mt8173-mmc", 5269719fa5aSEddie Huang "mediatek,mt8135-mmc"; 5279719fa5aSEddie Huang reg = <0 0x11230000 0 0x1000>; 5289719fa5aSEddie Huang interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 5299719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_0>, 5309719fa5aSEddie Huang <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 5319719fa5aSEddie Huang clock-names = "source", "hclk"; 5329719fa5aSEddie Huang status = "disabled"; 5339719fa5aSEddie Huang }; 5349719fa5aSEddie Huang 5359719fa5aSEddie Huang mmc1: mmc@11240000 { 5369719fa5aSEddie Huang compatible = "mediatek,mt8173-mmc", 5379719fa5aSEddie Huang "mediatek,mt8135-mmc"; 5389719fa5aSEddie Huang reg = <0 0x11240000 0 0x1000>; 5399719fa5aSEddie Huang interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 5409719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_1>, 5419719fa5aSEddie Huang <&topckgen CLK_TOP_AXI_SEL>; 5429719fa5aSEddie Huang clock-names = "source", "hclk"; 5439719fa5aSEddie Huang status = "disabled"; 5449719fa5aSEddie Huang }; 5459719fa5aSEddie Huang 5469719fa5aSEddie Huang mmc2: mmc@11250000 { 5479719fa5aSEddie Huang compatible = "mediatek,mt8173-mmc", 5489719fa5aSEddie Huang "mediatek,mt8135-mmc"; 5499719fa5aSEddie Huang reg = <0 0x11250000 0 0x1000>; 5509719fa5aSEddie Huang interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 5519719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_2>, 5529719fa5aSEddie Huang <&topckgen CLK_TOP_AXI_SEL>; 5539719fa5aSEddie Huang clock-names = "source", "hclk"; 5549719fa5aSEddie Huang status = "disabled"; 5559719fa5aSEddie Huang }; 5569719fa5aSEddie Huang 5579719fa5aSEddie Huang mmc3: mmc@11260000 { 5589719fa5aSEddie Huang compatible = "mediatek,mt8173-mmc", 5599719fa5aSEddie Huang "mediatek,mt8135-mmc"; 5609719fa5aSEddie Huang reg = <0 0x11260000 0 0x1000>; 5619719fa5aSEddie Huang interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 5629719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_3>, 5639719fa5aSEddie Huang <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 5649719fa5aSEddie Huang clock-names = "source", "hclk"; 5659719fa5aSEddie Huang status = "disabled"; 5669719fa5aSEddie Huang }; 56767e56c56SJames Liao 568bfcce47aSChunfeng Yun usb30: usb@11270000 { 569bfcce47aSChunfeng Yun compatible = "mediatek,mt8173-xhci"; 570bfcce47aSChunfeng Yun reg = <0 0x11270000 0 0x1000>, 571bfcce47aSChunfeng Yun <0 0x11280700 0 0x0100>; 572bfcce47aSChunfeng Yun interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 573bfcce47aSChunfeng Yun power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 574bfcce47aSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>, 575bfcce47aSChunfeng Yun <&pericfg CLK_PERI_USB0>, 576bfcce47aSChunfeng Yun <&pericfg CLK_PERI_USB1>; 577bfcce47aSChunfeng Yun clock-names = "sys_ck", 578bfcce47aSChunfeng Yun "wakeup_deb_p0", 579bfcce47aSChunfeng Yun "wakeup_deb_p1"; 580bfcce47aSChunfeng Yun phys = <&phy_port0 PHY_TYPE_USB3>, 581bfcce47aSChunfeng Yun <&phy_port1 PHY_TYPE_USB2>; 582bfcce47aSChunfeng Yun mediatek,syscon-wakeup = <&pericfg>; 583bfcce47aSChunfeng Yun status = "okay"; 584bfcce47aSChunfeng Yun }; 585bfcce47aSChunfeng Yun 586bfcce47aSChunfeng Yun u3phy: usb-phy@11290000 { 587bfcce47aSChunfeng Yun compatible = "mediatek,mt8173-u3phy"; 588bfcce47aSChunfeng Yun reg = <0 0x11290000 0 0x800>; 589bfcce47aSChunfeng Yun clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 590bfcce47aSChunfeng Yun clock-names = "u3phya_ref"; 591bfcce47aSChunfeng Yun #address-cells = <2>; 592bfcce47aSChunfeng Yun #size-cells = <2>; 593bfcce47aSChunfeng Yun ranges; 594bfcce47aSChunfeng Yun status = "okay"; 595bfcce47aSChunfeng Yun 596bfcce47aSChunfeng Yun phy_port0: port@11290800 { 597bfcce47aSChunfeng Yun reg = <0 0x11290800 0 0x800>; 598bfcce47aSChunfeng Yun #phy-cells = <1>; 599bfcce47aSChunfeng Yun status = "okay"; 600bfcce47aSChunfeng Yun }; 601bfcce47aSChunfeng Yun 602bfcce47aSChunfeng Yun phy_port1: port@11291000 { 603bfcce47aSChunfeng Yun reg = <0 0x11291000 0 0x800>; 604bfcce47aSChunfeng Yun #phy-cells = <1>; 605bfcce47aSChunfeng Yun status = "okay"; 606bfcce47aSChunfeng Yun }; 607bfcce47aSChunfeng Yun }; 608bfcce47aSChunfeng Yun 60967e56c56SJames Liao mmsys: clock-controller@14000000 { 61067e56c56SJames Liao compatible = "mediatek,mt8173-mmsys", "syscon"; 61167e56c56SJames Liao reg = <0 0x14000000 0 0x1000>; 61267e56c56SJames Liao #clock-cells = <1>; 61367e56c56SJames Liao }; 61467e56c56SJames Liao 61561aee934SYH Huang pwm0: pwm@1401e000 { 61661aee934SYH Huang compatible = "mediatek,mt8173-disp-pwm", 61761aee934SYH Huang "mediatek,mt6595-disp-pwm"; 61861aee934SYH Huang reg = <0 0x1401e000 0 0x1000>; 61961aee934SYH Huang #pwm-cells = <2>; 62061aee934SYH Huang clocks = <&mmsys CLK_MM_DISP_PWM026M>, 62161aee934SYH Huang <&mmsys CLK_MM_DISP_PWM0MM>; 62261aee934SYH Huang clock-names = "main", "mm"; 62361aee934SYH Huang status = "disabled"; 62461aee934SYH Huang }; 62561aee934SYH Huang 62661aee934SYH Huang pwm1: pwm@1401f000 { 62761aee934SYH Huang compatible = "mediatek,mt8173-disp-pwm", 62861aee934SYH Huang "mediatek,mt6595-disp-pwm"; 62961aee934SYH Huang reg = <0 0x1401f000 0 0x1000>; 63061aee934SYH Huang #pwm-cells = <2>; 63161aee934SYH Huang clocks = <&mmsys CLK_MM_DISP_PWM126M>, 63261aee934SYH Huang <&mmsys CLK_MM_DISP_PWM1MM>; 63361aee934SYH Huang clock-names = "main", "mm"; 63461aee934SYH Huang status = "disabled"; 63561aee934SYH Huang }; 63661aee934SYH Huang 6375ff6b3a6SYong Wu larb0: larb@14021000 { 6385ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 6395ff6b3a6SYong Wu reg = <0 0x14021000 0 0x1000>; 6405ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 6415ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 6425ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_LARB0>, 6435ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_LARB0>; 6445ff6b3a6SYong Wu clock-names = "apb", "smi"; 6455ff6b3a6SYong Wu }; 6465ff6b3a6SYong Wu 6475ff6b3a6SYong Wu smi_common: smi@14022000 { 6485ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-common"; 6495ff6b3a6SYong Wu reg = <0 0x14022000 0 0x1000>; 6505ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 6515ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_COMMON>, 6525ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_COMMON>; 6535ff6b3a6SYong Wu clock-names = "apb", "smi"; 6545ff6b3a6SYong Wu }; 6555ff6b3a6SYong Wu 6565ff6b3a6SYong Wu larb4: larb@14027000 { 6575ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 6585ff6b3a6SYong Wu reg = <0 0x14027000 0 0x1000>; 6595ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 6605ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 6615ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_LARB4>, 6625ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_LARB4>; 6635ff6b3a6SYong Wu clock-names = "apb", "smi"; 6645ff6b3a6SYong Wu }; 6655ff6b3a6SYong Wu 66667e56c56SJames Liao imgsys: clock-controller@15000000 { 66767e56c56SJames Liao compatible = "mediatek,mt8173-imgsys", "syscon"; 66867e56c56SJames Liao reg = <0 0x15000000 0 0x1000>; 66967e56c56SJames Liao #clock-cells = <1>; 67067e56c56SJames Liao }; 67167e56c56SJames Liao 6725ff6b3a6SYong Wu larb2: larb@15001000 { 6735ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 6745ff6b3a6SYong Wu reg = <0 0x15001000 0 0x1000>; 6755ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 6765ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>; 6775ff6b3a6SYong Wu clocks = <&imgsys CLK_IMG_LARB2_SMI>, 6785ff6b3a6SYong Wu <&imgsys CLK_IMG_LARB2_SMI>; 6795ff6b3a6SYong Wu clock-names = "apb", "smi"; 6805ff6b3a6SYong Wu }; 6815ff6b3a6SYong Wu 68267e56c56SJames Liao vdecsys: clock-controller@16000000 { 68367e56c56SJames Liao compatible = "mediatek,mt8173-vdecsys", "syscon"; 68467e56c56SJames Liao reg = <0 0x16000000 0 0x1000>; 68567e56c56SJames Liao #clock-cells = <1>; 68667e56c56SJames Liao }; 68767e56c56SJames Liao 6885ff6b3a6SYong Wu larb1: larb@16010000 { 6895ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 6905ff6b3a6SYong Wu reg = <0 0x16010000 0 0x1000>; 6915ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 6925ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 6935ff6b3a6SYong Wu clocks = <&vdecsys CLK_VDEC_CKEN>, 6945ff6b3a6SYong Wu <&vdecsys CLK_VDEC_LARB_CKEN>; 6955ff6b3a6SYong Wu clock-names = "apb", "smi"; 6965ff6b3a6SYong Wu }; 6975ff6b3a6SYong Wu 69867e56c56SJames Liao vencsys: clock-controller@18000000 { 69967e56c56SJames Liao compatible = "mediatek,mt8173-vencsys", "syscon"; 70067e56c56SJames Liao reg = <0 0x18000000 0 0x1000>; 70167e56c56SJames Liao #clock-cells = <1>; 70267e56c56SJames Liao }; 70367e56c56SJames Liao 7045ff6b3a6SYong Wu larb3: larb@18001000 { 7055ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 7065ff6b3a6SYong Wu reg = <0 0x18001000 0 0x1000>; 7075ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 7085ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 7095ff6b3a6SYong Wu clocks = <&vencsys CLK_VENC_CKE1>, 7105ff6b3a6SYong Wu <&vencsys CLK_VENC_CKE0>; 7115ff6b3a6SYong Wu clock-names = "apb", "smi"; 7125ff6b3a6SYong Wu }; 7135ff6b3a6SYong Wu 71467e56c56SJames Liao vencltsys: clock-controller@19000000 { 71567e56c56SJames Liao compatible = "mediatek,mt8173-vencltsys", "syscon"; 71667e56c56SJames Liao reg = <0 0x19000000 0 0x1000>; 71767e56c56SJames Liao #clock-cells = <1>; 71867e56c56SJames Liao }; 7195ff6b3a6SYong Wu 7205ff6b3a6SYong Wu larb5: larb@19001000 { 7215ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 7225ff6b3a6SYong Wu reg = <0 0x19001000 0 0x1000>; 7235ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 7245ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; 7255ff6b3a6SYong Wu clocks = <&vencltsys CLK_VENCLT_CKE1>, 7265ff6b3a6SYong Wu <&vencltsys CLK_VENCLT_CKE0>; 7275ff6b3a6SYong Wu clock-names = "apb", "smi"; 7285ff6b3a6SYong Wu }; 729b3a37248SEddie Huang }; 730b3a37248SEddie Huang}; 731b3a37248SEddie Huang 732