1b3a37248SEddie Huang/* 2b3a37248SEddie Huang * Copyright (c) 2014 MediaTek Inc. 3b3a37248SEddie Huang * Author: Eddie Huang <eddie.huang@mediatek.com> 4b3a37248SEddie Huang * 5b3a37248SEddie Huang * This program is free software; you can redistribute it and/or modify 6b3a37248SEddie Huang * it under the terms of the GNU General Public License version 2 as 7b3a37248SEddie Huang * published by the Free Software Foundation. 8b3a37248SEddie Huang * 9b3a37248SEddie Huang * This program is distributed in the hope that it will be useful, 10b3a37248SEddie Huang * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11b3a37248SEddie Huang * GNU General Public License for more details. 12b3a37248SEddie Huang */ 13b3a37248SEddie Huang 14f2ce7014SSascha Hauer#include <dt-bindings/clock/mt8173-clk.h> 15b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/irq.h> 16b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/arm-gic.h> 175ff6b3a6SYong Wu#include <dt-bindings/memory/mt8173-larb-port.h> 18bfcce47aSChunfeng Yun#include <dt-bindings/phy/phy.h> 19c02e0e86SKoro Chen#include <dt-bindings/power/mt8173-power.h> 20967313e2SPhilipp Zabel#include <dt-bindings/reset/mt8173-resets.h> 21c2e66b8fSHoulong Wei#include <dt-bindings/gce/mt8173-gce.h> 22359f9365SHongzhou Yang#include "mt8173-pinfunc.h" 23b3a37248SEddie Huang 24b3a37248SEddie Huang/ { 25b3a37248SEddie Huang compatible = "mediatek,mt8173"; 26b3a37248SEddie Huang interrupt-parent = <&sysirq>; 27b3a37248SEddie Huang #address-cells = <2>; 28b3a37248SEddie Huang #size-cells = <2>; 29b3a37248SEddie Huang 3081ad4dbaSCK Hu aliases { 3181ad4dbaSCK Hu ovl0 = &ovl0; 3281ad4dbaSCK Hu ovl1 = &ovl1; 3381ad4dbaSCK Hu rdma0 = &rdma0; 3481ad4dbaSCK Hu rdma1 = &rdma1; 3581ad4dbaSCK Hu rdma2 = &rdma2; 3681ad4dbaSCK Hu wdma0 = &wdma0; 3781ad4dbaSCK Hu wdma1 = &wdma1; 3881ad4dbaSCK Hu color0 = &color0; 3981ad4dbaSCK Hu color1 = &color1; 4081ad4dbaSCK Hu split0 = &split0; 4181ad4dbaSCK Hu split1 = &split1; 4281ad4dbaSCK Hu dpi0 = &dpi0; 4381ad4dbaSCK Hu dsi0 = &dsi0; 4481ad4dbaSCK Hu dsi1 = &dsi1; 45989b292aSMinghsiu Tsai mdp_rdma0 = &mdp_rdma0; 46989b292aSMinghsiu Tsai mdp_rdma1 = &mdp_rdma1; 47989b292aSMinghsiu Tsai mdp_rsz0 = &mdp_rsz0; 48989b292aSMinghsiu Tsai mdp_rsz1 = &mdp_rsz1; 49989b292aSMinghsiu Tsai mdp_rsz2 = &mdp_rsz2; 50989b292aSMinghsiu Tsai mdp_wdma0 = &mdp_wdma0; 51989b292aSMinghsiu Tsai mdp_wrot0 = &mdp_wrot0; 52989b292aSMinghsiu Tsai mdp_wrot1 = &mdp_wrot1; 530f5da28eSHsin-Yi Wang serial0 = &uart0; 540f5da28eSHsin-Yi Wang serial1 = &uart1; 550f5da28eSHsin-Yi Wang serial2 = &uart2; 560f5da28eSHsin-Yi Wang serial3 = &uart3; 5781ad4dbaSCK Hu }; 5881ad4dbaSCK Hu 59da85a3afSAndrew-sh Cheng cluster0_opp: opp_table0 { 60da85a3afSAndrew-sh Cheng compatible = "operating-points-v2"; 61da85a3afSAndrew-sh Cheng opp-shared; 62da85a3afSAndrew-sh Cheng opp-507000000 { 63da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <507000000>; 64da85a3afSAndrew-sh Cheng opp-microvolt = <859000>; 65da85a3afSAndrew-sh Cheng }; 66da85a3afSAndrew-sh Cheng opp-702000000 { 67da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <702000000>; 68da85a3afSAndrew-sh Cheng opp-microvolt = <908000>; 69da85a3afSAndrew-sh Cheng }; 70da85a3afSAndrew-sh Cheng opp-1001000000 { 71da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1001000000>; 72da85a3afSAndrew-sh Cheng opp-microvolt = <983000>; 73da85a3afSAndrew-sh Cheng }; 74da85a3afSAndrew-sh Cheng opp-1105000000 { 75da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1105000000>; 76da85a3afSAndrew-sh Cheng opp-microvolt = <1009000>; 77da85a3afSAndrew-sh Cheng }; 78da85a3afSAndrew-sh Cheng opp-1209000000 { 79da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1209000000>; 80da85a3afSAndrew-sh Cheng opp-microvolt = <1034000>; 81da85a3afSAndrew-sh Cheng }; 82da85a3afSAndrew-sh Cheng opp-1300000000 { 83da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1300000000>; 84da85a3afSAndrew-sh Cheng opp-microvolt = <1057000>; 85da85a3afSAndrew-sh Cheng }; 86da85a3afSAndrew-sh Cheng opp-1508000000 { 87da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1508000000>; 88da85a3afSAndrew-sh Cheng opp-microvolt = <1109000>; 89da85a3afSAndrew-sh Cheng }; 90da85a3afSAndrew-sh Cheng opp-1703000000 { 91da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1703000000>; 92da85a3afSAndrew-sh Cheng opp-microvolt = <1125000>; 93da85a3afSAndrew-sh Cheng }; 94da85a3afSAndrew-sh Cheng }; 95da85a3afSAndrew-sh Cheng 96da85a3afSAndrew-sh Cheng cluster1_opp: opp_table1 { 97da85a3afSAndrew-sh Cheng compatible = "operating-points-v2"; 98da85a3afSAndrew-sh Cheng opp-shared; 99da85a3afSAndrew-sh Cheng opp-507000000 { 100da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <507000000>; 101da85a3afSAndrew-sh Cheng opp-microvolt = <828000>; 102da85a3afSAndrew-sh Cheng }; 103da85a3afSAndrew-sh Cheng opp-702000000 { 104da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <702000000>; 105da85a3afSAndrew-sh Cheng opp-microvolt = <867000>; 106da85a3afSAndrew-sh Cheng }; 107da85a3afSAndrew-sh Cheng opp-1001000000 { 108da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1001000000>; 109da85a3afSAndrew-sh Cheng opp-microvolt = <927000>; 110da85a3afSAndrew-sh Cheng }; 111da85a3afSAndrew-sh Cheng opp-1209000000 { 112da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1209000000>; 113da85a3afSAndrew-sh Cheng opp-microvolt = <968000>; 114da85a3afSAndrew-sh Cheng }; 115da85a3afSAndrew-sh Cheng opp-1404000000 { 116da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1404000000>; 117da85a3afSAndrew-sh Cheng opp-microvolt = <1007000>; 118da85a3afSAndrew-sh Cheng }; 119da85a3afSAndrew-sh Cheng opp-1612000000 { 120da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1612000000>; 121da85a3afSAndrew-sh Cheng opp-microvolt = <1049000>; 122da85a3afSAndrew-sh Cheng }; 123da85a3afSAndrew-sh Cheng opp-1807000000 { 124da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1807000000>; 125da85a3afSAndrew-sh Cheng opp-microvolt = <1089000>; 126da85a3afSAndrew-sh Cheng }; 127da85a3afSAndrew-sh Cheng opp-2106000000 { 128da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <2106000000>; 129da85a3afSAndrew-sh Cheng opp-microvolt = <1125000>; 130da85a3afSAndrew-sh Cheng }; 131da85a3afSAndrew-sh Cheng }; 132da85a3afSAndrew-sh Cheng 133b3a37248SEddie Huang cpus { 134b3a37248SEddie Huang #address-cells = <1>; 135b3a37248SEddie Huang #size-cells = <0>; 136b3a37248SEddie Huang 137b3a37248SEddie Huang cpu-map { 138b3a37248SEddie Huang cluster0 { 139b3a37248SEddie Huang core0 { 140b3a37248SEddie Huang cpu = <&cpu0>; 141b3a37248SEddie Huang }; 142b3a37248SEddie Huang core1 { 143b3a37248SEddie Huang cpu = <&cpu1>; 144b3a37248SEddie Huang }; 145b3a37248SEddie Huang }; 146b3a37248SEddie Huang 147b3a37248SEddie Huang cluster1 { 148b3a37248SEddie Huang core0 { 149b3a37248SEddie Huang cpu = <&cpu2>; 150b3a37248SEddie Huang }; 151b3a37248SEddie Huang core1 { 152b3a37248SEddie Huang cpu = <&cpu3>; 153b3a37248SEddie Huang }; 154b3a37248SEddie Huang }; 155b3a37248SEddie Huang }; 156b3a37248SEddie Huang 157b3a37248SEddie Huang cpu0: cpu@0 { 158b3a37248SEddie Huang device_type = "cpu"; 159b3a37248SEddie Huang compatible = "arm,cortex-a53"; 160b3a37248SEddie Huang reg = <0x000>; 161ad4df7a5SHoward Chen enable-method = "psci"; 162ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 163acbf76eeSArnd Bergmann #cooling-cells = <2>; 16419f62c76Smichael.kao dynamic-power-coefficient = <263>; 165da85a3afSAndrew-sh Cheng clocks = <&infracfg CLK_INFRA_CA53SEL>, 166da85a3afSAndrew-sh Cheng <&apmixedsys CLK_APMIXED_MAINPLL>; 167da85a3afSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 168da85a3afSAndrew-sh Cheng operating-points-v2 = <&cluster0_opp>; 169b3a37248SEddie Huang }; 170b3a37248SEddie Huang 171b3a37248SEddie Huang cpu1: cpu@1 { 172b3a37248SEddie Huang device_type = "cpu"; 173b3a37248SEddie Huang compatible = "arm,cortex-a53"; 174b3a37248SEddie Huang reg = <0x001>; 175b3a37248SEddie Huang enable-method = "psci"; 176ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 177a06e5c05SViresh Kumar #cooling-cells = <2>; 17819f62c76Smichael.kao dynamic-power-coefficient = <263>; 179da85a3afSAndrew-sh Cheng clocks = <&infracfg CLK_INFRA_CA53SEL>, 180da85a3afSAndrew-sh Cheng <&apmixedsys CLK_APMIXED_MAINPLL>; 181da85a3afSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 182da85a3afSAndrew-sh Cheng operating-points-v2 = <&cluster0_opp>; 183b3a37248SEddie Huang }; 184b3a37248SEddie Huang 185b3a37248SEddie Huang cpu2: cpu@100 { 186b3a37248SEddie Huang device_type = "cpu"; 1875c6e116dSSeiya Wang compatible = "arm,cortex-a72"; 188b3a37248SEddie Huang reg = <0x100>; 189b3a37248SEddie Huang enable-method = "psci"; 190ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 191acbf76eeSArnd Bergmann #cooling-cells = <2>; 19219f62c76Smichael.kao dynamic-power-coefficient = <530>; 1935c6e116dSSeiya Wang clocks = <&infracfg CLK_INFRA_CA72SEL>, 194da85a3afSAndrew-sh Cheng <&apmixedsys CLK_APMIXED_MAINPLL>; 195da85a3afSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 196da85a3afSAndrew-sh Cheng operating-points-v2 = <&cluster1_opp>; 197b3a37248SEddie Huang }; 198b3a37248SEddie Huang 199b3a37248SEddie Huang cpu3: cpu@101 { 200b3a37248SEddie Huang device_type = "cpu"; 2015c6e116dSSeiya Wang compatible = "arm,cortex-a72"; 202b3a37248SEddie Huang reg = <0x101>; 203b3a37248SEddie Huang enable-method = "psci"; 204ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 205a06e5c05SViresh Kumar #cooling-cells = <2>; 20619f62c76Smichael.kao dynamic-power-coefficient = <530>; 2075c6e116dSSeiya Wang clocks = <&infracfg CLK_INFRA_CA72SEL>, 208da85a3afSAndrew-sh Cheng <&apmixedsys CLK_APMIXED_MAINPLL>; 209da85a3afSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 210da85a3afSAndrew-sh Cheng operating-points-v2 = <&cluster1_opp>; 211ad4df7a5SHoward Chen }; 212ad4df7a5SHoward Chen 213ad4df7a5SHoward Chen idle-states { 214a13f18f5SLorenzo Pieralisi entry-method = "psci"; 215ad4df7a5SHoward Chen 216ad4df7a5SHoward Chen CPU_SLEEP_0: cpu-sleep-0 { 217ad4df7a5SHoward Chen compatible = "arm,idle-state"; 218ad4df7a5SHoward Chen local-timer-stop; 219ad4df7a5SHoward Chen entry-latency-us = <639>; 220ad4df7a5SHoward Chen exit-latency-us = <680>; 221ad4df7a5SHoward Chen min-residency-us = <1088>; 222ad4df7a5SHoward Chen arm,psci-suspend-param = <0x0010000>; 223ad4df7a5SHoward Chen }; 224b3a37248SEddie Huang }; 225b3a37248SEddie Huang }; 226b3a37248SEddie Huang 227a4599f6eSSeiya Wang pmu_a53 { 228a4599f6eSSeiya Wang compatible = "arm,cortex-a53-pmu"; 229a4599f6eSSeiya Wang interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, 230a4599f6eSSeiya Wang <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>; 231a4599f6eSSeiya Wang interrupt-affinity = <&cpu0>, <&cpu1>; 232a4599f6eSSeiya Wang }; 233a4599f6eSSeiya Wang 234a4599f6eSSeiya Wang pmu_a72 { 235a4599f6eSSeiya Wang compatible = "arm,cortex-a72-pmu"; 236a4599f6eSSeiya Wang interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>, 237a4599f6eSSeiya Wang <GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>; 238a4599f6eSSeiya Wang interrupt-affinity = <&cpu2>, <&cpu3>; 239a4599f6eSSeiya Wang }; 240a4599f6eSSeiya Wang 241b3a37248SEddie Huang psci { 24205bdabe7SFan Chen compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 243b3a37248SEddie Huang method = "smc"; 244b3a37248SEddie Huang cpu_suspend = <0x84000001>; 245b3a37248SEddie Huang cpu_off = <0x84000002>; 246b3a37248SEddie Huang cpu_on = <0x84000003>; 247b3a37248SEddie Huang }; 248b3a37248SEddie Huang 24972b29215SHsin-Yi Wang clk26m: oscillator0 { 250f2ce7014SSascha Hauer compatible = "fixed-clock"; 251f2ce7014SSascha Hauer #clock-cells = <0>; 252f2ce7014SSascha Hauer clock-frequency = <26000000>; 253f2ce7014SSascha Hauer clock-output-names = "clk26m"; 254f2ce7014SSascha Hauer }; 255f2ce7014SSascha Hauer 25672b29215SHsin-Yi Wang clk32k: oscillator1 { 257f2ce7014SSascha Hauer compatible = "fixed-clock"; 258f2ce7014SSascha Hauer #clock-cells = <0>; 259f2ce7014SSascha Hauer clock-frequency = <32000>; 260f2ce7014SSascha Hauer clock-output-names = "clk32k"; 261f2ce7014SSascha Hauer }; 262f2ce7014SSascha Hauer 26372b29215SHsin-Yi Wang cpum_ck: oscillator2 { 26467e56c56SJames Liao compatible = "fixed-clock"; 26567e56c56SJames Liao #clock-cells = <0>; 26667e56c56SJames Liao clock-frequency = <0>; 26767e56c56SJames Liao clock-output-names = "cpum_ck"; 26867e56c56SJames Liao }; 26967e56c56SJames Liao 270962f5143Sdawei.chien@mediatek.com thermal-zones { 271962f5143Sdawei.chien@mediatek.com cpu_thermal: cpu_thermal { 272962f5143Sdawei.chien@mediatek.com polling-delay-passive = <1000>; /* milliseconds */ 273962f5143Sdawei.chien@mediatek.com polling-delay = <1000>; /* milliseconds */ 274962f5143Sdawei.chien@mediatek.com 275962f5143Sdawei.chien@mediatek.com thermal-sensors = <&thermal>; 276962f5143Sdawei.chien@mediatek.com sustainable-power = <1500>; /* milliwatts */ 277962f5143Sdawei.chien@mediatek.com 278962f5143Sdawei.chien@mediatek.com trips { 27972b29215SHsin-Yi Wang threshold: trip-point0 { 280962f5143Sdawei.chien@mediatek.com temperature = <68000>; 281962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 282962f5143Sdawei.chien@mediatek.com type = "passive"; 283962f5143Sdawei.chien@mediatek.com }; 284962f5143Sdawei.chien@mediatek.com 28572b29215SHsin-Yi Wang target: trip-point1 { 286962f5143Sdawei.chien@mediatek.com temperature = <85000>; 287962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 288962f5143Sdawei.chien@mediatek.com type = "passive"; 289962f5143Sdawei.chien@mediatek.com }; 290962f5143Sdawei.chien@mediatek.com 29172b29215SHsin-Yi Wang cpu_crit: cpu_crit0 { 292962f5143Sdawei.chien@mediatek.com temperature = <115000>; 293962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 294962f5143Sdawei.chien@mediatek.com type = "critical"; 295962f5143Sdawei.chien@mediatek.com }; 296962f5143Sdawei.chien@mediatek.com }; 297962f5143Sdawei.chien@mediatek.com 298962f5143Sdawei.chien@mediatek.com cooling-maps { 29972b29215SHsin-Yi Wang map0 { 300962f5143Sdawei.chien@mediatek.com trip = <&target>; 301398ed292SViresh Kumar cooling-device = <&cpu0 0 0>, 302398ed292SViresh Kumar <&cpu1 0 0>; 3037fcef92dSDaniel Kurtz contribution = <3072>; 304962f5143Sdawei.chien@mediatek.com }; 30572b29215SHsin-Yi Wang map1 { 306962f5143Sdawei.chien@mediatek.com trip = <&target>; 307398ed292SViresh Kumar cooling-device = <&cpu2 0 0>, 308398ed292SViresh Kumar <&cpu3 0 0>; 3097fcef92dSDaniel Kurtz contribution = <1024>; 310962f5143Sdawei.chien@mediatek.com }; 311962f5143Sdawei.chien@mediatek.com }; 312962f5143Sdawei.chien@mediatek.com }; 313962f5143Sdawei.chien@mediatek.com }; 314962f5143Sdawei.chien@mediatek.com 315404b2819SAndrew-CT Chen reserved-memory { 316404b2819SAndrew-CT Chen #address-cells = <2>; 317404b2819SAndrew-CT Chen #size-cells = <2>; 318404b2819SAndrew-CT Chen ranges; 31972b29215SHsin-Yi Wang vpu_dma_reserved: vpu_dma_mem_region@b7000000 { 320404b2819SAndrew-CT Chen compatible = "shared-dma-pool"; 321404b2819SAndrew-CT Chen reg = <0 0xb7000000 0 0x500000>; 322404b2819SAndrew-CT Chen alignment = <0x1000>; 323404b2819SAndrew-CT Chen no-map; 324404b2819SAndrew-CT Chen }; 325404b2819SAndrew-CT Chen }; 326404b2819SAndrew-CT Chen 327b3a37248SEddie Huang timer { 328b3a37248SEddie Huang compatible = "arm,armv8-timer"; 329b3a37248SEddie Huang interrupt-parent = <&gic>; 330b3a37248SEddie Huang interrupts = <GIC_PPI 13 331b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 332b3a37248SEddie Huang <GIC_PPI 14 333b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 334b3a37248SEddie Huang <GIC_PPI 11 335b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 336b3a37248SEddie Huang <GIC_PPI 10 337b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 338b5686273SHsin-Yi Wang arm,no-tick-in-suspend; 339b3a37248SEddie Huang }; 340b3a37248SEddie Huang 341b3a37248SEddie Huang soc { 342b3a37248SEddie Huang #address-cells = <2>; 343b3a37248SEddie Huang #size-cells = <2>; 344b3a37248SEddie Huang compatible = "simple-bus"; 345b3a37248SEddie Huang ranges; 346b3a37248SEddie Huang 347f2ce7014SSascha Hauer topckgen: clock-controller@10000000 { 348f2ce7014SSascha Hauer compatible = "mediatek,mt8173-topckgen"; 349f2ce7014SSascha Hauer reg = <0 0x10000000 0 0x1000>; 350f2ce7014SSascha Hauer #clock-cells = <1>; 351f2ce7014SSascha Hauer }; 352f2ce7014SSascha Hauer 353f2ce7014SSascha Hauer infracfg: power-controller@10001000 { 354f2ce7014SSascha Hauer compatible = "mediatek,mt8173-infracfg", "syscon"; 355f2ce7014SSascha Hauer reg = <0 0x10001000 0 0x1000>; 356f2ce7014SSascha Hauer #clock-cells = <1>; 357f2ce7014SSascha Hauer #reset-cells = <1>; 358f2ce7014SSascha Hauer }; 359f2ce7014SSascha Hauer 360f2ce7014SSascha Hauer pericfg: power-controller@10003000 { 361f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pericfg", "syscon"; 362f2ce7014SSascha Hauer reg = <0 0x10003000 0 0x1000>; 363f2ce7014SSascha Hauer #clock-cells = <1>; 364f2ce7014SSascha Hauer #reset-cells = <1>; 365f2ce7014SSascha Hauer }; 366f2ce7014SSascha Hauer 367f2ce7014SSascha Hauer syscfg_pctl_a: syscfg_pctl_a@10005000 { 368f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 369f2ce7014SSascha Hauer reg = <0 0x10005000 0 0x1000>; 370f2ce7014SSascha Hauer }; 371f2ce7014SSascha Hauer 37272b29215SHsin-Yi Wang pio: pinctrl@1000b000 { 373359f9365SHongzhou Yang compatible = "mediatek,mt8173-pinctrl"; 3746769b93cSYingjoe Chen reg = <0 0x1000b000 0 0x1000>; 375359f9365SHongzhou Yang mediatek,pctl-regmap = <&syscfg_pctl_a>; 376359f9365SHongzhou Yang pins-are-numbered; 377359f9365SHongzhou Yang gpio-controller; 378359f9365SHongzhou Yang #gpio-cells = <2>; 379359f9365SHongzhou Yang interrupt-controller; 380359f9365SHongzhou Yang #interrupt-cells = <2>; 381359f9365SHongzhou Yang interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 382359f9365SHongzhou Yang <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 383359f9365SHongzhou Yang <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 384091cf598SEddie Huang 385a10b57f4SCK Hu hdmi_pin: xxx { 386a10b57f4SCK Hu 387a10b57f4SCK Hu /*hdmi htplg pin*/ 388a10b57f4SCK Hu pins1 { 389a10b57f4SCK Hu pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>; 390a10b57f4SCK Hu input-enable; 391a10b57f4SCK Hu bias-pull-down; 392a10b57f4SCK Hu }; 393a10b57f4SCK Hu }; 394a10b57f4SCK Hu 395091cf598SEddie Huang i2c0_pins_a: i2c0 { 396091cf598SEddie Huang pins1 { 397091cf598SEddie Huang pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 398091cf598SEddie Huang <MT8173_PIN_46_SCL0__FUNC_SCL0>; 399091cf598SEddie Huang bias-disable; 400091cf598SEddie Huang }; 401359f9365SHongzhou Yang }; 402359f9365SHongzhou Yang 403091cf598SEddie Huang i2c1_pins_a: i2c1 { 404091cf598SEddie Huang pins1 { 405091cf598SEddie Huang pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 406091cf598SEddie Huang <MT8173_PIN_126_SCL1__FUNC_SCL1>; 407091cf598SEddie Huang bias-disable; 408091cf598SEddie Huang }; 409091cf598SEddie Huang }; 410091cf598SEddie Huang 411091cf598SEddie Huang i2c2_pins_a: i2c2 { 412091cf598SEddie Huang pins1 { 413091cf598SEddie Huang pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 414091cf598SEddie Huang <MT8173_PIN_44_SCL2__FUNC_SCL2>; 415091cf598SEddie Huang bias-disable; 416091cf598SEddie Huang }; 417091cf598SEddie Huang }; 418091cf598SEddie Huang 419091cf598SEddie Huang i2c3_pins_a: i2c3 { 420091cf598SEddie Huang pins1 { 421091cf598SEddie Huang pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 422091cf598SEddie Huang <MT8173_PIN_107_SCL3__FUNC_SCL3>; 423091cf598SEddie Huang bias-disable; 424091cf598SEddie Huang }; 425091cf598SEddie Huang }; 426091cf598SEddie Huang 427091cf598SEddie Huang i2c4_pins_a: i2c4 { 428091cf598SEddie Huang pins1 { 429091cf598SEddie Huang pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 430091cf598SEddie Huang <MT8173_PIN_134_SCL4__FUNC_SCL4>; 431091cf598SEddie Huang bias-disable; 432091cf598SEddie Huang }; 433091cf598SEddie Huang }; 434091cf598SEddie Huang 435091cf598SEddie Huang i2c6_pins_a: i2c6 { 436091cf598SEddie Huang pins1 { 437091cf598SEddie Huang pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 438091cf598SEddie Huang <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 439091cf598SEddie Huang bias-disable; 440091cf598SEddie Huang }; 441091cf598SEddie Huang }; 4426769b93cSYingjoe Chen }; 4436769b93cSYingjoe Chen 4446fc033b5SMatthias Brugger scpsys: power-controller@10006000 { 445c010ff53SSascha Hauer compatible = "mediatek,mt8173-scpsys"; 446c010ff53SSascha Hauer #power-domain-cells = <1>; 447c010ff53SSascha Hauer reg = <0 0x10006000 0 0x1000>; 448c010ff53SSascha Hauer clocks = <&clk26m>, 449e34573c9SJames Liao <&topckgen CLK_TOP_MM_SEL>, 450e34573c9SJames Liao <&topckgen CLK_TOP_VENC_SEL>, 451e34573c9SJames Liao <&topckgen CLK_TOP_VENC_LT_SEL>; 452e34573c9SJames Liao clock-names = "mfg", "mm", "venc", "venc_lt"; 453c010ff53SSascha Hauer infracfg = <&infracfg>; 454c010ff53SSascha Hauer }; 455c010ff53SSascha Hauer 45613421b3eSEddie Huang watchdog: watchdog@10007000 { 45713421b3eSEddie Huang compatible = "mediatek,mt8173-wdt", 45813421b3eSEddie Huang "mediatek,mt6589-wdt"; 45913421b3eSEddie Huang reg = <0 0x10007000 0 0x100>; 46013421b3eSEddie Huang }; 46113421b3eSEddie Huang 462b2c76e27SDaniel Kurtz timer: timer@10008000 { 463b2c76e27SDaniel Kurtz compatible = "mediatek,mt8173-timer", 464b2c76e27SDaniel Kurtz "mediatek,mt6577-timer"; 465b2c76e27SDaniel Kurtz reg = <0 0x10008000 0 0x1000>; 466b2c76e27SDaniel Kurtz interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 467b2c76e27SDaniel Kurtz clocks = <&infracfg CLK_INFRA_CLK_13M>, 468b2c76e27SDaniel Kurtz <&topckgen CLK_TOP_RTC_SEL>; 469b2c76e27SDaniel Kurtz }; 470b2c76e27SDaniel Kurtz 4716cf15fc2SSascha Hauer pwrap: pwrap@1000d000 { 4726cf15fc2SSascha Hauer compatible = "mediatek,mt8173-pwrap"; 4736cf15fc2SSascha Hauer reg = <0 0x1000d000 0 0x1000>; 4746cf15fc2SSascha Hauer reg-names = "pwrap"; 4756cf15fc2SSascha Hauer interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 4766cf15fc2SSascha Hauer resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 4776cf15fc2SSascha Hauer reset-names = "pwrap"; 4786cf15fc2SSascha Hauer clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 4796cf15fc2SSascha Hauer clock-names = "spi", "wrap"; 4806cf15fc2SSascha Hauer }; 4816cf15fc2SSascha Hauer 482a10b57f4SCK Hu cec: cec@10013000 { 483a10b57f4SCK Hu compatible = "mediatek,mt8173-cec"; 484a10b57f4SCK Hu reg = <0 0x10013000 0 0xbc>; 485a10b57f4SCK Hu interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; 486a10b57f4SCK Hu clocks = <&infracfg CLK_INFRA_CEC>; 487a10b57f4SCK Hu status = "disabled"; 488a10b57f4SCK Hu }; 489a10b57f4SCK Hu 490404b2819SAndrew-CT Chen vpu: vpu@10020000 { 491404b2819SAndrew-CT Chen compatible = "mediatek,mt8173-vpu"; 492404b2819SAndrew-CT Chen reg = <0 0x10020000 0 0x30000>, 493404b2819SAndrew-CT Chen <0 0x10050000 0 0x100>; 494404b2819SAndrew-CT Chen reg-names = "tcm", "cfg_reg"; 495404b2819SAndrew-CT Chen interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 496404b2819SAndrew-CT Chen clocks = <&topckgen CLK_TOP_SCP_SEL>; 497404b2819SAndrew-CT Chen clock-names = "main"; 498404b2819SAndrew-CT Chen memory-region = <&vpu_dma_reserved>; 499404b2819SAndrew-CT Chen }; 500404b2819SAndrew-CT Chen 501b3a37248SEddie Huang sysirq: intpol-controller@10200620 { 502b3a37248SEddie Huang compatible = "mediatek,mt8173-sysirq", 503b3a37248SEddie Huang "mediatek,mt6577-sysirq"; 504b3a37248SEddie Huang interrupt-controller; 505b3a37248SEddie Huang #interrupt-cells = <3>; 506b3a37248SEddie Huang interrupt-parent = <&gic>; 507b3a37248SEddie Huang reg = <0 0x10200620 0 0x20>; 508b3a37248SEddie Huang }; 509b3a37248SEddie Huang 5105ff6b3a6SYong Wu iommu: iommu@10205000 { 5115ff6b3a6SYong Wu compatible = "mediatek,mt8173-m4u"; 5125ff6b3a6SYong Wu reg = <0 0x10205000 0 0x1000>; 5135ff6b3a6SYong Wu interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 5145ff6b3a6SYong Wu clocks = <&infracfg CLK_INFRA_M4U>; 5155ff6b3a6SYong Wu clock-names = "bclk"; 5165ff6b3a6SYong Wu mediatek,larbs = <&larb0 &larb1 &larb2 5175ff6b3a6SYong Wu &larb3 &larb4 &larb5>; 5185ff6b3a6SYong Wu #iommu-cells = <1>; 5195ff6b3a6SYong Wu }; 5205ff6b3a6SYong Wu 52193e9f5eeSandrew-ct.chen@mediatek.com efuse: efuse@10206000 { 52293e9f5eeSandrew-ct.chen@mediatek.com compatible = "mediatek,mt8173-efuse"; 52393e9f5eeSandrew-ct.chen@mediatek.com reg = <0 0x10206000 0 0x1000>; 5246de18454Sdawei.chien@mediatek.com #address-cells = <1>; 5256de18454Sdawei.chien@mediatek.com #size-cells = <1>; 5266de18454Sdawei.chien@mediatek.com thermal_calibration: calib@528 { 5276de18454Sdawei.chien@mediatek.com reg = <0x528 0xc>; 5286de18454Sdawei.chien@mediatek.com }; 52993e9f5eeSandrew-ct.chen@mediatek.com }; 53093e9f5eeSandrew-ct.chen@mediatek.com 531f2ce7014SSascha Hauer apmixedsys: clock-controller@10209000 { 532f2ce7014SSascha Hauer compatible = "mediatek,mt8173-apmixedsys"; 533f2ce7014SSascha Hauer reg = <0 0x10209000 0 0x1000>; 534f2ce7014SSascha Hauer #clock-cells = <1>; 535f2ce7014SSascha Hauer }; 536f2ce7014SSascha Hauer 537a10b57f4SCK Hu hdmi_phy: hdmi-phy@10209100 { 538a10b57f4SCK Hu compatible = "mediatek,mt8173-hdmi-phy"; 539a10b57f4SCK Hu reg = <0 0x10209100 0 0x24>; 540a10b57f4SCK Hu clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; 541a10b57f4SCK Hu clock-names = "pll_ref"; 542a10b57f4SCK Hu clock-output-names = "hdmitx_dig_cts"; 543a10b57f4SCK Hu mediatek,ibias = <0xa>; 544a10b57f4SCK Hu mediatek,ibias_up = <0x1c>; 545a10b57f4SCK Hu #clock-cells = <0>; 546a10b57f4SCK Hu #phy-cells = <0>; 547a10b57f4SCK Hu status = "disabled"; 548a10b57f4SCK Hu }; 549a10b57f4SCK Hu 550c2e66b8fSHoulong Wei gce: mailbox@10212000 { 551c2e66b8fSHoulong Wei compatible = "mediatek,mt8173-gce"; 552c2e66b8fSHoulong Wei reg = <0 0x10212000 0 0x1000>; 553c2e66b8fSHoulong Wei interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 554c2e66b8fSHoulong Wei clocks = <&infracfg CLK_INFRA_GCE>; 555c2e66b8fSHoulong Wei clock-names = "gce"; 556eb4a01afSHsin-Yi Wang #mbox-cells = <2>; 557c2e66b8fSHoulong Wei }; 558c2e66b8fSHoulong Wei 55981ad4dbaSCK Hu mipi_tx0: mipi-dphy@10215000 { 56081ad4dbaSCK Hu compatible = "mediatek,mt8173-mipi-tx"; 56181ad4dbaSCK Hu reg = <0 0x10215000 0 0x1000>; 56281ad4dbaSCK Hu clocks = <&clk26m>; 56381ad4dbaSCK Hu clock-output-names = "mipi_tx0_pll"; 56481ad4dbaSCK Hu #clock-cells = <0>; 56581ad4dbaSCK Hu #phy-cells = <0>; 56681ad4dbaSCK Hu status = "disabled"; 56781ad4dbaSCK Hu }; 56881ad4dbaSCK Hu 56981ad4dbaSCK Hu mipi_tx1: mipi-dphy@10216000 { 57081ad4dbaSCK Hu compatible = "mediatek,mt8173-mipi-tx"; 57181ad4dbaSCK Hu reg = <0 0x10216000 0 0x1000>; 57281ad4dbaSCK Hu clocks = <&clk26m>; 57381ad4dbaSCK Hu clock-output-names = "mipi_tx1_pll"; 57481ad4dbaSCK Hu #clock-cells = <0>; 57581ad4dbaSCK Hu #phy-cells = <0>; 57681ad4dbaSCK Hu status = "disabled"; 57781ad4dbaSCK Hu }; 57881ad4dbaSCK Hu 57972b29215SHsin-Yi Wang gic: interrupt-controller@10221000 { 580b3a37248SEddie Huang compatible = "arm,gic-400"; 581b3a37248SEddie Huang #interrupt-cells = <3>; 582b3a37248SEddie Huang interrupt-parent = <&gic>; 583b3a37248SEddie Huang interrupt-controller; 584b3a37248SEddie Huang reg = <0 0x10221000 0 0x1000>, 585b3a37248SEddie Huang <0 0x10222000 0 0x2000>, 586b3a37248SEddie Huang <0 0x10224000 0 0x2000>, 587b3a37248SEddie Huang <0 0x10226000 0 0x2000>; 588b3a37248SEddie Huang interrupts = <GIC_PPI 9 589b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 590b3a37248SEddie Huang }; 591b3a37248SEddie Huang 592748c7d4dSSascha Hauer auxadc: auxadc@11001000 { 593748c7d4dSSascha Hauer compatible = "mediatek,mt8173-auxadc"; 594748c7d4dSSascha Hauer reg = <0 0x11001000 0 0x1000>; 595a3207d64SMatthias Brugger clocks = <&pericfg CLK_PERI_AUXADC>; 596a3207d64SMatthias Brugger clock-names = "main"; 597a3207d64SMatthias Brugger #io-channel-cells = <1>; 598748c7d4dSSascha Hauer }; 599748c7d4dSSascha Hauer 600b3a37248SEddie Huang uart0: serial@11002000 { 601b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 602b3a37248SEddie Huang "mediatek,mt6577-uart"; 603b3a37248SEddie Huang reg = <0 0x11002000 0 0x400>; 604b3a37248SEddie Huang interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 6050e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 6060e84faa1SSascha Hauer clock-names = "baud", "bus"; 607b3a37248SEddie Huang status = "disabled"; 608b3a37248SEddie Huang }; 609b3a37248SEddie Huang 610b3a37248SEddie Huang uart1: serial@11003000 { 611b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 612b3a37248SEddie Huang "mediatek,mt6577-uart"; 613b3a37248SEddie Huang reg = <0 0x11003000 0 0x400>; 614b3a37248SEddie Huang interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 6150e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 6160e84faa1SSascha Hauer clock-names = "baud", "bus"; 617b3a37248SEddie Huang status = "disabled"; 618b3a37248SEddie Huang }; 619b3a37248SEddie Huang 620b3a37248SEddie Huang uart2: serial@11004000 { 621b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 622b3a37248SEddie Huang "mediatek,mt6577-uart"; 623b3a37248SEddie Huang reg = <0 0x11004000 0 0x400>; 624b3a37248SEddie Huang interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 6250e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 6260e84faa1SSascha Hauer clock-names = "baud", "bus"; 627b3a37248SEddie Huang status = "disabled"; 628b3a37248SEddie Huang }; 629b3a37248SEddie Huang 630b3a37248SEddie Huang uart3: serial@11005000 { 631b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 632b3a37248SEddie Huang "mediatek,mt6577-uart"; 633b3a37248SEddie Huang reg = <0 0x11005000 0 0x400>; 634b3a37248SEddie Huang interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 6350e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 6360e84faa1SSascha Hauer clock-names = "baud", "bus"; 637b3a37248SEddie Huang status = "disabled"; 638b3a37248SEddie Huang }; 639091cf598SEddie Huang 640091cf598SEddie Huang i2c0: i2c@11007000 { 641091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 642091cf598SEddie Huang reg = <0 0x11007000 0 0x70>, 643091cf598SEddie Huang <0 0x11000100 0 0x80>; 644091cf598SEddie Huang interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 645091cf598SEddie Huang clock-div = <16>; 646091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C0>, 647091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 648091cf598SEddie Huang clock-names = "main", "dma"; 649091cf598SEddie Huang pinctrl-names = "default"; 650091cf598SEddie Huang pinctrl-0 = <&i2c0_pins_a>; 651091cf598SEddie Huang #address-cells = <1>; 652091cf598SEddie Huang #size-cells = <0>; 653091cf598SEddie Huang status = "disabled"; 654091cf598SEddie Huang }; 655091cf598SEddie Huang 656091cf598SEddie Huang i2c1: i2c@11008000 { 657091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 658091cf598SEddie Huang reg = <0 0x11008000 0 0x70>, 659091cf598SEddie Huang <0 0x11000180 0 0x80>; 660091cf598SEddie Huang interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 661091cf598SEddie Huang clock-div = <16>; 662091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C1>, 663091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 664091cf598SEddie Huang clock-names = "main", "dma"; 665091cf598SEddie Huang pinctrl-names = "default"; 666091cf598SEddie Huang pinctrl-0 = <&i2c1_pins_a>; 667091cf598SEddie Huang #address-cells = <1>; 668091cf598SEddie Huang #size-cells = <0>; 669091cf598SEddie Huang status = "disabled"; 670091cf598SEddie Huang }; 671091cf598SEddie Huang 672091cf598SEddie Huang i2c2: i2c@11009000 { 673091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 674091cf598SEddie Huang reg = <0 0x11009000 0 0x70>, 675091cf598SEddie Huang <0 0x11000200 0 0x80>; 676091cf598SEddie Huang interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 677091cf598SEddie Huang clock-div = <16>; 678091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C2>, 679091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 680091cf598SEddie Huang clock-names = "main", "dma"; 681091cf598SEddie Huang pinctrl-names = "default"; 682091cf598SEddie Huang pinctrl-0 = <&i2c2_pins_a>; 683091cf598SEddie Huang #address-cells = <1>; 684091cf598SEddie Huang #size-cells = <0>; 685091cf598SEddie Huang status = "disabled"; 686091cf598SEddie Huang }; 687091cf598SEddie Huang 688b0c936f5SLeilk Liu spi: spi@1100a000 { 689b0c936f5SLeilk Liu compatible = "mediatek,mt8173-spi"; 690b0c936f5SLeilk Liu #address-cells = <1>; 691b0c936f5SLeilk Liu #size-cells = <0>; 692b0c936f5SLeilk Liu reg = <0 0x1100a000 0 0x1000>; 693b0c936f5SLeilk Liu interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 694b0c936f5SLeilk Liu clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 695b0c936f5SLeilk Liu <&topckgen CLK_TOP_SPI_SEL>, 696b0c936f5SLeilk Liu <&pericfg CLK_PERI_SPI0>; 697b0c936f5SLeilk Liu clock-names = "parent-clk", "sel-clk", "spi-clk"; 698b0c936f5SLeilk Liu status = "disabled"; 699b0c936f5SLeilk Liu }; 700b0c936f5SLeilk Liu 701748c7d4dSSascha Hauer thermal: thermal@1100b000 { 702748c7d4dSSascha Hauer #thermal-sensor-cells = <0>; 703748c7d4dSSascha Hauer compatible = "mediatek,mt8173-thermal"; 704748c7d4dSSascha Hauer reg = <0 0x1100b000 0 0x1000>; 705748c7d4dSSascha Hauer interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 706748c7d4dSSascha Hauer clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 707748c7d4dSSascha Hauer clock-names = "therm", "auxadc"; 708748c7d4dSSascha Hauer resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 709748c7d4dSSascha Hauer mediatek,auxadc = <&auxadc>; 710748c7d4dSSascha Hauer mediatek,apmixedsys = <&apmixedsys>; 7116de18454Sdawei.chien@mediatek.com nvmem-cells = <&thermal_calibration>; 7126de18454Sdawei.chien@mediatek.com nvmem-cell-names = "calibration-data"; 713748c7d4dSSascha Hauer }; 714748c7d4dSSascha Hauer 71586cb8a88SBayi Cheng nor_flash: spi@1100d000 { 71686cb8a88SBayi Cheng compatible = "mediatek,mt8173-nor"; 71786cb8a88SBayi Cheng reg = <0 0x1100d000 0 0xe0>; 71886cb8a88SBayi Cheng clocks = <&pericfg CLK_PERI_SPI>, 71986cb8a88SBayi Cheng <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 72086cb8a88SBayi Cheng clock-names = "spi", "sf"; 72186cb8a88SBayi Cheng #address-cells = <1>; 72286cb8a88SBayi Cheng #size-cells = <0>; 72386cb8a88SBayi Cheng status = "disabled"; 72486cb8a88SBayi Cheng }; 72586cb8a88SBayi Cheng 7261ee35c05SYingjoe Chen i2c3: i2c@11010000 { 727091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 728091cf598SEddie Huang reg = <0 0x11010000 0 0x70>, 729091cf598SEddie Huang <0 0x11000280 0 0x80>; 730091cf598SEddie Huang interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 731091cf598SEddie Huang clock-div = <16>; 732091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C3>, 733091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 734091cf598SEddie Huang clock-names = "main", "dma"; 735091cf598SEddie Huang pinctrl-names = "default"; 736091cf598SEddie Huang pinctrl-0 = <&i2c3_pins_a>; 737091cf598SEddie Huang #address-cells = <1>; 738091cf598SEddie Huang #size-cells = <0>; 739091cf598SEddie Huang status = "disabled"; 740091cf598SEddie Huang }; 741091cf598SEddie Huang 7421ee35c05SYingjoe Chen i2c4: i2c@11011000 { 743091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 744091cf598SEddie Huang reg = <0 0x11011000 0 0x70>, 745091cf598SEddie Huang <0 0x11000300 0 0x80>; 746091cf598SEddie Huang interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 747091cf598SEddie Huang clock-div = <16>; 748091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C4>, 749091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 750091cf598SEddie Huang clock-names = "main", "dma"; 751091cf598SEddie Huang pinctrl-names = "default"; 752091cf598SEddie Huang pinctrl-0 = <&i2c4_pins_a>; 753091cf598SEddie Huang #address-cells = <1>; 754091cf598SEddie Huang #size-cells = <0>; 755091cf598SEddie Huang status = "disabled"; 756091cf598SEddie Huang }; 757091cf598SEddie Huang 758a10b57f4SCK Hu hdmiddc0: i2c@11012000 { 759a10b57f4SCK Hu compatible = "mediatek,mt8173-hdmi-ddc"; 760a10b57f4SCK Hu interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 761a10b57f4SCK Hu reg = <0 0x11012000 0 0x1C>; 762a10b57f4SCK Hu clocks = <&pericfg CLK_PERI_I2C5>; 763a10b57f4SCK Hu clock-names = "ddc-i2c"; 764a10b57f4SCK Hu }; 765a10b57f4SCK Hu 7661ee35c05SYingjoe Chen i2c6: i2c@11013000 { 767091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 768091cf598SEddie Huang reg = <0 0x11013000 0 0x70>, 769091cf598SEddie Huang <0 0x11000080 0 0x80>; 770091cf598SEddie Huang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 771091cf598SEddie Huang clock-div = <16>; 772091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C6>, 773091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 774091cf598SEddie Huang clock-names = "main", "dma"; 775091cf598SEddie Huang pinctrl-names = "default"; 776091cf598SEddie Huang pinctrl-0 = <&i2c6_pins_a>; 777091cf598SEddie Huang #address-cells = <1>; 778091cf598SEddie Huang #size-cells = <0>; 779091cf598SEddie Huang status = "disabled"; 780091cf598SEddie Huang }; 781c02e0e86SKoro Chen 782c02e0e86SKoro Chen afe: audio-controller@11220000 { 783c02e0e86SKoro Chen compatible = "mediatek,mt8173-afe-pcm"; 784c02e0e86SKoro Chen reg = <0 0x11220000 0 0x1000>; 785c02e0e86SKoro Chen interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 786c02e0e86SKoro Chen power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; 787c02e0e86SKoro Chen clocks = <&infracfg CLK_INFRA_AUDIO>, 788c02e0e86SKoro Chen <&topckgen CLK_TOP_AUDIO_SEL>, 789c02e0e86SKoro Chen <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 790c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL1_DIV0>, 791c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL2_DIV0>, 792c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S0_M_SEL>, 793c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S1_M_SEL>, 794c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S2_M_SEL>, 795c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S3_M_SEL>, 796c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S3_B_SEL>; 797c02e0e86SKoro Chen clock-names = "infra_sys_audio_clk", 798c02e0e86SKoro Chen "top_pdn_audio", 799c02e0e86SKoro Chen "top_pdn_aud_intbus", 800c02e0e86SKoro Chen "bck0", 801c02e0e86SKoro Chen "bck1", 802c02e0e86SKoro Chen "i2s0_m", 803c02e0e86SKoro Chen "i2s1_m", 804c02e0e86SKoro Chen "i2s2_m", 805c02e0e86SKoro Chen "i2s3_m", 806c02e0e86SKoro Chen "i2s3_b"; 807c02e0e86SKoro Chen assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 808c02e0e86SKoro Chen <&topckgen CLK_TOP_AUD_2_SEL>; 809c02e0e86SKoro Chen assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 810c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL2>; 811c02e0e86SKoro Chen }; 8129719fa5aSEddie Huang 8139719fa5aSEddie Huang mmc0: mmc@11230000 { 814689362b3SChaotian Jing compatible = "mediatek,mt8173-mmc"; 8159719fa5aSEddie Huang reg = <0 0x11230000 0 0x1000>; 8169719fa5aSEddie Huang interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 8179719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_0>, 8189719fa5aSEddie Huang <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 8199719fa5aSEddie Huang clock-names = "source", "hclk"; 8209719fa5aSEddie Huang status = "disabled"; 8219719fa5aSEddie Huang }; 8229719fa5aSEddie Huang 8239719fa5aSEddie Huang mmc1: mmc@11240000 { 824689362b3SChaotian Jing compatible = "mediatek,mt8173-mmc"; 8259719fa5aSEddie Huang reg = <0 0x11240000 0 0x1000>; 8269719fa5aSEddie Huang interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 8279719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_1>, 8289719fa5aSEddie Huang <&topckgen CLK_TOP_AXI_SEL>; 8299719fa5aSEddie Huang clock-names = "source", "hclk"; 8309719fa5aSEddie Huang status = "disabled"; 8319719fa5aSEddie Huang }; 8329719fa5aSEddie Huang 8339719fa5aSEddie Huang mmc2: mmc@11250000 { 834689362b3SChaotian Jing compatible = "mediatek,mt8173-mmc"; 8359719fa5aSEddie Huang reg = <0 0x11250000 0 0x1000>; 8369719fa5aSEddie Huang interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 8379719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_2>, 8389719fa5aSEddie Huang <&topckgen CLK_TOP_AXI_SEL>; 8399719fa5aSEddie Huang clock-names = "source", "hclk"; 8409719fa5aSEddie Huang status = "disabled"; 8419719fa5aSEddie Huang }; 8429719fa5aSEddie Huang 8439719fa5aSEddie Huang mmc3: mmc@11260000 { 844689362b3SChaotian Jing compatible = "mediatek,mt8173-mmc"; 8459719fa5aSEddie Huang reg = <0 0x11260000 0 0x1000>; 8469719fa5aSEddie Huang interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 8479719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_3>, 8489719fa5aSEddie Huang <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 8499719fa5aSEddie Huang clock-names = "source", "hclk"; 8509719fa5aSEddie Huang status = "disabled"; 8519719fa5aSEddie Huang }; 85267e56c56SJames Liao 853c0891284SChunfeng Yun ssusb: usb@11271000 { 854c0891284SChunfeng Yun compatible = "mediatek,mt8173-mtu3"; 855c0891284SChunfeng Yun reg = <0 0x11271000 0 0x3000>, 856bfcce47aSChunfeng Yun <0 0x11280700 0 0x0100>; 857c0891284SChunfeng Yun reg-names = "mac", "ippc"; 858c0891284SChunfeng Yun interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>; 859ebf61c63Schunfeng.yun@mediatek.com phys = <&u2port0 PHY_TYPE_USB2>, 860ebf61c63Schunfeng.yun@mediatek.com <&u3port0 PHY_TYPE_USB3>, 861ebf61c63Schunfeng.yun@mediatek.com <&u2port1 PHY_TYPE_USB2>; 862bfcce47aSChunfeng Yun power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 863cf1fcd45SChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 864cf1fcd45SChunfeng Yun clock-names = "sys_ck", "ref_ck"; 865cf1fcd45SChunfeng Yun mediatek,syscon-wakeup = <&pericfg 0x400 1>; 866c0891284SChunfeng Yun #address-cells = <2>; 867c0891284SChunfeng Yun #size-cells = <2>; 868c0891284SChunfeng Yun ranges; 869c0891284SChunfeng Yun status = "disabled"; 870c0891284SChunfeng Yun 871c0891284SChunfeng Yun usb_host: xhci@11270000 { 872c0891284SChunfeng Yun compatible = "mediatek,mt8173-xhci"; 873c0891284SChunfeng Yun reg = <0 0x11270000 0 0x1000>; 874c0891284SChunfeng Yun reg-names = "mac"; 875c0891284SChunfeng Yun interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 876c0891284SChunfeng Yun power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 877cb6efc7bSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 878cb6efc7bSChunfeng Yun clock-names = "sys_ck", "ref_ck"; 879c0891284SChunfeng Yun status = "disabled"; 880c0891284SChunfeng Yun }; 881bfcce47aSChunfeng Yun }; 882bfcce47aSChunfeng Yun 883bfcce47aSChunfeng Yun u3phy: usb-phy@11290000 { 884bfcce47aSChunfeng Yun compatible = "mediatek,mt8173-u3phy"; 885bfcce47aSChunfeng Yun reg = <0 0x11290000 0 0x800>; 886bfcce47aSChunfeng Yun #address-cells = <2>; 887bfcce47aSChunfeng Yun #size-cells = <2>; 888bfcce47aSChunfeng Yun ranges; 889bfcce47aSChunfeng Yun status = "okay"; 890bfcce47aSChunfeng Yun 891ebf61c63Schunfeng.yun@mediatek.com u2port0: usb-phy@11290800 { 892ebf61c63Schunfeng.yun@mediatek.com reg = <0 0x11290800 0 0x100>; 89310f84a7aSchunfeng.yun@mediatek.com clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 89410f84a7aSchunfeng.yun@mediatek.com clock-names = "ref"; 895bfcce47aSChunfeng Yun #phy-cells = <1>; 896bfcce47aSChunfeng Yun status = "okay"; 897bfcce47aSChunfeng Yun }; 898bfcce47aSChunfeng Yun 899ebf61c63Schunfeng.yun@mediatek.com u3port0: usb-phy@11290900 { 900ebf61c63Schunfeng.yun@mediatek.com reg = <0 0x11290900 0 0x700>; 90110f84a7aSchunfeng.yun@mediatek.com clocks = <&clk26m>; 90210f84a7aSchunfeng.yun@mediatek.com clock-names = "ref"; 903ebf61c63Schunfeng.yun@mediatek.com #phy-cells = <1>; 904ebf61c63Schunfeng.yun@mediatek.com status = "okay"; 905ebf61c63Schunfeng.yun@mediatek.com }; 906ebf61c63Schunfeng.yun@mediatek.com 907ebf61c63Schunfeng.yun@mediatek.com u2port1: usb-phy@11291000 { 908ebf61c63Schunfeng.yun@mediatek.com reg = <0 0x11291000 0 0x100>; 90910f84a7aSchunfeng.yun@mediatek.com clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 91010f84a7aSchunfeng.yun@mediatek.com clock-names = "ref"; 911bfcce47aSChunfeng Yun #phy-cells = <1>; 912bfcce47aSChunfeng Yun status = "okay"; 913bfcce47aSChunfeng Yun }; 914bfcce47aSChunfeng Yun }; 915bfcce47aSChunfeng Yun 91667e56c56SJames Liao mmsys: clock-controller@14000000 { 91767e56c56SJames Liao compatible = "mediatek,mt8173-mmsys", "syscon"; 91867e56c56SJames Liao reg = <0 0x14000000 0 0x1000>; 91981ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 920fc6634acSBibby Hsieh assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; 921fc6634acSBibby Hsieh assigned-clock-rates = <400000000>; 92267e56c56SJames Liao #clock-cells = <1>; 923eb4a01afSHsin-Yi Wang mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 924eb4a01afSHsin-Yi Wang <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 925eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 92667e56c56SJames Liao }; 92767e56c56SJames Liao 928989b292aSMinghsiu Tsai mdp_rdma0: rdma@14001000 { 9298127881fSDaniel Kurtz compatible = "mediatek,mt8173-mdp-rdma", 9308127881fSDaniel Kurtz "mediatek,mt8173-mdp"; 931989b292aSMinghsiu Tsai reg = <0 0x14001000 0 0x1000>; 932989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RDMA0>, 933989b292aSMinghsiu Tsai <&mmsys CLK_MM_MUTEX_32K>; 934989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 935989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_RDMA0>; 936989b292aSMinghsiu Tsai mediatek,larb = <&larb0>; 9378127881fSDaniel Kurtz mediatek,vpu = <&vpu>; 938989b292aSMinghsiu Tsai }; 939989b292aSMinghsiu Tsai 940989b292aSMinghsiu Tsai mdp_rdma1: rdma@14002000 { 941989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rdma"; 942989b292aSMinghsiu Tsai reg = <0 0x14002000 0 0x1000>; 943989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RDMA1>, 944989b292aSMinghsiu Tsai <&mmsys CLK_MM_MUTEX_32K>; 945989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 946989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_RDMA1>; 947989b292aSMinghsiu Tsai mediatek,larb = <&larb4>; 948989b292aSMinghsiu Tsai }; 949989b292aSMinghsiu Tsai 950989b292aSMinghsiu Tsai mdp_rsz0: rsz@14003000 { 951989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rsz"; 952989b292aSMinghsiu Tsai reg = <0 0x14003000 0 0x1000>; 953989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RSZ0>; 954989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 955989b292aSMinghsiu Tsai }; 956989b292aSMinghsiu Tsai 957989b292aSMinghsiu Tsai mdp_rsz1: rsz@14004000 { 958989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rsz"; 959989b292aSMinghsiu Tsai reg = <0 0x14004000 0 0x1000>; 960989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RSZ1>; 961989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 962989b292aSMinghsiu Tsai }; 963989b292aSMinghsiu Tsai 964989b292aSMinghsiu Tsai mdp_rsz2: rsz@14005000 { 965989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rsz"; 966989b292aSMinghsiu Tsai reg = <0 0x14005000 0 0x1000>; 967989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RSZ2>; 968989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 969989b292aSMinghsiu Tsai }; 970989b292aSMinghsiu Tsai 971989b292aSMinghsiu Tsai mdp_wdma0: wdma@14006000 { 972989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-wdma"; 973989b292aSMinghsiu Tsai reg = <0 0x14006000 0 0x1000>; 974989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_WDMA>; 975989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 976989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_WDMA>; 977989b292aSMinghsiu Tsai mediatek,larb = <&larb0>; 978989b292aSMinghsiu Tsai }; 979989b292aSMinghsiu Tsai 980989b292aSMinghsiu Tsai mdp_wrot0: wrot@14007000 { 981989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-wrot"; 982989b292aSMinghsiu Tsai reg = <0 0x14007000 0 0x1000>; 983989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_WROT0>; 984989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 985989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_WROT0>; 986989b292aSMinghsiu Tsai mediatek,larb = <&larb0>; 987989b292aSMinghsiu Tsai }; 988989b292aSMinghsiu Tsai 989989b292aSMinghsiu Tsai mdp_wrot1: wrot@14008000 { 990989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-wrot"; 991989b292aSMinghsiu Tsai reg = <0 0x14008000 0 0x1000>; 992989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_WROT1>; 993989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 994989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_WROT1>; 995989b292aSMinghsiu Tsai mediatek,larb = <&larb4>; 996989b292aSMinghsiu Tsai }; 997989b292aSMinghsiu Tsai 99881ad4dbaSCK Hu ovl0: ovl@1400c000 { 99981ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-ovl"; 100081ad4dbaSCK Hu reg = <0 0x1400c000 0 0x1000>; 100181ad4dbaSCK Hu interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 100281ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 100381ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_OVL0>; 100481ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_OVL0>; 100581ad4dbaSCK Hu mediatek,larb = <&larb0>; 1006eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 100781ad4dbaSCK Hu }; 100881ad4dbaSCK Hu 100981ad4dbaSCK Hu ovl1: ovl@1400d000 { 101081ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-ovl"; 101181ad4dbaSCK Hu reg = <0 0x1400d000 0 0x1000>; 101281ad4dbaSCK Hu interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; 101381ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 101481ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_OVL1>; 101581ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_OVL1>; 101681ad4dbaSCK Hu mediatek,larb = <&larb4>; 1017eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 101881ad4dbaSCK Hu }; 101981ad4dbaSCK Hu 102081ad4dbaSCK Hu rdma0: rdma@1400e000 { 102181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-rdma"; 102281ad4dbaSCK Hu reg = <0 0x1400e000 0 0x1000>; 102381ad4dbaSCK Hu interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 102481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 102581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_RDMA0>; 102681ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_RDMA0>; 102781ad4dbaSCK Hu mediatek,larb = <&larb0>; 1028eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 102981ad4dbaSCK Hu }; 103081ad4dbaSCK Hu 103181ad4dbaSCK Hu rdma1: rdma@1400f000 { 103281ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-rdma"; 103381ad4dbaSCK Hu reg = <0 0x1400f000 0 0x1000>; 103481ad4dbaSCK Hu interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; 103581ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 103681ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_RDMA1>; 103781ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_RDMA1>; 103881ad4dbaSCK Hu mediatek,larb = <&larb4>; 1039eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; 104081ad4dbaSCK Hu }; 104181ad4dbaSCK Hu 104281ad4dbaSCK Hu rdma2: rdma@14010000 { 104381ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-rdma"; 104481ad4dbaSCK Hu reg = <0 0x14010000 0 0x1000>; 104581ad4dbaSCK Hu interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; 104681ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 104781ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_RDMA2>; 104881ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_RDMA2>; 104981ad4dbaSCK Hu mediatek,larb = <&larb4>; 1050eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; 105181ad4dbaSCK Hu }; 105281ad4dbaSCK Hu 105381ad4dbaSCK Hu wdma0: wdma@14011000 { 105481ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-wdma"; 105581ad4dbaSCK Hu reg = <0 0x14011000 0 0x1000>; 105681ad4dbaSCK Hu interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 105781ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 105881ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_WDMA0>; 105981ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_WDMA0>; 106081ad4dbaSCK Hu mediatek,larb = <&larb0>; 1061eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 106281ad4dbaSCK Hu }; 106381ad4dbaSCK Hu 106481ad4dbaSCK Hu wdma1: wdma@14012000 { 106581ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-wdma"; 106681ad4dbaSCK Hu reg = <0 0x14012000 0 0x1000>; 106781ad4dbaSCK Hu interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; 106881ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 106981ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_WDMA1>; 107081ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_WDMA1>; 107181ad4dbaSCK Hu mediatek,larb = <&larb4>; 1072eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; 107381ad4dbaSCK Hu }; 107481ad4dbaSCK Hu 107581ad4dbaSCK Hu color0: color@14013000 { 107681ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-color"; 107781ad4dbaSCK Hu reg = <0 0x14013000 0 0x1000>; 107881ad4dbaSCK Hu interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; 107981ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 108081ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1081eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>; 108281ad4dbaSCK Hu }; 108381ad4dbaSCK Hu 108481ad4dbaSCK Hu color1: color@14014000 { 108581ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-color"; 108681ad4dbaSCK Hu reg = <0 0x14014000 0 0x1000>; 108781ad4dbaSCK Hu interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 108881ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 108981ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_COLOR1>; 1090eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; 109181ad4dbaSCK Hu }; 109281ad4dbaSCK Hu 109381ad4dbaSCK Hu aal@14015000 { 109481ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-aal"; 109581ad4dbaSCK Hu reg = <0 0x14015000 0 0x1000>; 109681ad4dbaSCK Hu interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 109781ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 109881ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_AAL>; 1099eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; 110081ad4dbaSCK Hu }; 110181ad4dbaSCK Hu 110281ad4dbaSCK Hu gamma@14016000 { 110381ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-gamma"; 110481ad4dbaSCK Hu reg = <0 0x14016000 0 0x1000>; 110581ad4dbaSCK Hu interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 110681ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 110781ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_GAMMA>; 1108eb4a01afSHsin-Yi Wang mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; 110981ad4dbaSCK Hu }; 111081ad4dbaSCK Hu 111181ad4dbaSCK Hu merge@14017000 { 111281ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-merge"; 111381ad4dbaSCK Hu reg = <0 0x14017000 0 0x1000>; 111481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 111581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_MERGE>; 111681ad4dbaSCK Hu }; 111781ad4dbaSCK Hu 111881ad4dbaSCK Hu split0: split@14018000 { 111981ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-split"; 112081ad4dbaSCK Hu reg = <0 0x14018000 0 0x1000>; 112181ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 112281ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_SPLIT0>; 112381ad4dbaSCK Hu }; 112481ad4dbaSCK Hu 112581ad4dbaSCK Hu split1: split@14019000 { 112681ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-split"; 112781ad4dbaSCK Hu reg = <0 0x14019000 0 0x1000>; 112881ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 112981ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_SPLIT1>; 113081ad4dbaSCK Hu }; 113181ad4dbaSCK Hu 113281ad4dbaSCK Hu ufoe@1401a000 { 113381ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-ufoe"; 113481ad4dbaSCK Hu reg = <0 0x1401a000 0 0x1000>; 113581ad4dbaSCK Hu interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 113681ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 113781ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_UFOE>; 113881ad4dbaSCK Hu }; 113981ad4dbaSCK Hu 114081ad4dbaSCK Hu dsi0: dsi@1401b000 { 114181ad4dbaSCK Hu compatible = "mediatek,mt8173-dsi"; 114281ad4dbaSCK Hu reg = <0 0x1401b000 0 0x1000>; 114381ad4dbaSCK Hu interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 114481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 114581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DSI0_ENGINE>, 114681ad4dbaSCK Hu <&mmsys CLK_MM_DSI0_DIGITAL>, 114781ad4dbaSCK Hu <&mipi_tx0>; 114881ad4dbaSCK Hu clock-names = "engine", "digital", "hs"; 114981ad4dbaSCK Hu phys = <&mipi_tx0>; 115081ad4dbaSCK Hu phy-names = "dphy"; 115181ad4dbaSCK Hu status = "disabled"; 115281ad4dbaSCK Hu }; 115381ad4dbaSCK Hu 115481ad4dbaSCK Hu dsi1: dsi@1401c000 { 115581ad4dbaSCK Hu compatible = "mediatek,mt8173-dsi"; 115681ad4dbaSCK Hu reg = <0 0x1401c000 0 0x1000>; 115781ad4dbaSCK Hu interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 115881ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 115981ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DSI1_ENGINE>, 116081ad4dbaSCK Hu <&mmsys CLK_MM_DSI1_DIGITAL>, 116181ad4dbaSCK Hu <&mipi_tx1>; 116281ad4dbaSCK Hu clock-names = "engine", "digital", "hs"; 116381ad4dbaSCK Hu phy = <&mipi_tx1>; 116481ad4dbaSCK Hu phy-names = "dphy"; 116581ad4dbaSCK Hu status = "disabled"; 116681ad4dbaSCK Hu }; 116781ad4dbaSCK Hu 116881ad4dbaSCK Hu dpi0: dpi@1401d000 { 116981ad4dbaSCK Hu compatible = "mediatek,mt8173-dpi"; 117081ad4dbaSCK Hu reg = <0 0x1401d000 0 0x1000>; 117181ad4dbaSCK Hu interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 117281ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 117381ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DPI_PIXEL>, 117481ad4dbaSCK Hu <&mmsys CLK_MM_DPI_ENGINE>, 117581ad4dbaSCK Hu <&apmixedsys CLK_APMIXED_TVDPLL>; 117681ad4dbaSCK Hu clock-names = "pixel", "engine", "pll"; 117781ad4dbaSCK Hu status = "disabled"; 1178a10b57f4SCK Hu 1179a10b57f4SCK Hu port { 1180a10b57f4SCK Hu dpi0_out: endpoint { 1181a10b57f4SCK Hu remote-endpoint = <&hdmi0_in>; 1182a10b57f4SCK Hu }; 1183a10b57f4SCK Hu }; 118481ad4dbaSCK Hu }; 118581ad4dbaSCK Hu 118661aee934SYH Huang pwm0: pwm@1401e000 { 118761aee934SYH Huang compatible = "mediatek,mt8173-disp-pwm", 118861aee934SYH Huang "mediatek,mt6595-disp-pwm"; 118961aee934SYH Huang reg = <0 0x1401e000 0 0x1000>; 119061aee934SYH Huang #pwm-cells = <2>; 119161aee934SYH Huang clocks = <&mmsys CLK_MM_DISP_PWM026M>, 119261aee934SYH Huang <&mmsys CLK_MM_DISP_PWM0MM>; 119361aee934SYH Huang clock-names = "main", "mm"; 119461aee934SYH Huang status = "disabled"; 119561aee934SYH Huang }; 119661aee934SYH Huang 119761aee934SYH Huang pwm1: pwm@1401f000 { 119861aee934SYH Huang compatible = "mediatek,mt8173-disp-pwm", 119961aee934SYH Huang "mediatek,mt6595-disp-pwm"; 120061aee934SYH Huang reg = <0 0x1401f000 0 0x1000>; 120161aee934SYH Huang #pwm-cells = <2>; 120261aee934SYH Huang clocks = <&mmsys CLK_MM_DISP_PWM126M>, 120361aee934SYH Huang <&mmsys CLK_MM_DISP_PWM1MM>; 120461aee934SYH Huang clock-names = "main", "mm"; 120561aee934SYH Huang status = "disabled"; 120661aee934SYH Huang }; 120761aee934SYH Huang 120881ad4dbaSCK Hu mutex: mutex@14020000 { 120981ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-mutex"; 121081ad4dbaSCK Hu reg = <0 0x14020000 0 0x1000>; 121181ad4dbaSCK Hu interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 121281ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 121381ad4dbaSCK Hu clocks = <&mmsys CLK_MM_MUTEX_32K>; 1214eb4a01afSHsin-Yi Wang mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>, 1215eb4a01afSHsin-Yi Wang <CMDQ_EVENT_MUTEX1_STREAM_EOF>; 121681ad4dbaSCK Hu }; 121781ad4dbaSCK Hu 12185ff6b3a6SYong Wu larb0: larb@14021000 { 12195ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 12205ff6b3a6SYong Wu reg = <0 0x14021000 0 0x1000>; 12215ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 12225ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 12235ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_LARB0>, 12245ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_LARB0>; 12255ff6b3a6SYong Wu clock-names = "apb", "smi"; 12265ff6b3a6SYong Wu }; 12275ff6b3a6SYong Wu 12285ff6b3a6SYong Wu smi_common: smi@14022000 { 12295ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-common"; 12305ff6b3a6SYong Wu reg = <0 0x14022000 0 0x1000>; 12315ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 12325ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_COMMON>, 12335ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_COMMON>; 12345ff6b3a6SYong Wu clock-names = "apb", "smi"; 12355ff6b3a6SYong Wu }; 12365ff6b3a6SYong Wu 123781ad4dbaSCK Hu od@14023000 { 123881ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-od"; 123981ad4dbaSCK Hu reg = <0 0x14023000 0 0x1000>; 124081ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_OD>; 124181ad4dbaSCK Hu }; 124281ad4dbaSCK Hu 1243a10b57f4SCK Hu hdmi0: hdmi@14025000 { 1244a10b57f4SCK Hu compatible = "mediatek,mt8173-hdmi"; 1245a10b57f4SCK Hu reg = <0 0x14025000 0 0x400>; 1246a10b57f4SCK Hu interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>; 1247a10b57f4SCK Hu clocks = <&mmsys CLK_MM_HDMI_PIXEL>, 1248a10b57f4SCK Hu <&mmsys CLK_MM_HDMI_PLLCK>, 1249a10b57f4SCK Hu <&mmsys CLK_MM_HDMI_AUDIO>, 1250a10b57f4SCK Hu <&mmsys CLK_MM_HDMI_SPDIF>; 1251a10b57f4SCK Hu clock-names = "pixel", "pll", "bclk", "spdif"; 1252a10b57f4SCK Hu pinctrl-names = "default"; 1253a10b57f4SCK Hu pinctrl-0 = <&hdmi_pin>; 1254a10b57f4SCK Hu phys = <&hdmi_phy>; 1255a10b57f4SCK Hu phy-names = "hdmi"; 1256a10b57f4SCK Hu mediatek,syscon-hdmi = <&mmsys 0x900>; 1257a10b57f4SCK Hu assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; 1258a10b57f4SCK Hu assigned-clock-parents = <&hdmi_phy>; 1259a10b57f4SCK Hu status = "disabled"; 1260a10b57f4SCK Hu 1261a10b57f4SCK Hu ports { 1262a10b57f4SCK Hu #address-cells = <1>; 1263a10b57f4SCK Hu #size-cells = <0>; 1264a10b57f4SCK Hu 1265a10b57f4SCK Hu port@0 { 1266a10b57f4SCK Hu reg = <0>; 1267a10b57f4SCK Hu 1268a10b57f4SCK Hu hdmi0_in: endpoint { 1269a10b57f4SCK Hu remote-endpoint = <&dpi0_out>; 1270a10b57f4SCK Hu }; 1271a10b57f4SCK Hu }; 1272a10b57f4SCK Hu }; 1273a10b57f4SCK Hu }; 1274a10b57f4SCK Hu 12755ff6b3a6SYong Wu larb4: larb@14027000 { 12765ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 12775ff6b3a6SYong Wu reg = <0 0x14027000 0 0x1000>; 12785ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 12795ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 12805ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_LARB4>, 12815ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_LARB4>; 12825ff6b3a6SYong Wu clock-names = "apb", "smi"; 12835ff6b3a6SYong Wu }; 12845ff6b3a6SYong Wu 128567e56c56SJames Liao imgsys: clock-controller@15000000 { 128667e56c56SJames Liao compatible = "mediatek,mt8173-imgsys", "syscon"; 128767e56c56SJames Liao reg = <0 0x15000000 0 0x1000>; 128867e56c56SJames Liao #clock-cells = <1>; 128967e56c56SJames Liao }; 129067e56c56SJames Liao 12915ff6b3a6SYong Wu larb2: larb@15001000 { 12925ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 12935ff6b3a6SYong Wu reg = <0 0x15001000 0 0x1000>; 12945ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 12955ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>; 12965ff6b3a6SYong Wu clocks = <&imgsys CLK_IMG_LARB2_SMI>, 12975ff6b3a6SYong Wu <&imgsys CLK_IMG_LARB2_SMI>; 12985ff6b3a6SYong Wu clock-names = "apb", "smi"; 12995ff6b3a6SYong Wu }; 13005ff6b3a6SYong Wu 130167e56c56SJames Liao vdecsys: clock-controller@16000000 { 130267e56c56SJames Liao compatible = "mediatek,mt8173-vdecsys", "syscon"; 130367e56c56SJames Liao reg = <0 0x16000000 0 0x1000>; 130467e56c56SJames Liao #clock-cells = <1>; 130567e56c56SJames Liao }; 130667e56c56SJames Liao 130760eaae2bSTiffany Lin vcodec_dec: vcodec@16000000 { 130860eaae2bSTiffany Lin compatible = "mediatek,mt8173-vcodec-dec"; 130960eaae2bSTiffany Lin reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */ 131060eaae2bSTiffany Lin <0 0x16020000 0 0x1000>, /* VDEC_MISC */ 131160eaae2bSTiffany Lin <0 0x16021000 0 0x800>, /* VDEC_LD */ 131260eaae2bSTiffany Lin <0 0x16021800 0 0x800>, /* VDEC_TOP */ 131360eaae2bSTiffany Lin <0 0x16022000 0 0x1000>, /* VDEC_CM */ 131460eaae2bSTiffany Lin <0 0x16023000 0 0x1000>, /* VDEC_AD */ 131560eaae2bSTiffany Lin <0 0x16024000 0 0x1000>, /* VDEC_AV */ 131660eaae2bSTiffany Lin <0 0x16025000 0 0x1000>, /* VDEC_PP */ 131760eaae2bSTiffany Lin <0 0x16026800 0 0x800>, /* VDEC_HWD */ 131860eaae2bSTiffany Lin <0 0x16027000 0 0x800>, /* VDEC_HWQ */ 131960eaae2bSTiffany Lin <0 0x16027800 0 0x800>, /* VDEC_HWB */ 132060eaae2bSTiffany Lin <0 0x16028400 0 0x400>; /* VDEC_HWG */ 132160eaae2bSTiffany Lin interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; 132260eaae2bSTiffany Lin mediatek,larb = <&larb1>; 132360eaae2bSTiffany Lin iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, 132460eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_PP_EXT>, 132560eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, 132660eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, 132760eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, 132860eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, 132960eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, 133060eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; 133160eaae2bSTiffany Lin mediatek,vpu = <&vpu>; 133260eaae2bSTiffany Lin power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 133360eaae2bSTiffany Lin clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, 133460eaae2bSTiffany Lin <&topckgen CLK_TOP_UNIVPLL_D2>, 133560eaae2bSTiffany Lin <&topckgen CLK_TOP_CCI400_SEL>, 133660eaae2bSTiffany Lin <&topckgen CLK_TOP_VDEC_SEL>, 133760eaae2bSTiffany Lin <&topckgen CLK_TOP_VCODECPLL>, 133860eaae2bSTiffany Lin <&apmixedsys CLK_APMIXED_VENCPLL>, 133960eaae2bSTiffany Lin <&topckgen CLK_TOP_VENC_LT_SEL>, 134060eaae2bSTiffany Lin <&topckgen CLK_TOP_VCODECPLL_370P5>; 134160eaae2bSTiffany Lin clock-names = "vcodecpll", 134260eaae2bSTiffany Lin "univpll_d2", 134360eaae2bSTiffany Lin "clk_cci400_sel", 134460eaae2bSTiffany Lin "vdec_sel", 134560eaae2bSTiffany Lin "vdecpll", 134660eaae2bSTiffany Lin "vencpll", 134760eaae2bSTiffany Lin "venc_lt_sel", 134860eaae2bSTiffany Lin "vdec_bus_clk_src"; 1349fbbad028SYunfei Dong assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>, 1350fbbad028SYunfei Dong <&topckgen CLK_TOP_CCI400_SEL>, 1351fbbad028SYunfei Dong <&topckgen CLK_TOP_VDEC_SEL>, 1352fbbad028SYunfei Dong <&apmixedsys CLK_APMIXED_VCODECPLL>, 1353fbbad028SYunfei Dong <&apmixedsys CLK_APMIXED_VENCPLL>; 1354fbbad028SYunfei Dong assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>, 1355fbbad028SYunfei Dong <&topckgen CLK_TOP_UNIVPLL_D2>, 1356fbbad028SYunfei Dong <&topckgen CLK_TOP_VCODECPLL>; 1357fbbad028SYunfei Dong assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>; 135860eaae2bSTiffany Lin }; 135960eaae2bSTiffany Lin 13605ff6b3a6SYong Wu larb1: larb@16010000 { 13615ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 13625ff6b3a6SYong Wu reg = <0 0x16010000 0 0x1000>; 13635ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 13645ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 13655ff6b3a6SYong Wu clocks = <&vdecsys CLK_VDEC_CKEN>, 13665ff6b3a6SYong Wu <&vdecsys CLK_VDEC_LARB_CKEN>; 13675ff6b3a6SYong Wu clock-names = "apb", "smi"; 13685ff6b3a6SYong Wu }; 13695ff6b3a6SYong Wu 137067e56c56SJames Liao vencsys: clock-controller@18000000 { 137167e56c56SJames Liao compatible = "mediatek,mt8173-vencsys", "syscon"; 137267e56c56SJames Liao reg = <0 0x18000000 0 0x1000>; 137367e56c56SJames Liao #clock-cells = <1>; 137467e56c56SJames Liao }; 137567e56c56SJames Liao 13765ff6b3a6SYong Wu larb3: larb@18001000 { 13775ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 13785ff6b3a6SYong Wu reg = <0 0x18001000 0 0x1000>; 13795ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 13805ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 13815ff6b3a6SYong Wu clocks = <&vencsys CLK_VENC_CKE1>, 13825ff6b3a6SYong Wu <&vencsys CLK_VENC_CKE0>; 13835ff6b3a6SYong Wu clock-names = "apb", "smi"; 13845ff6b3a6SYong Wu }; 13855ff6b3a6SYong Wu 13868eb80252STiffany Lin vcodec_enc: vcodec@18002000 { 13878eb80252STiffany Lin compatible = "mediatek,mt8173-vcodec-enc"; 13888eb80252STiffany Lin reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */ 13898eb80252STiffany Lin <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ 13908eb80252STiffany Lin interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>, 13918eb80252STiffany Lin <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; 13928eb80252STiffany Lin mediatek,larb = <&larb3>, 13938eb80252STiffany Lin <&larb5>; 13948eb80252STiffany Lin iommus = <&iommu M4U_PORT_VENC_RCPU>, 13958eb80252STiffany Lin <&iommu M4U_PORT_VENC_REC>, 13968eb80252STiffany Lin <&iommu M4U_PORT_VENC_BSDMA>, 13978eb80252STiffany Lin <&iommu M4U_PORT_VENC_SV_COMV>, 13988eb80252STiffany Lin <&iommu M4U_PORT_VENC_RD_COMV>, 13998eb80252STiffany Lin <&iommu M4U_PORT_VENC_CUR_LUMA>, 14008eb80252STiffany Lin <&iommu M4U_PORT_VENC_CUR_CHROMA>, 14018eb80252STiffany Lin <&iommu M4U_PORT_VENC_REF_LUMA>, 14028eb80252STiffany Lin <&iommu M4U_PORT_VENC_REF_CHROMA>, 14038eb80252STiffany Lin <&iommu M4U_PORT_VENC_NBM_RDMA>, 14048eb80252STiffany Lin <&iommu M4U_PORT_VENC_NBM_WDMA>, 14058eb80252STiffany Lin <&iommu M4U_PORT_VENC_RCPU_SET2>, 14068eb80252STiffany Lin <&iommu M4U_PORT_VENC_REC_FRM_SET2>, 14078eb80252STiffany Lin <&iommu M4U_PORT_VENC_BSDMA_SET2>, 14088eb80252STiffany Lin <&iommu M4U_PORT_VENC_SV_COMA_SET2>, 14098eb80252STiffany Lin <&iommu M4U_PORT_VENC_RD_COMA_SET2>, 14108eb80252STiffany Lin <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, 14118eb80252STiffany Lin <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, 14128eb80252STiffany Lin <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, 14138eb80252STiffany Lin <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; 14148eb80252STiffany Lin mediatek,vpu = <&vpu>; 14158eb80252STiffany Lin clocks = <&topckgen CLK_TOP_VENCPLL_D2>, 14168eb80252STiffany Lin <&topckgen CLK_TOP_VENC_SEL>, 14178eb80252STiffany Lin <&topckgen CLK_TOP_UNIVPLL1_D2>, 14188eb80252STiffany Lin <&topckgen CLK_TOP_VENC_LT_SEL>; 14198eb80252STiffany Lin clock-names = "venc_sel_src", 14208eb80252STiffany Lin "venc_sel", 14218eb80252STiffany Lin "venc_lt_sel_src", 14228eb80252STiffany Lin "venc_lt_sel"; 1423fbbad028SYunfei Dong assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>, 1424fbbad028SYunfei Dong <&topckgen CLK_TOP_VENC_LT_SEL>; 1425fbbad028SYunfei Dong assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>, 1426fbbad028SYunfei Dong <&topckgen CLK_TOP_UNIVPLL1_D2>; 14278eb80252STiffany Lin }; 14288eb80252STiffany Lin 14291180beb0SHsin-Yi Wang jpegdec: jpegdec@18004000 { 14301180beb0SHsin-Yi Wang compatible = "mediatek,mt8173-jpgdec"; 14311180beb0SHsin-Yi Wang reg = <0 0x18004000 0 0x1000>; 14321180beb0SHsin-Yi Wang interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW>; 14331180beb0SHsin-Yi Wang clocks = <&vencsys CLK_VENC_CKE0>, 14341180beb0SHsin-Yi Wang <&vencsys CLK_VENC_CKE3>; 14351180beb0SHsin-Yi Wang clock-names = "jpgdec-smi", 14361180beb0SHsin-Yi Wang "jpgdec"; 14371180beb0SHsin-Yi Wang power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 14381180beb0SHsin-Yi Wang mediatek,larb = <&larb3>; 14391180beb0SHsin-Yi Wang iommus = <&iommu M4U_PORT_JPGDEC_WDMA>, 14401180beb0SHsin-Yi Wang <&iommu M4U_PORT_JPGDEC_BSDMA>; 14411180beb0SHsin-Yi Wang }; 14421180beb0SHsin-Yi Wang 144367e56c56SJames Liao vencltsys: clock-controller@19000000 { 144467e56c56SJames Liao compatible = "mediatek,mt8173-vencltsys", "syscon"; 144567e56c56SJames Liao reg = <0 0x19000000 0 0x1000>; 144667e56c56SJames Liao #clock-cells = <1>; 144767e56c56SJames Liao }; 14485ff6b3a6SYong Wu 14495ff6b3a6SYong Wu larb5: larb@19001000 { 14505ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 14515ff6b3a6SYong Wu reg = <0 0x19001000 0 0x1000>; 14525ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 14535ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; 14545ff6b3a6SYong Wu clocks = <&vencltsys CLK_VENCLT_CKE1>, 14555ff6b3a6SYong Wu <&vencltsys CLK_VENCLT_CKE0>; 14565ff6b3a6SYong Wu clock-names = "apb", "smi"; 14575ff6b3a6SYong Wu }; 1458b3a37248SEddie Huang }; 1459b3a37248SEddie Huang}; 1460b3a37248SEddie Huang 1461