1b3a37248SEddie Huang/* 2b3a37248SEddie Huang * Copyright (c) 2014 MediaTek Inc. 3b3a37248SEddie Huang * Author: Eddie Huang <eddie.huang@mediatek.com> 4b3a37248SEddie Huang * 5b3a37248SEddie Huang * This program is free software; you can redistribute it and/or modify 6b3a37248SEddie Huang * it under the terms of the GNU General Public License version 2 as 7b3a37248SEddie Huang * published by the Free Software Foundation. 8b3a37248SEddie Huang * 9b3a37248SEddie Huang * This program is distributed in the hope that it will be useful, 10b3a37248SEddie Huang * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11b3a37248SEddie Huang * GNU General Public License for more details. 12b3a37248SEddie Huang */ 13b3a37248SEddie Huang 14f2ce7014SSascha Hauer#include <dt-bindings/clock/mt8173-clk.h> 15b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/irq.h> 16b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/arm-gic.h> 17c02e0e86SKoro Chen#include <dt-bindings/power/mt8173-power.h> 186cf15fc2SSascha Hauer#include <dt-bindings/reset-controller/mt8173-resets.h> 19359f9365SHongzhou Yang#include "mt8173-pinfunc.h" 20b3a37248SEddie Huang 21b3a37248SEddie Huang/ { 22b3a37248SEddie Huang compatible = "mediatek,mt8173"; 23b3a37248SEddie Huang interrupt-parent = <&sysirq>; 24b3a37248SEddie Huang #address-cells = <2>; 25b3a37248SEddie Huang #size-cells = <2>; 26b3a37248SEddie Huang 27b3a37248SEddie Huang cpus { 28b3a37248SEddie Huang #address-cells = <1>; 29b3a37248SEddie Huang #size-cells = <0>; 30b3a37248SEddie Huang 31b3a37248SEddie Huang cpu-map { 32b3a37248SEddie Huang cluster0 { 33b3a37248SEddie Huang core0 { 34b3a37248SEddie Huang cpu = <&cpu0>; 35b3a37248SEddie Huang }; 36b3a37248SEddie Huang core1 { 37b3a37248SEddie Huang cpu = <&cpu1>; 38b3a37248SEddie Huang }; 39b3a37248SEddie Huang }; 40b3a37248SEddie Huang 41b3a37248SEddie Huang cluster1 { 42b3a37248SEddie Huang core0 { 43b3a37248SEddie Huang cpu = <&cpu2>; 44b3a37248SEddie Huang }; 45b3a37248SEddie Huang core1 { 46b3a37248SEddie Huang cpu = <&cpu3>; 47b3a37248SEddie Huang }; 48b3a37248SEddie Huang }; 49b3a37248SEddie Huang }; 50b3a37248SEddie Huang 51b3a37248SEddie Huang cpu0: cpu@0 { 52b3a37248SEddie Huang device_type = "cpu"; 53b3a37248SEddie Huang compatible = "arm,cortex-a53"; 54b3a37248SEddie Huang reg = <0x000>; 55ad4df7a5SHoward Chen enable-method = "psci"; 56ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 57b3a37248SEddie Huang }; 58b3a37248SEddie Huang 59b3a37248SEddie Huang cpu1: cpu@1 { 60b3a37248SEddie Huang device_type = "cpu"; 61b3a37248SEddie Huang compatible = "arm,cortex-a53"; 62b3a37248SEddie Huang reg = <0x001>; 63b3a37248SEddie Huang enable-method = "psci"; 64ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 65b3a37248SEddie Huang }; 66b3a37248SEddie Huang 67b3a37248SEddie Huang cpu2: cpu@100 { 68b3a37248SEddie Huang device_type = "cpu"; 69b3a37248SEddie Huang compatible = "arm,cortex-a57"; 70b3a37248SEddie Huang reg = <0x100>; 71b3a37248SEddie Huang enable-method = "psci"; 72ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 73b3a37248SEddie Huang }; 74b3a37248SEddie Huang 75b3a37248SEddie Huang cpu3: cpu@101 { 76b3a37248SEddie Huang device_type = "cpu"; 77b3a37248SEddie Huang compatible = "arm,cortex-a57"; 78b3a37248SEddie Huang reg = <0x101>; 79b3a37248SEddie Huang enable-method = "psci"; 80ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 81ad4df7a5SHoward Chen }; 82ad4df7a5SHoward Chen 83ad4df7a5SHoward Chen idle-states { 84ad4df7a5SHoward Chen entry-method = "arm,psci"; 85ad4df7a5SHoward Chen 86ad4df7a5SHoward Chen CPU_SLEEP_0: cpu-sleep-0 { 87ad4df7a5SHoward Chen compatible = "arm,idle-state"; 88ad4df7a5SHoward Chen local-timer-stop; 89ad4df7a5SHoward Chen entry-latency-us = <639>; 90ad4df7a5SHoward Chen exit-latency-us = <680>; 91ad4df7a5SHoward Chen min-residency-us = <1088>; 92ad4df7a5SHoward Chen arm,psci-suspend-param = <0x0010000>; 93ad4df7a5SHoward Chen }; 94b3a37248SEddie Huang }; 95b3a37248SEddie Huang }; 96b3a37248SEddie Huang 97b3a37248SEddie Huang psci { 98b3a37248SEddie Huang compatible = "arm,psci"; 99b3a37248SEddie Huang method = "smc"; 100b3a37248SEddie Huang cpu_suspend = <0x84000001>; 101b3a37248SEddie Huang cpu_off = <0x84000002>; 102b3a37248SEddie Huang cpu_on = <0x84000003>; 103b3a37248SEddie Huang }; 104b3a37248SEddie Huang 105f2ce7014SSascha Hauer clk26m: oscillator@0 { 106f2ce7014SSascha Hauer compatible = "fixed-clock"; 107f2ce7014SSascha Hauer #clock-cells = <0>; 108f2ce7014SSascha Hauer clock-frequency = <26000000>; 109f2ce7014SSascha Hauer clock-output-names = "clk26m"; 110f2ce7014SSascha Hauer }; 111f2ce7014SSascha Hauer 112f2ce7014SSascha Hauer clk32k: oscillator@1 { 113f2ce7014SSascha Hauer compatible = "fixed-clock"; 114f2ce7014SSascha Hauer #clock-cells = <0>; 115f2ce7014SSascha Hauer clock-frequency = <32000>; 116f2ce7014SSascha Hauer clock-output-names = "clk32k"; 117f2ce7014SSascha Hauer }; 118f2ce7014SSascha Hauer 11967e56c56SJames Liao cpum_ck: oscillator@2 { 12067e56c56SJames Liao compatible = "fixed-clock"; 12167e56c56SJames Liao #clock-cells = <0>; 12267e56c56SJames Liao clock-frequency = <0>; 12367e56c56SJames Liao clock-output-names = "cpum_ck"; 12467e56c56SJames Liao }; 12567e56c56SJames Liao 126b3a37248SEddie Huang timer { 127b3a37248SEddie Huang compatible = "arm,armv8-timer"; 128b3a37248SEddie Huang interrupt-parent = <&gic>; 129b3a37248SEddie Huang interrupts = <GIC_PPI 13 130b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 131b3a37248SEddie Huang <GIC_PPI 14 132b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 133b3a37248SEddie Huang <GIC_PPI 11 134b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 135b3a37248SEddie Huang <GIC_PPI 10 136b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 137b3a37248SEddie Huang }; 138b3a37248SEddie Huang 139b3a37248SEddie Huang soc { 140b3a37248SEddie Huang #address-cells = <2>; 141b3a37248SEddie Huang #size-cells = <2>; 142b3a37248SEddie Huang compatible = "simple-bus"; 143b3a37248SEddie Huang ranges; 144b3a37248SEddie Huang 145f2ce7014SSascha Hauer topckgen: clock-controller@10000000 { 146f2ce7014SSascha Hauer compatible = "mediatek,mt8173-topckgen"; 147f2ce7014SSascha Hauer reg = <0 0x10000000 0 0x1000>; 148f2ce7014SSascha Hauer #clock-cells = <1>; 149f2ce7014SSascha Hauer }; 150f2ce7014SSascha Hauer 151f2ce7014SSascha Hauer infracfg: power-controller@10001000 { 152f2ce7014SSascha Hauer compatible = "mediatek,mt8173-infracfg", "syscon"; 153f2ce7014SSascha Hauer reg = <0 0x10001000 0 0x1000>; 154f2ce7014SSascha Hauer #clock-cells = <1>; 155f2ce7014SSascha Hauer #reset-cells = <1>; 156f2ce7014SSascha Hauer }; 157f2ce7014SSascha Hauer 158f2ce7014SSascha Hauer pericfg: power-controller@10003000 { 159f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pericfg", "syscon"; 160f2ce7014SSascha Hauer reg = <0 0x10003000 0 0x1000>; 161f2ce7014SSascha Hauer #clock-cells = <1>; 162f2ce7014SSascha Hauer #reset-cells = <1>; 163f2ce7014SSascha Hauer }; 164f2ce7014SSascha Hauer 165f2ce7014SSascha Hauer syscfg_pctl_a: syscfg_pctl_a@10005000 { 166f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 167f2ce7014SSascha Hauer reg = <0 0x10005000 0 0x1000>; 168f2ce7014SSascha Hauer }; 169f2ce7014SSascha Hauer 170f2ce7014SSascha Hauer pio: pinctrl@0x10005000 { 171359f9365SHongzhou Yang compatible = "mediatek,mt8173-pinctrl"; 1726769b93cSYingjoe Chen reg = <0 0x1000b000 0 0x1000>; 173359f9365SHongzhou Yang mediatek,pctl-regmap = <&syscfg_pctl_a>; 174359f9365SHongzhou Yang pins-are-numbered; 175359f9365SHongzhou Yang gpio-controller; 176359f9365SHongzhou Yang #gpio-cells = <2>; 177359f9365SHongzhou Yang interrupt-controller; 178359f9365SHongzhou Yang #interrupt-cells = <2>; 179359f9365SHongzhou Yang interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 180359f9365SHongzhou Yang <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 181359f9365SHongzhou Yang <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 182091cf598SEddie Huang 183091cf598SEddie Huang i2c0_pins_a: i2c0 { 184091cf598SEddie Huang pins1 { 185091cf598SEddie Huang pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 186091cf598SEddie Huang <MT8173_PIN_46_SCL0__FUNC_SCL0>; 187091cf598SEddie Huang bias-disable; 188091cf598SEddie Huang }; 189359f9365SHongzhou Yang }; 190359f9365SHongzhou Yang 191091cf598SEddie Huang i2c1_pins_a: i2c1 { 192091cf598SEddie Huang pins1 { 193091cf598SEddie Huang pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 194091cf598SEddie Huang <MT8173_PIN_126_SCL1__FUNC_SCL1>; 195091cf598SEddie Huang bias-disable; 196091cf598SEddie Huang }; 197091cf598SEddie Huang }; 198091cf598SEddie Huang 199091cf598SEddie Huang i2c2_pins_a: i2c2 { 200091cf598SEddie Huang pins1 { 201091cf598SEddie Huang pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 202091cf598SEddie Huang <MT8173_PIN_44_SCL2__FUNC_SCL2>; 203091cf598SEddie Huang bias-disable; 204091cf598SEddie Huang }; 205091cf598SEddie Huang }; 206091cf598SEddie Huang 207091cf598SEddie Huang i2c3_pins_a: i2c3 { 208091cf598SEddie Huang pins1 { 209091cf598SEddie Huang pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 210091cf598SEddie Huang <MT8173_PIN_107_SCL3__FUNC_SCL3>; 211091cf598SEddie Huang bias-disable; 212091cf598SEddie Huang }; 213091cf598SEddie Huang }; 214091cf598SEddie Huang 215091cf598SEddie Huang i2c4_pins_a: i2c4 { 216091cf598SEddie Huang pins1 { 217091cf598SEddie Huang pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 218091cf598SEddie Huang <MT8173_PIN_134_SCL4__FUNC_SCL4>; 219091cf598SEddie Huang bias-disable; 220091cf598SEddie Huang }; 221091cf598SEddie Huang }; 222091cf598SEddie Huang 223091cf598SEddie Huang i2c6_pins_a: i2c6 { 224091cf598SEddie Huang pins1 { 225091cf598SEddie Huang pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 226091cf598SEddie Huang <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 227091cf598SEddie Huang bias-disable; 228091cf598SEddie Huang }; 229091cf598SEddie Huang }; 2306769b93cSYingjoe Chen }; 2316769b93cSYingjoe Chen 232c010ff53SSascha Hauer scpsys: scpsys@10006000 { 233c010ff53SSascha Hauer compatible = "mediatek,mt8173-scpsys"; 234c010ff53SSascha Hauer #power-domain-cells = <1>; 235c010ff53SSascha Hauer reg = <0 0x10006000 0 0x1000>; 236c010ff53SSascha Hauer clocks = <&clk26m>, 237c010ff53SSascha Hauer <&topckgen CLK_TOP_MM_SEL>; 238c010ff53SSascha Hauer clock-names = "mfg", "mm"; 239c010ff53SSascha Hauer infracfg = <&infracfg>; 240c010ff53SSascha Hauer }; 241c010ff53SSascha Hauer 24213421b3eSEddie Huang watchdog: watchdog@10007000 { 24313421b3eSEddie Huang compatible = "mediatek,mt8173-wdt", 24413421b3eSEddie Huang "mediatek,mt6589-wdt"; 24513421b3eSEddie Huang reg = <0 0x10007000 0 0x100>; 24613421b3eSEddie Huang }; 24713421b3eSEddie Huang 2486cf15fc2SSascha Hauer pwrap: pwrap@1000d000 { 2496cf15fc2SSascha Hauer compatible = "mediatek,mt8173-pwrap"; 2506cf15fc2SSascha Hauer reg = <0 0x1000d000 0 0x1000>; 2516cf15fc2SSascha Hauer reg-names = "pwrap"; 2526cf15fc2SSascha Hauer interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 2536cf15fc2SSascha Hauer resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 2546cf15fc2SSascha Hauer reset-names = "pwrap"; 2556cf15fc2SSascha Hauer clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 2566cf15fc2SSascha Hauer clock-names = "spi", "wrap"; 2576cf15fc2SSascha Hauer }; 2586cf15fc2SSascha Hauer 259b3a37248SEddie Huang sysirq: intpol-controller@10200620 { 260b3a37248SEddie Huang compatible = "mediatek,mt8173-sysirq", 261b3a37248SEddie Huang "mediatek,mt6577-sysirq"; 262b3a37248SEddie Huang interrupt-controller; 263b3a37248SEddie Huang #interrupt-cells = <3>; 264b3a37248SEddie Huang interrupt-parent = <&gic>; 265b3a37248SEddie Huang reg = <0 0x10200620 0 0x20>; 266b3a37248SEddie Huang }; 267b3a37248SEddie Huang 268f2ce7014SSascha Hauer apmixedsys: clock-controller@10209000 { 269f2ce7014SSascha Hauer compatible = "mediatek,mt8173-apmixedsys"; 270f2ce7014SSascha Hauer reg = <0 0x10209000 0 0x1000>; 271f2ce7014SSascha Hauer #clock-cells = <1>; 272f2ce7014SSascha Hauer }; 273f2ce7014SSascha Hauer 274b3a37248SEddie Huang gic: interrupt-controller@10220000 { 275b3a37248SEddie Huang compatible = "arm,gic-400"; 276b3a37248SEddie Huang #interrupt-cells = <3>; 277b3a37248SEddie Huang interrupt-parent = <&gic>; 278b3a37248SEddie Huang interrupt-controller; 279b3a37248SEddie Huang reg = <0 0x10221000 0 0x1000>, 280b3a37248SEddie Huang <0 0x10222000 0 0x2000>, 281b3a37248SEddie Huang <0 0x10224000 0 0x2000>, 282b3a37248SEddie Huang <0 0x10226000 0 0x2000>; 283b3a37248SEddie Huang interrupts = <GIC_PPI 9 284b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 285b3a37248SEddie Huang }; 286b3a37248SEddie Huang 287b3a37248SEddie Huang uart0: serial@11002000 { 288b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 289b3a37248SEddie Huang "mediatek,mt6577-uart"; 290b3a37248SEddie Huang reg = <0 0x11002000 0 0x400>; 291b3a37248SEddie Huang interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 2920e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 2930e84faa1SSascha Hauer clock-names = "baud", "bus"; 294b3a37248SEddie Huang status = "disabled"; 295b3a37248SEddie Huang }; 296b3a37248SEddie Huang 297b3a37248SEddie Huang uart1: serial@11003000 { 298b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 299b3a37248SEddie Huang "mediatek,mt6577-uart"; 300b3a37248SEddie Huang reg = <0 0x11003000 0 0x400>; 301b3a37248SEddie Huang interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 3020e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 3030e84faa1SSascha Hauer clock-names = "baud", "bus"; 304b3a37248SEddie Huang status = "disabled"; 305b3a37248SEddie Huang }; 306b3a37248SEddie Huang 307b3a37248SEddie Huang uart2: serial@11004000 { 308b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 309b3a37248SEddie Huang "mediatek,mt6577-uart"; 310b3a37248SEddie Huang reg = <0 0x11004000 0 0x400>; 311b3a37248SEddie Huang interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 3120e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 3130e84faa1SSascha Hauer clock-names = "baud", "bus"; 314b3a37248SEddie Huang status = "disabled"; 315b3a37248SEddie Huang }; 316b3a37248SEddie Huang 317b3a37248SEddie Huang uart3: serial@11005000 { 318b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 319b3a37248SEddie Huang "mediatek,mt6577-uart"; 320b3a37248SEddie Huang reg = <0 0x11005000 0 0x400>; 321b3a37248SEddie Huang interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 3220e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 3230e84faa1SSascha Hauer clock-names = "baud", "bus"; 324b3a37248SEddie Huang status = "disabled"; 325b3a37248SEddie Huang }; 326091cf598SEddie Huang 327091cf598SEddie Huang i2c0: i2c@11007000 { 328091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 329091cf598SEddie Huang reg = <0 0x11007000 0 0x70>, 330091cf598SEddie Huang <0 0x11000100 0 0x80>; 331091cf598SEddie Huang interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 332091cf598SEddie Huang clock-div = <16>; 333091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C0>, 334091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 335091cf598SEddie Huang clock-names = "main", "dma"; 336091cf598SEddie Huang pinctrl-names = "default"; 337091cf598SEddie Huang pinctrl-0 = <&i2c0_pins_a>; 338091cf598SEddie Huang #address-cells = <1>; 339091cf598SEddie Huang #size-cells = <0>; 340091cf598SEddie Huang status = "disabled"; 341091cf598SEddie Huang }; 342091cf598SEddie Huang 343091cf598SEddie Huang i2c1: i2c@11008000 { 344091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 345091cf598SEddie Huang reg = <0 0x11008000 0 0x70>, 346091cf598SEddie Huang <0 0x11000180 0 0x80>; 347091cf598SEddie Huang interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 348091cf598SEddie Huang clock-div = <16>; 349091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C1>, 350091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 351091cf598SEddie Huang clock-names = "main", "dma"; 352091cf598SEddie Huang pinctrl-names = "default"; 353091cf598SEddie Huang pinctrl-0 = <&i2c1_pins_a>; 354091cf598SEddie Huang #address-cells = <1>; 355091cf598SEddie Huang #size-cells = <0>; 356091cf598SEddie Huang status = "disabled"; 357091cf598SEddie Huang }; 358091cf598SEddie Huang 359091cf598SEddie Huang i2c2: i2c@11009000 { 360091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 361091cf598SEddie Huang reg = <0 0x11009000 0 0x70>, 362091cf598SEddie Huang <0 0x11000200 0 0x80>; 363091cf598SEddie Huang interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 364091cf598SEddie Huang clock-div = <16>; 365091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C2>, 366091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 367091cf598SEddie Huang clock-names = "main", "dma"; 368091cf598SEddie Huang pinctrl-names = "default"; 369091cf598SEddie Huang pinctrl-0 = <&i2c2_pins_a>; 370091cf598SEddie Huang #address-cells = <1>; 371091cf598SEddie Huang #size-cells = <0>; 372091cf598SEddie Huang status = "disabled"; 373091cf598SEddie Huang }; 374091cf598SEddie Huang 375b0c936f5SLeilk Liu spi: spi@1100a000 { 376b0c936f5SLeilk Liu compatible = "mediatek,mt8173-spi"; 377b0c936f5SLeilk Liu #address-cells = <1>; 378b0c936f5SLeilk Liu #size-cells = <0>; 379b0c936f5SLeilk Liu reg = <0 0x1100a000 0 0x1000>; 380b0c936f5SLeilk Liu interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 381b0c936f5SLeilk Liu clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 382b0c936f5SLeilk Liu <&topckgen CLK_TOP_SPI_SEL>, 383b0c936f5SLeilk Liu <&pericfg CLK_PERI_SPI0>; 384b0c936f5SLeilk Liu clock-names = "parent-clk", "sel-clk", "spi-clk"; 385b0c936f5SLeilk Liu status = "disabled"; 386b0c936f5SLeilk Liu }; 387b0c936f5SLeilk Liu 3881ee35c05SYingjoe Chen i2c3: i2c@11010000 { 389091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 390091cf598SEddie Huang reg = <0 0x11010000 0 0x70>, 391091cf598SEddie Huang <0 0x11000280 0 0x80>; 392091cf598SEddie Huang interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 393091cf598SEddie Huang clock-div = <16>; 394091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C3>, 395091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 396091cf598SEddie Huang clock-names = "main", "dma"; 397091cf598SEddie Huang pinctrl-names = "default"; 398091cf598SEddie Huang pinctrl-0 = <&i2c3_pins_a>; 399091cf598SEddie Huang #address-cells = <1>; 400091cf598SEddie Huang #size-cells = <0>; 401091cf598SEddie Huang status = "disabled"; 402091cf598SEddie Huang }; 403091cf598SEddie Huang 4041ee35c05SYingjoe Chen i2c4: i2c@11011000 { 405091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 406091cf598SEddie Huang reg = <0 0x11011000 0 0x70>, 407091cf598SEddie Huang <0 0x11000300 0 0x80>; 408091cf598SEddie Huang interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 409091cf598SEddie Huang clock-div = <16>; 410091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C4>, 411091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 412091cf598SEddie Huang clock-names = "main", "dma"; 413091cf598SEddie Huang pinctrl-names = "default"; 414091cf598SEddie Huang pinctrl-0 = <&i2c4_pins_a>; 415091cf598SEddie Huang #address-cells = <1>; 416091cf598SEddie Huang #size-cells = <0>; 417091cf598SEddie Huang status = "disabled"; 418091cf598SEddie Huang }; 419091cf598SEddie Huang 4201ee35c05SYingjoe Chen i2c6: i2c@11013000 { 421091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 422091cf598SEddie Huang reg = <0 0x11013000 0 0x70>, 423091cf598SEddie Huang <0 0x11000080 0 0x80>; 424091cf598SEddie Huang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 425091cf598SEddie Huang clock-div = <16>; 426091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C6>, 427091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 428091cf598SEddie Huang clock-names = "main", "dma"; 429091cf598SEddie Huang pinctrl-names = "default"; 430091cf598SEddie Huang pinctrl-0 = <&i2c6_pins_a>; 431091cf598SEddie Huang #address-cells = <1>; 432091cf598SEddie Huang #size-cells = <0>; 433091cf598SEddie Huang status = "disabled"; 434091cf598SEddie Huang }; 435c02e0e86SKoro Chen 436c02e0e86SKoro Chen afe: audio-controller@11220000 { 437c02e0e86SKoro Chen compatible = "mediatek,mt8173-afe-pcm"; 438c02e0e86SKoro Chen reg = <0 0x11220000 0 0x1000>; 439c02e0e86SKoro Chen interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 440c02e0e86SKoro Chen power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; 441c02e0e86SKoro Chen clocks = <&infracfg CLK_INFRA_AUDIO>, 442c02e0e86SKoro Chen <&topckgen CLK_TOP_AUDIO_SEL>, 443c02e0e86SKoro Chen <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 444c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL1_DIV0>, 445c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL2_DIV0>, 446c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S0_M_SEL>, 447c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S1_M_SEL>, 448c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S2_M_SEL>, 449c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S3_M_SEL>, 450c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S3_B_SEL>; 451c02e0e86SKoro Chen clock-names = "infra_sys_audio_clk", 452c02e0e86SKoro Chen "top_pdn_audio", 453c02e0e86SKoro Chen "top_pdn_aud_intbus", 454c02e0e86SKoro Chen "bck0", 455c02e0e86SKoro Chen "bck1", 456c02e0e86SKoro Chen "i2s0_m", 457c02e0e86SKoro Chen "i2s1_m", 458c02e0e86SKoro Chen "i2s2_m", 459c02e0e86SKoro Chen "i2s3_m", 460c02e0e86SKoro Chen "i2s3_b"; 461c02e0e86SKoro Chen assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 462c02e0e86SKoro Chen <&topckgen CLK_TOP_AUD_2_SEL>; 463c02e0e86SKoro Chen assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 464c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL2>; 465c02e0e86SKoro Chen }; 4669719fa5aSEddie Huang 4679719fa5aSEddie Huang mmc0: mmc@11230000 { 4689719fa5aSEddie Huang compatible = "mediatek,mt8173-mmc", 4699719fa5aSEddie Huang "mediatek,mt8135-mmc"; 4709719fa5aSEddie Huang reg = <0 0x11230000 0 0x1000>; 4719719fa5aSEddie Huang interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 4729719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_0>, 4739719fa5aSEddie Huang <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 4749719fa5aSEddie Huang clock-names = "source", "hclk"; 4759719fa5aSEddie Huang status = "disabled"; 4769719fa5aSEddie Huang }; 4779719fa5aSEddie Huang 4789719fa5aSEddie Huang mmc1: mmc@11240000 { 4799719fa5aSEddie Huang compatible = "mediatek,mt8173-mmc", 4809719fa5aSEddie Huang "mediatek,mt8135-mmc"; 4819719fa5aSEddie Huang reg = <0 0x11240000 0 0x1000>; 4829719fa5aSEddie Huang interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 4839719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_1>, 4849719fa5aSEddie Huang <&topckgen CLK_TOP_AXI_SEL>; 4859719fa5aSEddie Huang clock-names = "source", "hclk"; 4869719fa5aSEddie Huang status = "disabled"; 4879719fa5aSEddie Huang }; 4889719fa5aSEddie Huang 4899719fa5aSEddie Huang mmc2: mmc@11250000 { 4909719fa5aSEddie Huang compatible = "mediatek,mt8173-mmc", 4919719fa5aSEddie Huang "mediatek,mt8135-mmc"; 4929719fa5aSEddie Huang reg = <0 0x11250000 0 0x1000>; 4939719fa5aSEddie Huang interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 4949719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_2>, 4959719fa5aSEddie Huang <&topckgen CLK_TOP_AXI_SEL>; 4969719fa5aSEddie Huang clock-names = "source", "hclk"; 4979719fa5aSEddie Huang status = "disabled"; 4989719fa5aSEddie Huang }; 4999719fa5aSEddie Huang 5009719fa5aSEddie Huang mmc3: mmc@11260000 { 5019719fa5aSEddie Huang compatible = "mediatek,mt8173-mmc", 5029719fa5aSEddie Huang "mediatek,mt8135-mmc"; 5039719fa5aSEddie Huang reg = <0 0x11260000 0 0x1000>; 5049719fa5aSEddie Huang interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 5059719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_3>, 5069719fa5aSEddie Huang <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 5079719fa5aSEddie Huang clock-names = "source", "hclk"; 5089719fa5aSEddie Huang status = "disabled"; 5099719fa5aSEddie Huang }; 51067e56c56SJames Liao 51167e56c56SJames Liao mmsys: clock-controller@14000000 { 51267e56c56SJames Liao compatible = "mediatek,mt8173-mmsys", "syscon"; 51367e56c56SJames Liao reg = <0 0x14000000 0 0x1000>; 51467e56c56SJames Liao #clock-cells = <1>; 51567e56c56SJames Liao }; 51667e56c56SJames Liao 51767e56c56SJames Liao imgsys: clock-controller@15000000 { 51867e56c56SJames Liao compatible = "mediatek,mt8173-imgsys", "syscon"; 51967e56c56SJames Liao reg = <0 0x15000000 0 0x1000>; 52067e56c56SJames Liao #clock-cells = <1>; 52167e56c56SJames Liao }; 52267e56c56SJames Liao 52367e56c56SJames Liao vdecsys: clock-controller@16000000 { 52467e56c56SJames Liao compatible = "mediatek,mt8173-vdecsys", "syscon"; 52567e56c56SJames Liao reg = <0 0x16000000 0 0x1000>; 52667e56c56SJames Liao #clock-cells = <1>; 52767e56c56SJames Liao }; 52867e56c56SJames Liao 52967e56c56SJames Liao vencsys: clock-controller@18000000 { 53067e56c56SJames Liao compatible = "mediatek,mt8173-vencsys", "syscon"; 53167e56c56SJames Liao reg = <0 0x18000000 0 0x1000>; 53267e56c56SJames Liao #clock-cells = <1>; 53367e56c56SJames Liao }; 53467e56c56SJames Liao 53567e56c56SJames Liao vencltsys: clock-controller@19000000 { 53667e56c56SJames Liao compatible = "mediatek,mt8173-vencltsys", "syscon"; 53767e56c56SJames Liao reg = <0 0x19000000 0 0x1000>; 53867e56c56SJames Liao #clock-cells = <1>; 53967e56c56SJames Liao }; 540b3a37248SEddie Huang }; 541b3a37248SEddie Huang}; 542b3a37248SEddie Huang 543