1b3a37248SEddie Huang/* 2b3a37248SEddie Huang * Copyright (c) 2014 MediaTek Inc. 3b3a37248SEddie Huang * Author: Eddie Huang <eddie.huang@mediatek.com> 4b3a37248SEddie Huang * 5b3a37248SEddie Huang * This program is free software; you can redistribute it and/or modify 6b3a37248SEddie Huang * it under the terms of the GNU General Public License version 2 as 7b3a37248SEddie Huang * published by the Free Software Foundation. 8b3a37248SEddie Huang * 9b3a37248SEddie Huang * This program is distributed in the hope that it will be useful, 10b3a37248SEddie Huang * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11b3a37248SEddie Huang * GNU General Public License for more details. 12b3a37248SEddie Huang */ 13b3a37248SEddie Huang 14f2ce7014SSascha Hauer#include <dt-bindings/clock/mt8173-clk.h> 15b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/irq.h> 16b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/arm-gic.h> 175ff6b3a6SYong Wu#include <dt-bindings/memory/mt8173-larb-port.h> 18bfcce47aSChunfeng Yun#include <dt-bindings/phy/phy.h> 19c02e0e86SKoro Chen#include <dt-bindings/power/mt8173-power.h> 20967313e2SPhilipp Zabel#include <dt-bindings/reset/mt8173-resets.h> 21359f9365SHongzhou Yang#include "mt8173-pinfunc.h" 22b3a37248SEddie Huang 23b3a37248SEddie Huang/ { 24b3a37248SEddie Huang compatible = "mediatek,mt8173"; 25b3a37248SEddie Huang interrupt-parent = <&sysirq>; 26b3a37248SEddie Huang #address-cells = <2>; 27b3a37248SEddie Huang #size-cells = <2>; 28b3a37248SEddie Huang 29b3a37248SEddie Huang cpus { 30b3a37248SEddie Huang #address-cells = <1>; 31b3a37248SEddie Huang #size-cells = <0>; 32b3a37248SEddie Huang 33b3a37248SEddie Huang cpu-map { 34b3a37248SEddie Huang cluster0 { 35b3a37248SEddie Huang core0 { 36b3a37248SEddie Huang cpu = <&cpu0>; 37b3a37248SEddie Huang }; 38b3a37248SEddie Huang core1 { 39b3a37248SEddie Huang cpu = <&cpu1>; 40b3a37248SEddie Huang }; 41b3a37248SEddie Huang }; 42b3a37248SEddie Huang 43b3a37248SEddie Huang cluster1 { 44b3a37248SEddie Huang core0 { 45b3a37248SEddie Huang cpu = <&cpu2>; 46b3a37248SEddie Huang }; 47b3a37248SEddie Huang core1 { 48b3a37248SEddie Huang cpu = <&cpu3>; 49b3a37248SEddie Huang }; 50b3a37248SEddie Huang }; 51b3a37248SEddie Huang }; 52b3a37248SEddie Huang 53b3a37248SEddie Huang cpu0: cpu@0 { 54b3a37248SEddie Huang device_type = "cpu"; 55b3a37248SEddie Huang compatible = "arm,cortex-a53"; 56b3a37248SEddie Huang reg = <0x000>; 57ad4df7a5SHoward Chen enable-method = "psci"; 58ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 59b3a37248SEddie Huang }; 60b3a37248SEddie Huang 61b3a37248SEddie Huang cpu1: cpu@1 { 62b3a37248SEddie Huang device_type = "cpu"; 63b3a37248SEddie Huang compatible = "arm,cortex-a53"; 64b3a37248SEddie Huang reg = <0x001>; 65b3a37248SEddie Huang enable-method = "psci"; 66ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 67b3a37248SEddie Huang }; 68b3a37248SEddie Huang 69b3a37248SEddie Huang cpu2: cpu@100 { 70b3a37248SEddie Huang device_type = "cpu"; 71b3a37248SEddie Huang compatible = "arm,cortex-a57"; 72b3a37248SEddie Huang reg = <0x100>; 73b3a37248SEddie Huang enable-method = "psci"; 74ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 75b3a37248SEddie Huang }; 76b3a37248SEddie Huang 77b3a37248SEddie Huang cpu3: cpu@101 { 78b3a37248SEddie Huang device_type = "cpu"; 79b3a37248SEddie Huang compatible = "arm,cortex-a57"; 80b3a37248SEddie Huang reg = <0x101>; 81b3a37248SEddie Huang enable-method = "psci"; 82ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 83ad4df7a5SHoward Chen }; 84ad4df7a5SHoward Chen 85ad4df7a5SHoward Chen idle-states { 86a13f18f5SLorenzo Pieralisi entry-method = "psci"; 87ad4df7a5SHoward Chen 88ad4df7a5SHoward Chen CPU_SLEEP_0: cpu-sleep-0 { 89ad4df7a5SHoward Chen compatible = "arm,idle-state"; 90ad4df7a5SHoward Chen local-timer-stop; 91ad4df7a5SHoward Chen entry-latency-us = <639>; 92ad4df7a5SHoward Chen exit-latency-us = <680>; 93ad4df7a5SHoward Chen min-residency-us = <1088>; 94ad4df7a5SHoward Chen arm,psci-suspend-param = <0x0010000>; 95ad4df7a5SHoward Chen }; 96b3a37248SEddie Huang }; 97b3a37248SEddie Huang }; 98b3a37248SEddie Huang 99b3a37248SEddie Huang psci { 10005bdabe7SFan Chen compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 101b3a37248SEddie Huang method = "smc"; 102b3a37248SEddie Huang cpu_suspend = <0x84000001>; 103b3a37248SEddie Huang cpu_off = <0x84000002>; 104b3a37248SEddie Huang cpu_on = <0x84000003>; 105b3a37248SEddie Huang }; 106b3a37248SEddie Huang 107f2ce7014SSascha Hauer clk26m: oscillator@0 { 108f2ce7014SSascha Hauer compatible = "fixed-clock"; 109f2ce7014SSascha Hauer #clock-cells = <0>; 110f2ce7014SSascha Hauer clock-frequency = <26000000>; 111f2ce7014SSascha Hauer clock-output-names = "clk26m"; 112f2ce7014SSascha Hauer }; 113f2ce7014SSascha Hauer 114f2ce7014SSascha Hauer clk32k: oscillator@1 { 115f2ce7014SSascha Hauer compatible = "fixed-clock"; 116f2ce7014SSascha Hauer #clock-cells = <0>; 117f2ce7014SSascha Hauer clock-frequency = <32000>; 118f2ce7014SSascha Hauer clock-output-names = "clk32k"; 119f2ce7014SSascha Hauer }; 120f2ce7014SSascha Hauer 12167e56c56SJames Liao cpum_ck: oscillator@2 { 12267e56c56SJames Liao compatible = "fixed-clock"; 12367e56c56SJames Liao #clock-cells = <0>; 12467e56c56SJames Liao clock-frequency = <0>; 12567e56c56SJames Liao clock-output-names = "cpum_ck"; 12667e56c56SJames Liao }; 12767e56c56SJames Liao 128962f5143Sdawei.chien@mediatek.com thermal-zones { 129962f5143Sdawei.chien@mediatek.com cpu_thermal: cpu_thermal { 130962f5143Sdawei.chien@mediatek.com polling-delay-passive = <1000>; /* milliseconds */ 131962f5143Sdawei.chien@mediatek.com polling-delay = <1000>; /* milliseconds */ 132962f5143Sdawei.chien@mediatek.com 133962f5143Sdawei.chien@mediatek.com thermal-sensors = <&thermal>; 134962f5143Sdawei.chien@mediatek.com sustainable-power = <1500>; /* milliwatts */ 135962f5143Sdawei.chien@mediatek.com 136962f5143Sdawei.chien@mediatek.com trips { 137962f5143Sdawei.chien@mediatek.com threshold: trip-point@0 { 138962f5143Sdawei.chien@mediatek.com temperature = <68000>; 139962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 140962f5143Sdawei.chien@mediatek.com type = "passive"; 141962f5143Sdawei.chien@mediatek.com }; 142962f5143Sdawei.chien@mediatek.com 143962f5143Sdawei.chien@mediatek.com target: trip-point@1 { 144962f5143Sdawei.chien@mediatek.com temperature = <85000>; 145962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 146962f5143Sdawei.chien@mediatek.com type = "passive"; 147962f5143Sdawei.chien@mediatek.com }; 148962f5143Sdawei.chien@mediatek.com 149962f5143Sdawei.chien@mediatek.com cpu_crit: cpu_crit@0 { 150962f5143Sdawei.chien@mediatek.com temperature = <115000>; 151962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 152962f5143Sdawei.chien@mediatek.com type = "critical"; 153962f5143Sdawei.chien@mediatek.com }; 154962f5143Sdawei.chien@mediatek.com }; 155962f5143Sdawei.chien@mediatek.com 156962f5143Sdawei.chien@mediatek.com cooling-maps { 157962f5143Sdawei.chien@mediatek.com map@0 { 158962f5143Sdawei.chien@mediatek.com trip = <&target>; 159962f5143Sdawei.chien@mediatek.com cooling-device = <&cpu0 0 0>; 160962f5143Sdawei.chien@mediatek.com contribution = <1024>; 161962f5143Sdawei.chien@mediatek.com }; 162962f5143Sdawei.chien@mediatek.com map@1 { 163962f5143Sdawei.chien@mediatek.com trip = <&target>; 164962f5143Sdawei.chien@mediatek.com cooling-device = <&cpu2 0 0>; 165962f5143Sdawei.chien@mediatek.com contribution = <2048>; 166962f5143Sdawei.chien@mediatek.com }; 167962f5143Sdawei.chien@mediatek.com }; 168962f5143Sdawei.chien@mediatek.com }; 169962f5143Sdawei.chien@mediatek.com }; 170962f5143Sdawei.chien@mediatek.com 171404b2819SAndrew-CT Chen reserved-memory { 172404b2819SAndrew-CT Chen #address-cells = <2>; 173404b2819SAndrew-CT Chen #size-cells = <2>; 174404b2819SAndrew-CT Chen ranges; 175404b2819SAndrew-CT Chen vpu_dma_reserved: vpu_dma_mem_region { 176404b2819SAndrew-CT Chen compatible = "shared-dma-pool"; 177404b2819SAndrew-CT Chen reg = <0 0xb7000000 0 0x500000>; 178404b2819SAndrew-CT Chen alignment = <0x1000>; 179404b2819SAndrew-CT Chen no-map; 180404b2819SAndrew-CT Chen }; 181404b2819SAndrew-CT Chen }; 182404b2819SAndrew-CT Chen 183b3a37248SEddie Huang timer { 184b3a37248SEddie Huang compatible = "arm,armv8-timer"; 185b3a37248SEddie Huang interrupt-parent = <&gic>; 186b3a37248SEddie Huang interrupts = <GIC_PPI 13 187b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 188b3a37248SEddie Huang <GIC_PPI 14 189b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 190b3a37248SEddie Huang <GIC_PPI 11 191b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 192b3a37248SEddie Huang <GIC_PPI 10 193b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 194b3a37248SEddie Huang }; 195b3a37248SEddie Huang 196b3a37248SEddie Huang soc { 197b3a37248SEddie Huang #address-cells = <2>; 198b3a37248SEddie Huang #size-cells = <2>; 199b3a37248SEddie Huang compatible = "simple-bus"; 200b3a37248SEddie Huang ranges; 201b3a37248SEddie Huang 202f2ce7014SSascha Hauer topckgen: clock-controller@10000000 { 203f2ce7014SSascha Hauer compatible = "mediatek,mt8173-topckgen"; 204f2ce7014SSascha Hauer reg = <0 0x10000000 0 0x1000>; 205f2ce7014SSascha Hauer #clock-cells = <1>; 206f2ce7014SSascha Hauer }; 207f2ce7014SSascha Hauer 208f2ce7014SSascha Hauer infracfg: power-controller@10001000 { 209f2ce7014SSascha Hauer compatible = "mediatek,mt8173-infracfg", "syscon"; 210f2ce7014SSascha Hauer reg = <0 0x10001000 0 0x1000>; 211f2ce7014SSascha Hauer #clock-cells = <1>; 212f2ce7014SSascha Hauer #reset-cells = <1>; 213f2ce7014SSascha Hauer }; 214f2ce7014SSascha Hauer 215f2ce7014SSascha Hauer pericfg: power-controller@10003000 { 216f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pericfg", "syscon"; 217f2ce7014SSascha Hauer reg = <0 0x10003000 0 0x1000>; 218f2ce7014SSascha Hauer #clock-cells = <1>; 219f2ce7014SSascha Hauer #reset-cells = <1>; 220f2ce7014SSascha Hauer }; 221f2ce7014SSascha Hauer 222f2ce7014SSascha Hauer syscfg_pctl_a: syscfg_pctl_a@10005000 { 223f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 224f2ce7014SSascha Hauer reg = <0 0x10005000 0 0x1000>; 225f2ce7014SSascha Hauer }; 226f2ce7014SSascha Hauer 227f2ce7014SSascha Hauer pio: pinctrl@0x10005000 { 228359f9365SHongzhou Yang compatible = "mediatek,mt8173-pinctrl"; 2296769b93cSYingjoe Chen reg = <0 0x1000b000 0 0x1000>; 230359f9365SHongzhou Yang mediatek,pctl-regmap = <&syscfg_pctl_a>; 231359f9365SHongzhou Yang pins-are-numbered; 232359f9365SHongzhou Yang gpio-controller; 233359f9365SHongzhou Yang #gpio-cells = <2>; 234359f9365SHongzhou Yang interrupt-controller; 235359f9365SHongzhou Yang #interrupt-cells = <2>; 236359f9365SHongzhou Yang interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 237359f9365SHongzhou Yang <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 238359f9365SHongzhou Yang <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 239091cf598SEddie Huang 240091cf598SEddie Huang i2c0_pins_a: i2c0 { 241091cf598SEddie Huang pins1 { 242091cf598SEddie Huang pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 243091cf598SEddie Huang <MT8173_PIN_46_SCL0__FUNC_SCL0>; 244091cf598SEddie Huang bias-disable; 245091cf598SEddie Huang }; 246359f9365SHongzhou Yang }; 247359f9365SHongzhou Yang 248091cf598SEddie Huang i2c1_pins_a: i2c1 { 249091cf598SEddie Huang pins1 { 250091cf598SEddie Huang pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 251091cf598SEddie Huang <MT8173_PIN_126_SCL1__FUNC_SCL1>; 252091cf598SEddie Huang bias-disable; 253091cf598SEddie Huang }; 254091cf598SEddie Huang }; 255091cf598SEddie Huang 256091cf598SEddie Huang i2c2_pins_a: i2c2 { 257091cf598SEddie Huang pins1 { 258091cf598SEddie Huang pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 259091cf598SEddie Huang <MT8173_PIN_44_SCL2__FUNC_SCL2>; 260091cf598SEddie Huang bias-disable; 261091cf598SEddie Huang }; 262091cf598SEddie Huang }; 263091cf598SEddie Huang 264091cf598SEddie Huang i2c3_pins_a: i2c3 { 265091cf598SEddie Huang pins1 { 266091cf598SEddie Huang pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 267091cf598SEddie Huang <MT8173_PIN_107_SCL3__FUNC_SCL3>; 268091cf598SEddie Huang bias-disable; 269091cf598SEddie Huang }; 270091cf598SEddie Huang }; 271091cf598SEddie Huang 272091cf598SEddie Huang i2c4_pins_a: i2c4 { 273091cf598SEddie Huang pins1 { 274091cf598SEddie Huang pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 275091cf598SEddie Huang <MT8173_PIN_134_SCL4__FUNC_SCL4>; 276091cf598SEddie Huang bias-disable; 277091cf598SEddie Huang }; 278091cf598SEddie Huang }; 279091cf598SEddie Huang 280091cf598SEddie Huang i2c6_pins_a: i2c6 { 281091cf598SEddie Huang pins1 { 282091cf598SEddie Huang pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 283091cf598SEddie Huang <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 284091cf598SEddie Huang bias-disable; 285091cf598SEddie Huang }; 286091cf598SEddie Huang }; 2876769b93cSYingjoe Chen }; 2886769b93cSYingjoe Chen 289c010ff53SSascha Hauer scpsys: scpsys@10006000 { 290c010ff53SSascha Hauer compatible = "mediatek,mt8173-scpsys"; 291c010ff53SSascha Hauer #power-domain-cells = <1>; 292c010ff53SSascha Hauer reg = <0 0x10006000 0 0x1000>; 293c010ff53SSascha Hauer clocks = <&clk26m>, 294e34573c9SJames Liao <&topckgen CLK_TOP_MM_SEL>, 295e34573c9SJames Liao <&topckgen CLK_TOP_VENC_SEL>, 296e34573c9SJames Liao <&topckgen CLK_TOP_VENC_LT_SEL>; 297e34573c9SJames Liao clock-names = "mfg", "mm", "venc", "venc_lt"; 298c010ff53SSascha Hauer infracfg = <&infracfg>; 299c010ff53SSascha Hauer }; 300c010ff53SSascha Hauer 30113421b3eSEddie Huang watchdog: watchdog@10007000 { 30213421b3eSEddie Huang compatible = "mediatek,mt8173-wdt", 30313421b3eSEddie Huang "mediatek,mt6589-wdt"; 30413421b3eSEddie Huang reg = <0 0x10007000 0 0x100>; 30513421b3eSEddie Huang }; 30613421b3eSEddie Huang 307b2c76e27SDaniel Kurtz timer: timer@10008000 { 308b2c76e27SDaniel Kurtz compatible = "mediatek,mt8173-timer", 309b2c76e27SDaniel Kurtz "mediatek,mt6577-timer"; 310b2c76e27SDaniel Kurtz reg = <0 0x10008000 0 0x1000>; 311b2c76e27SDaniel Kurtz interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 312b2c76e27SDaniel Kurtz clocks = <&infracfg CLK_INFRA_CLK_13M>, 313b2c76e27SDaniel Kurtz <&topckgen CLK_TOP_RTC_SEL>; 314b2c76e27SDaniel Kurtz }; 315b2c76e27SDaniel Kurtz 3166cf15fc2SSascha Hauer pwrap: pwrap@1000d000 { 3176cf15fc2SSascha Hauer compatible = "mediatek,mt8173-pwrap"; 3186cf15fc2SSascha Hauer reg = <0 0x1000d000 0 0x1000>; 3196cf15fc2SSascha Hauer reg-names = "pwrap"; 3206cf15fc2SSascha Hauer interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 3216cf15fc2SSascha Hauer resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 3226cf15fc2SSascha Hauer reset-names = "pwrap"; 3236cf15fc2SSascha Hauer clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 3246cf15fc2SSascha Hauer clock-names = "spi", "wrap"; 3256cf15fc2SSascha Hauer }; 3266cf15fc2SSascha Hauer 327404b2819SAndrew-CT Chen vpu: vpu@10020000 { 328404b2819SAndrew-CT Chen compatible = "mediatek,mt8173-vpu"; 329404b2819SAndrew-CT Chen reg = <0 0x10020000 0 0x30000>, 330404b2819SAndrew-CT Chen <0 0x10050000 0 0x100>; 331404b2819SAndrew-CT Chen reg-names = "tcm", "cfg_reg"; 332404b2819SAndrew-CT Chen interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 333404b2819SAndrew-CT Chen clocks = <&topckgen CLK_TOP_SCP_SEL>; 334404b2819SAndrew-CT Chen clock-names = "main"; 335404b2819SAndrew-CT Chen memory-region = <&vpu_dma_reserved>; 336404b2819SAndrew-CT Chen }; 337404b2819SAndrew-CT Chen 338b3a37248SEddie Huang sysirq: intpol-controller@10200620 { 339b3a37248SEddie Huang compatible = "mediatek,mt8173-sysirq", 340b3a37248SEddie Huang "mediatek,mt6577-sysirq"; 341b3a37248SEddie Huang interrupt-controller; 342b3a37248SEddie Huang #interrupt-cells = <3>; 343b3a37248SEddie Huang interrupt-parent = <&gic>; 344b3a37248SEddie Huang reg = <0 0x10200620 0 0x20>; 345b3a37248SEddie Huang }; 346b3a37248SEddie Huang 3475ff6b3a6SYong Wu iommu: iommu@10205000 { 3485ff6b3a6SYong Wu compatible = "mediatek,mt8173-m4u"; 3495ff6b3a6SYong Wu reg = <0 0x10205000 0 0x1000>; 3505ff6b3a6SYong Wu interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 3515ff6b3a6SYong Wu clocks = <&infracfg CLK_INFRA_M4U>; 3525ff6b3a6SYong Wu clock-names = "bclk"; 3535ff6b3a6SYong Wu mediatek,larbs = <&larb0 &larb1 &larb2 3545ff6b3a6SYong Wu &larb3 &larb4 &larb5>; 3555ff6b3a6SYong Wu #iommu-cells = <1>; 3565ff6b3a6SYong Wu }; 3575ff6b3a6SYong Wu 35893e9f5eeSandrew-ct.chen@mediatek.com efuse: efuse@10206000 { 35993e9f5eeSandrew-ct.chen@mediatek.com compatible = "mediatek,mt8173-efuse"; 36093e9f5eeSandrew-ct.chen@mediatek.com reg = <0 0x10206000 0 0x1000>; 36193e9f5eeSandrew-ct.chen@mediatek.com }; 36293e9f5eeSandrew-ct.chen@mediatek.com 363f2ce7014SSascha Hauer apmixedsys: clock-controller@10209000 { 364f2ce7014SSascha Hauer compatible = "mediatek,mt8173-apmixedsys"; 365f2ce7014SSascha Hauer reg = <0 0x10209000 0 0x1000>; 366f2ce7014SSascha Hauer #clock-cells = <1>; 367f2ce7014SSascha Hauer }; 368f2ce7014SSascha Hauer 369b3a37248SEddie Huang gic: interrupt-controller@10220000 { 370b3a37248SEddie Huang compatible = "arm,gic-400"; 371b3a37248SEddie Huang #interrupt-cells = <3>; 372b3a37248SEddie Huang interrupt-parent = <&gic>; 373b3a37248SEddie Huang interrupt-controller; 374b3a37248SEddie Huang reg = <0 0x10221000 0 0x1000>, 375b3a37248SEddie Huang <0 0x10222000 0 0x2000>, 376b3a37248SEddie Huang <0 0x10224000 0 0x2000>, 377b3a37248SEddie Huang <0 0x10226000 0 0x2000>; 378b3a37248SEddie Huang interrupts = <GIC_PPI 9 379b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 380b3a37248SEddie Huang }; 381b3a37248SEddie Huang 382748c7d4dSSascha Hauer auxadc: auxadc@11001000 { 383748c7d4dSSascha Hauer compatible = "mediatek,mt8173-auxadc"; 384748c7d4dSSascha Hauer reg = <0 0x11001000 0 0x1000>; 385748c7d4dSSascha Hauer }; 386748c7d4dSSascha Hauer 387b3a37248SEddie Huang uart0: serial@11002000 { 388b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 389b3a37248SEddie Huang "mediatek,mt6577-uart"; 390b3a37248SEddie Huang reg = <0 0x11002000 0 0x400>; 391b3a37248SEddie Huang interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 3920e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 3930e84faa1SSascha Hauer clock-names = "baud", "bus"; 394b3a37248SEddie Huang status = "disabled"; 395b3a37248SEddie Huang }; 396b3a37248SEddie Huang 397b3a37248SEddie Huang uart1: serial@11003000 { 398b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 399b3a37248SEddie Huang "mediatek,mt6577-uart"; 400b3a37248SEddie Huang reg = <0 0x11003000 0 0x400>; 401b3a37248SEddie Huang interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 4020e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 4030e84faa1SSascha Hauer clock-names = "baud", "bus"; 404b3a37248SEddie Huang status = "disabled"; 405b3a37248SEddie Huang }; 406b3a37248SEddie Huang 407b3a37248SEddie Huang uart2: serial@11004000 { 408b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 409b3a37248SEddie Huang "mediatek,mt6577-uart"; 410b3a37248SEddie Huang reg = <0 0x11004000 0 0x400>; 411b3a37248SEddie Huang interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 4120e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 4130e84faa1SSascha Hauer clock-names = "baud", "bus"; 414b3a37248SEddie Huang status = "disabled"; 415b3a37248SEddie Huang }; 416b3a37248SEddie Huang 417b3a37248SEddie Huang uart3: serial@11005000 { 418b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 419b3a37248SEddie Huang "mediatek,mt6577-uart"; 420b3a37248SEddie Huang reg = <0 0x11005000 0 0x400>; 421b3a37248SEddie Huang interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 4220e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 4230e84faa1SSascha Hauer clock-names = "baud", "bus"; 424b3a37248SEddie Huang status = "disabled"; 425b3a37248SEddie Huang }; 426091cf598SEddie Huang 427091cf598SEddie Huang i2c0: i2c@11007000 { 428091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 429091cf598SEddie Huang reg = <0 0x11007000 0 0x70>, 430091cf598SEddie Huang <0 0x11000100 0 0x80>; 431091cf598SEddie Huang interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 432091cf598SEddie Huang clock-div = <16>; 433091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C0>, 434091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 435091cf598SEddie Huang clock-names = "main", "dma"; 436091cf598SEddie Huang pinctrl-names = "default"; 437091cf598SEddie Huang pinctrl-0 = <&i2c0_pins_a>; 438091cf598SEddie Huang #address-cells = <1>; 439091cf598SEddie Huang #size-cells = <0>; 440091cf598SEddie Huang status = "disabled"; 441091cf598SEddie Huang }; 442091cf598SEddie Huang 443091cf598SEddie Huang i2c1: i2c@11008000 { 444091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 445091cf598SEddie Huang reg = <0 0x11008000 0 0x70>, 446091cf598SEddie Huang <0 0x11000180 0 0x80>; 447091cf598SEddie Huang interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 448091cf598SEddie Huang clock-div = <16>; 449091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C1>, 450091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 451091cf598SEddie Huang clock-names = "main", "dma"; 452091cf598SEddie Huang pinctrl-names = "default"; 453091cf598SEddie Huang pinctrl-0 = <&i2c1_pins_a>; 454091cf598SEddie Huang #address-cells = <1>; 455091cf598SEddie Huang #size-cells = <0>; 456091cf598SEddie Huang status = "disabled"; 457091cf598SEddie Huang }; 458091cf598SEddie Huang 459091cf598SEddie Huang i2c2: i2c@11009000 { 460091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 461091cf598SEddie Huang reg = <0 0x11009000 0 0x70>, 462091cf598SEddie Huang <0 0x11000200 0 0x80>; 463091cf598SEddie Huang interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 464091cf598SEddie Huang clock-div = <16>; 465091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C2>, 466091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 467091cf598SEddie Huang clock-names = "main", "dma"; 468091cf598SEddie Huang pinctrl-names = "default"; 469091cf598SEddie Huang pinctrl-0 = <&i2c2_pins_a>; 470091cf598SEddie Huang #address-cells = <1>; 471091cf598SEddie Huang #size-cells = <0>; 472091cf598SEddie Huang status = "disabled"; 473091cf598SEddie Huang }; 474091cf598SEddie Huang 475b0c936f5SLeilk Liu spi: spi@1100a000 { 476b0c936f5SLeilk Liu compatible = "mediatek,mt8173-spi"; 477b0c936f5SLeilk Liu #address-cells = <1>; 478b0c936f5SLeilk Liu #size-cells = <0>; 479b0c936f5SLeilk Liu reg = <0 0x1100a000 0 0x1000>; 480b0c936f5SLeilk Liu interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 481b0c936f5SLeilk Liu clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 482b0c936f5SLeilk Liu <&topckgen CLK_TOP_SPI_SEL>, 483b0c936f5SLeilk Liu <&pericfg CLK_PERI_SPI0>; 484b0c936f5SLeilk Liu clock-names = "parent-clk", "sel-clk", "spi-clk"; 485b0c936f5SLeilk Liu status = "disabled"; 486b0c936f5SLeilk Liu }; 487b0c936f5SLeilk Liu 488748c7d4dSSascha Hauer thermal: thermal@1100b000 { 489748c7d4dSSascha Hauer #thermal-sensor-cells = <0>; 490748c7d4dSSascha Hauer compatible = "mediatek,mt8173-thermal"; 491748c7d4dSSascha Hauer reg = <0 0x1100b000 0 0x1000>; 492748c7d4dSSascha Hauer interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 493748c7d4dSSascha Hauer clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 494748c7d4dSSascha Hauer clock-names = "therm", "auxadc"; 495748c7d4dSSascha Hauer resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 496748c7d4dSSascha Hauer mediatek,auxadc = <&auxadc>; 497748c7d4dSSascha Hauer mediatek,apmixedsys = <&apmixedsys>; 498748c7d4dSSascha Hauer }; 499748c7d4dSSascha Hauer 50086cb8a88SBayi Cheng nor_flash: spi@1100d000 { 50186cb8a88SBayi Cheng compatible = "mediatek,mt8173-nor"; 50286cb8a88SBayi Cheng reg = <0 0x1100d000 0 0xe0>; 50386cb8a88SBayi Cheng clocks = <&pericfg CLK_PERI_SPI>, 50486cb8a88SBayi Cheng <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 50586cb8a88SBayi Cheng clock-names = "spi", "sf"; 50686cb8a88SBayi Cheng #address-cells = <1>; 50786cb8a88SBayi Cheng #size-cells = <0>; 50886cb8a88SBayi Cheng status = "disabled"; 50986cb8a88SBayi Cheng }; 51086cb8a88SBayi Cheng 5111ee35c05SYingjoe Chen i2c3: i2c@11010000 { 512091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 513091cf598SEddie Huang reg = <0 0x11010000 0 0x70>, 514091cf598SEddie Huang <0 0x11000280 0 0x80>; 515091cf598SEddie Huang interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 516091cf598SEddie Huang clock-div = <16>; 517091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C3>, 518091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 519091cf598SEddie Huang clock-names = "main", "dma"; 520091cf598SEddie Huang pinctrl-names = "default"; 521091cf598SEddie Huang pinctrl-0 = <&i2c3_pins_a>; 522091cf598SEddie Huang #address-cells = <1>; 523091cf598SEddie Huang #size-cells = <0>; 524091cf598SEddie Huang status = "disabled"; 525091cf598SEddie Huang }; 526091cf598SEddie Huang 5271ee35c05SYingjoe Chen i2c4: i2c@11011000 { 528091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 529091cf598SEddie Huang reg = <0 0x11011000 0 0x70>, 530091cf598SEddie Huang <0 0x11000300 0 0x80>; 531091cf598SEddie Huang interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 532091cf598SEddie Huang clock-div = <16>; 533091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C4>, 534091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 535091cf598SEddie Huang clock-names = "main", "dma"; 536091cf598SEddie Huang pinctrl-names = "default"; 537091cf598SEddie Huang pinctrl-0 = <&i2c4_pins_a>; 538091cf598SEddie Huang #address-cells = <1>; 539091cf598SEddie Huang #size-cells = <0>; 540091cf598SEddie Huang status = "disabled"; 541091cf598SEddie Huang }; 542091cf598SEddie Huang 5431ee35c05SYingjoe Chen i2c6: i2c@11013000 { 544091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 545091cf598SEddie Huang reg = <0 0x11013000 0 0x70>, 546091cf598SEddie Huang <0 0x11000080 0 0x80>; 547091cf598SEddie Huang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 548091cf598SEddie Huang clock-div = <16>; 549091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C6>, 550091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 551091cf598SEddie Huang clock-names = "main", "dma"; 552091cf598SEddie Huang pinctrl-names = "default"; 553091cf598SEddie Huang pinctrl-0 = <&i2c6_pins_a>; 554091cf598SEddie Huang #address-cells = <1>; 555091cf598SEddie Huang #size-cells = <0>; 556091cf598SEddie Huang status = "disabled"; 557091cf598SEddie Huang }; 558c02e0e86SKoro Chen 559c02e0e86SKoro Chen afe: audio-controller@11220000 { 560c02e0e86SKoro Chen compatible = "mediatek,mt8173-afe-pcm"; 561c02e0e86SKoro Chen reg = <0 0x11220000 0 0x1000>; 562c02e0e86SKoro Chen interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 563c02e0e86SKoro Chen power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; 564c02e0e86SKoro Chen clocks = <&infracfg CLK_INFRA_AUDIO>, 565c02e0e86SKoro Chen <&topckgen CLK_TOP_AUDIO_SEL>, 566c02e0e86SKoro Chen <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 567c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL1_DIV0>, 568c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL2_DIV0>, 569c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S0_M_SEL>, 570c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S1_M_SEL>, 571c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S2_M_SEL>, 572c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S3_M_SEL>, 573c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S3_B_SEL>; 574c02e0e86SKoro Chen clock-names = "infra_sys_audio_clk", 575c02e0e86SKoro Chen "top_pdn_audio", 576c02e0e86SKoro Chen "top_pdn_aud_intbus", 577c02e0e86SKoro Chen "bck0", 578c02e0e86SKoro Chen "bck1", 579c02e0e86SKoro Chen "i2s0_m", 580c02e0e86SKoro Chen "i2s1_m", 581c02e0e86SKoro Chen "i2s2_m", 582c02e0e86SKoro Chen "i2s3_m", 583c02e0e86SKoro Chen "i2s3_b"; 584c02e0e86SKoro Chen assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 585c02e0e86SKoro Chen <&topckgen CLK_TOP_AUD_2_SEL>; 586c02e0e86SKoro Chen assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 587c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL2>; 588c02e0e86SKoro Chen }; 5899719fa5aSEddie Huang 5909719fa5aSEddie Huang mmc0: mmc@11230000 { 5919719fa5aSEddie Huang compatible = "mediatek,mt8173-mmc", 5929719fa5aSEddie Huang "mediatek,mt8135-mmc"; 5939719fa5aSEddie Huang reg = <0 0x11230000 0 0x1000>; 5949719fa5aSEddie Huang interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 5959719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_0>, 5969719fa5aSEddie Huang <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 5979719fa5aSEddie Huang clock-names = "source", "hclk"; 5989719fa5aSEddie Huang status = "disabled"; 5999719fa5aSEddie Huang }; 6009719fa5aSEddie Huang 6019719fa5aSEddie Huang mmc1: mmc@11240000 { 6029719fa5aSEddie Huang compatible = "mediatek,mt8173-mmc", 6039719fa5aSEddie Huang "mediatek,mt8135-mmc"; 6049719fa5aSEddie Huang reg = <0 0x11240000 0 0x1000>; 6059719fa5aSEddie Huang interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 6069719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_1>, 6079719fa5aSEddie Huang <&topckgen CLK_TOP_AXI_SEL>; 6089719fa5aSEddie Huang clock-names = "source", "hclk"; 6099719fa5aSEddie Huang status = "disabled"; 6109719fa5aSEddie Huang }; 6119719fa5aSEddie Huang 6129719fa5aSEddie Huang mmc2: mmc@11250000 { 6139719fa5aSEddie Huang compatible = "mediatek,mt8173-mmc", 6149719fa5aSEddie Huang "mediatek,mt8135-mmc"; 6159719fa5aSEddie Huang reg = <0 0x11250000 0 0x1000>; 6169719fa5aSEddie Huang interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 6179719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_2>, 6189719fa5aSEddie Huang <&topckgen CLK_TOP_AXI_SEL>; 6199719fa5aSEddie Huang clock-names = "source", "hclk"; 6209719fa5aSEddie Huang status = "disabled"; 6219719fa5aSEddie Huang }; 6229719fa5aSEddie Huang 6239719fa5aSEddie Huang mmc3: mmc@11260000 { 6249719fa5aSEddie Huang compatible = "mediatek,mt8173-mmc", 6259719fa5aSEddie Huang "mediatek,mt8135-mmc"; 6269719fa5aSEddie Huang reg = <0 0x11260000 0 0x1000>; 6279719fa5aSEddie Huang interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 6289719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_3>, 6299719fa5aSEddie Huang <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 6309719fa5aSEddie Huang clock-names = "source", "hclk"; 6319719fa5aSEddie Huang status = "disabled"; 6329719fa5aSEddie Huang }; 63367e56c56SJames Liao 634bfcce47aSChunfeng Yun usb30: usb@11270000 { 635bfcce47aSChunfeng Yun compatible = "mediatek,mt8173-xhci"; 636bfcce47aSChunfeng Yun reg = <0 0x11270000 0 0x1000>, 637bfcce47aSChunfeng Yun <0 0x11280700 0 0x0100>; 638bfcce47aSChunfeng Yun interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 639bfcce47aSChunfeng Yun power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 640bfcce47aSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>, 641bfcce47aSChunfeng Yun <&pericfg CLK_PERI_USB0>, 642bfcce47aSChunfeng Yun <&pericfg CLK_PERI_USB1>; 643bfcce47aSChunfeng Yun clock-names = "sys_ck", 644bfcce47aSChunfeng Yun "wakeup_deb_p0", 645bfcce47aSChunfeng Yun "wakeup_deb_p1"; 646bfcce47aSChunfeng Yun phys = <&phy_port0 PHY_TYPE_USB3>, 647bfcce47aSChunfeng Yun <&phy_port1 PHY_TYPE_USB2>; 648bfcce47aSChunfeng Yun mediatek,syscon-wakeup = <&pericfg>; 649bfcce47aSChunfeng Yun status = "okay"; 650bfcce47aSChunfeng Yun }; 651bfcce47aSChunfeng Yun 652bfcce47aSChunfeng Yun u3phy: usb-phy@11290000 { 653bfcce47aSChunfeng Yun compatible = "mediatek,mt8173-u3phy"; 654bfcce47aSChunfeng Yun reg = <0 0x11290000 0 0x800>; 655bfcce47aSChunfeng Yun clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 656bfcce47aSChunfeng Yun clock-names = "u3phya_ref"; 657bfcce47aSChunfeng Yun #address-cells = <2>; 658bfcce47aSChunfeng Yun #size-cells = <2>; 659bfcce47aSChunfeng Yun ranges; 660bfcce47aSChunfeng Yun status = "okay"; 661bfcce47aSChunfeng Yun 662bfcce47aSChunfeng Yun phy_port0: port@11290800 { 663bfcce47aSChunfeng Yun reg = <0 0x11290800 0 0x800>; 664bfcce47aSChunfeng Yun #phy-cells = <1>; 665bfcce47aSChunfeng Yun status = "okay"; 666bfcce47aSChunfeng Yun }; 667bfcce47aSChunfeng Yun 668bfcce47aSChunfeng Yun phy_port1: port@11291000 { 669bfcce47aSChunfeng Yun reg = <0 0x11291000 0 0x800>; 670bfcce47aSChunfeng Yun #phy-cells = <1>; 671bfcce47aSChunfeng Yun status = "okay"; 672bfcce47aSChunfeng Yun }; 673bfcce47aSChunfeng Yun }; 674bfcce47aSChunfeng Yun 67567e56c56SJames Liao mmsys: clock-controller@14000000 { 67667e56c56SJames Liao compatible = "mediatek,mt8173-mmsys", "syscon"; 67767e56c56SJames Liao reg = <0 0x14000000 0 0x1000>; 67867e56c56SJames Liao #clock-cells = <1>; 67967e56c56SJames Liao }; 68067e56c56SJames Liao 68161aee934SYH Huang pwm0: pwm@1401e000 { 68261aee934SYH Huang compatible = "mediatek,mt8173-disp-pwm", 68361aee934SYH Huang "mediatek,mt6595-disp-pwm"; 68461aee934SYH Huang reg = <0 0x1401e000 0 0x1000>; 68561aee934SYH Huang #pwm-cells = <2>; 68661aee934SYH Huang clocks = <&mmsys CLK_MM_DISP_PWM026M>, 68761aee934SYH Huang <&mmsys CLK_MM_DISP_PWM0MM>; 68861aee934SYH Huang clock-names = "main", "mm"; 68961aee934SYH Huang status = "disabled"; 69061aee934SYH Huang }; 69161aee934SYH Huang 69261aee934SYH Huang pwm1: pwm@1401f000 { 69361aee934SYH Huang compatible = "mediatek,mt8173-disp-pwm", 69461aee934SYH Huang "mediatek,mt6595-disp-pwm"; 69561aee934SYH Huang reg = <0 0x1401f000 0 0x1000>; 69661aee934SYH Huang #pwm-cells = <2>; 69761aee934SYH Huang clocks = <&mmsys CLK_MM_DISP_PWM126M>, 69861aee934SYH Huang <&mmsys CLK_MM_DISP_PWM1MM>; 69961aee934SYH Huang clock-names = "main", "mm"; 70061aee934SYH Huang status = "disabled"; 70161aee934SYH Huang }; 70261aee934SYH Huang 7035ff6b3a6SYong Wu larb0: larb@14021000 { 7045ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 7055ff6b3a6SYong Wu reg = <0 0x14021000 0 0x1000>; 7065ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 7075ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 7085ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_LARB0>, 7095ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_LARB0>; 7105ff6b3a6SYong Wu clock-names = "apb", "smi"; 7115ff6b3a6SYong Wu }; 7125ff6b3a6SYong Wu 7135ff6b3a6SYong Wu smi_common: smi@14022000 { 7145ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-common"; 7155ff6b3a6SYong Wu reg = <0 0x14022000 0 0x1000>; 7165ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 7175ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_COMMON>, 7185ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_COMMON>; 7195ff6b3a6SYong Wu clock-names = "apb", "smi"; 7205ff6b3a6SYong Wu }; 7215ff6b3a6SYong Wu 7225ff6b3a6SYong Wu larb4: larb@14027000 { 7235ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 7245ff6b3a6SYong Wu reg = <0 0x14027000 0 0x1000>; 7255ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 7265ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 7275ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_LARB4>, 7285ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_LARB4>; 7295ff6b3a6SYong Wu clock-names = "apb", "smi"; 7305ff6b3a6SYong Wu }; 7315ff6b3a6SYong Wu 73267e56c56SJames Liao imgsys: clock-controller@15000000 { 73367e56c56SJames Liao compatible = "mediatek,mt8173-imgsys", "syscon"; 73467e56c56SJames Liao reg = <0 0x15000000 0 0x1000>; 73567e56c56SJames Liao #clock-cells = <1>; 73667e56c56SJames Liao }; 73767e56c56SJames Liao 7385ff6b3a6SYong Wu larb2: larb@15001000 { 7395ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 7405ff6b3a6SYong Wu reg = <0 0x15001000 0 0x1000>; 7415ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 7425ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>; 7435ff6b3a6SYong Wu clocks = <&imgsys CLK_IMG_LARB2_SMI>, 7445ff6b3a6SYong Wu <&imgsys CLK_IMG_LARB2_SMI>; 7455ff6b3a6SYong Wu clock-names = "apb", "smi"; 7465ff6b3a6SYong Wu }; 7475ff6b3a6SYong Wu 74867e56c56SJames Liao vdecsys: clock-controller@16000000 { 74967e56c56SJames Liao compatible = "mediatek,mt8173-vdecsys", "syscon"; 75067e56c56SJames Liao reg = <0 0x16000000 0 0x1000>; 75167e56c56SJames Liao #clock-cells = <1>; 75267e56c56SJames Liao }; 75367e56c56SJames Liao 7545ff6b3a6SYong Wu larb1: larb@16010000 { 7555ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 7565ff6b3a6SYong Wu reg = <0 0x16010000 0 0x1000>; 7575ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 7585ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 7595ff6b3a6SYong Wu clocks = <&vdecsys CLK_VDEC_CKEN>, 7605ff6b3a6SYong Wu <&vdecsys CLK_VDEC_LARB_CKEN>; 7615ff6b3a6SYong Wu clock-names = "apb", "smi"; 7625ff6b3a6SYong Wu }; 7635ff6b3a6SYong Wu 76467e56c56SJames Liao vencsys: clock-controller@18000000 { 76567e56c56SJames Liao compatible = "mediatek,mt8173-vencsys", "syscon"; 76667e56c56SJames Liao reg = <0 0x18000000 0 0x1000>; 76767e56c56SJames Liao #clock-cells = <1>; 76867e56c56SJames Liao }; 76967e56c56SJames Liao 7705ff6b3a6SYong Wu larb3: larb@18001000 { 7715ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 7725ff6b3a6SYong Wu reg = <0 0x18001000 0 0x1000>; 7735ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 7745ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 7755ff6b3a6SYong Wu clocks = <&vencsys CLK_VENC_CKE1>, 7765ff6b3a6SYong Wu <&vencsys CLK_VENC_CKE0>; 7775ff6b3a6SYong Wu clock-names = "apb", "smi"; 7785ff6b3a6SYong Wu }; 7795ff6b3a6SYong Wu 78067e56c56SJames Liao vencltsys: clock-controller@19000000 { 78167e56c56SJames Liao compatible = "mediatek,mt8173-vencltsys", "syscon"; 78267e56c56SJames Liao reg = <0 0x19000000 0 0x1000>; 78367e56c56SJames Liao #clock-cells = <1>; 78467e56c56SJames Liao }; 7855ff6b3a6SYong Wu 7865ff6b3a6SYong Wu larb5: larb@19001000 { 7875ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 7885ff6b3a6SYong Wu reg = <0 0x19001000 0 0x1000>; 7895ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 7905ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; 7915ff6b3a6SYong Wu clocks = <&vencltsys CLK_VENCLT_CKE1>, 7925ff6b3a6SYong Wu <&vencltsys CLK_VENCLT_CKE0>; 7935ff6b3a6SYong Wu clock-names = "apb", "smi"; 7945ff6b3a6SYong Wu }; 795b3a37248SEddie Huang }; 796b3a37248SEddie Huang}; 797b3a37248SEddie Huang 798