1b3a37248SEddie Huang/* 2b3a37248SEddie Huang * Copyright (c) 2014 MediaTek Inc. 3b3a37248SEddie Huang * Author: Eddie Huang <eddie.huang@mediatek.com> 4b3a37248SEddie Huang * 5b3a37248SEddie Huang * This program is free software; you can redistribute it and/or modify 6b3a37248SEddie Huang * it under the terms of the GNU General Public License version 2 as 7b3a37248SEddie Huang * published by the Free Software Foundation. 8b3a37248SEddie Huang * 9b3a37248SEddie Huang * This program is distributed in the hope that it will be useful, 10b3a37248SEddie Huang * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11b3a37248SEddie Huang * GNU General Public License for more details. 12b3a37248SEddie Huang */ 13b3a37248SEddie Huang 14b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/irq.h> 15b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/arm-gic.h> 16359f9365SHongzhou Yang#include "mt8173-pinfunc.h" 17b3a37248SEddie Huang 18b3a37248SEddie Huang/ { 19b3a37248SEddie Huang compatible = "mediatek,mt8173"; 20b3a37248SEddie Huang interrupt-parent = <&sysirq>; 21b3a37248SEddie Huang #address-cells = <2>; 22b3a37248SEddie Huang #size-cells = <2>; 23b3a37248SEddie Huang 24b3a37248SEddie Huang cpus { 25b3a37248SEddie Huang #address-cells = <1>; 26b3a37248SEddie Huang #size-cells = <0>; 27b3a37248SEddie Huang 28b3a37248SEddie Huang cpu-map { 29b3a37248SEddie Huang cluster0 { 30b3a37248SEddie Huang core0 { 31b3a37248SEddie Huang cpu = <&cpu0>; 32b3a37248SEddie Huang }; 33b3a37248SEddie Huang core1 { 34b3a37248SEddie Huang cpu = <&cpu1>; 35b3a37248SEddie Huang }; 36b3a37248SEddie Huang }; 37b3a37248SEddie Huang 38b3a37248SEddie Huang cluster1 { 39b3a37248SEddie Huang core0 { 40b3a37248SEddie Huang cpu = <&cpu2>; 41b3a37248SEddie Huang }; 42b3a37248SEddie Huang core1 { 43b3a37248SEddie Huang cpu = <&cpu3>; 44b3a37248SEddie Huang }; 45b3a37248SEddie Huang }; 46b3a37248SEddie Huang }; 47b3a37248SEddie Huang 48b3a37248SEddie Huang cpu0: cpu@0 { 49b3a37248SEddie Huang device_type = "cpu"; 50b3a37248SEddie Huang compatible = "arm,cortex-a53"; 51b3a37248SEddie Huang reg = <0x000>; 52b3a37248SEddie Huang }; 53b3a37248SEddie Huang 54b3a37248SEddie Huang cpu1: cpu@1 { 55b3a37248SEddie Huang device_type = "cpu"; 56b3a37248SEddie Huang compatible = "arm,cortex-a53"; 57b3a37248SEddie Huang reg = <0x001>; 58b3a37248SEddie Huang enable-method = "psci"; 59b3a37248SEddie Huang }; 60b3a37248SEddie Huang 61b3a37248SEddie Huang cpu2: cpu@100 { 62b3a37248SEddie Huang device_type = "cpu"; 63b3a37248SEddie Huang compatible = "arm,cortex-a57"; 64b3a37248SEddie Huang reg = <0x100>; 65b3a37248SEddie Huang enable-method = "psci"; 66b3a37248SEddie Huang }; 67b3a37248SEddie Huang 68b3a37248SEddie Huang cpu3: cpu@101 { 69b3a37248SEddie Huang device_type = "cpu"; 70b3a37248SEddie Huang compatible = "arm,cortex-a57"; 71b3a37248SEddie Huang reg = <0x101>; 72b3a37248SEddie Huang enable-method = "psci"; 73b3a37248SEddie Huang }; 74b3a37248SEddie Huang }; 75b3a37248SEddie Huang 76b3a37248SEddie Huang psci { 77b3a37248SEddie Huang compatible = "arm,psci"; 78b3a37248SEddie Huang method = "smc"; 79b3a37248SEddie Huang cpu_suspend = <0x84000001>; 80b3a37248SEddie Huang cpu_off = <0x84000002>; 81b3a37248SEddie Huang cpu_on = <0x84000003>; 82b3a37248SEddie Huang }; 83b3a37248SEddie Huang 84b3a37248SEddie Huang uart_clk: dummy26m { 85b3a37248SEddie Huang compatible = "fixed-clock"; 86b3a37248SEddie Huang clock-frequency = <26000000>; 87b3a37248SEddie Huang #clock-cells = <0>; 88b3a37248SEddie Huang }; 89b3a37248SEddie Huang 90b3a37248SEddie Huang timer { 91b3a37248SEddie Huang compatible = "arm,armv8-timer"; 92b3a37248SEddie Huang interrupt-parent = <&gic>; 93b3a37248SEddie Huang interrupts = <GIC_PPI 13 94b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 95b3a37248SEddie Huang <GIC_PPI 14 96b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 97b3a37248SEddie Huang <GIC_PPI 11 98b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 99b3a37248SEddie Huang <GIC_PPI 10 100b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 101b3a37248SEddie Huang }; 102b3a37248SEddie Huang 103b3a37248SEddie Huang soc { 104b3a37248SEddie Huang #address-cells = <2>; 105b3a37248SEddie Huang #size-cells = <2>; 106b3a37248SEddie Huang compatible = "simple-bus"; 107b3a37248SEddie Huang ranges; 108b3a37248SEddie Huang 109359f9365SHongzhou Yang syscfg_pctl_a: syscfg_pctl_a@10005000 { 110359f9365SHongzhou Yang compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 111359f9365SHongzhou Yang reg = <0 0x10005000 0 0x1000>; 112359f9365SHongzhou Yang }; 113359f9365SHongzhou Yang 114359f9365SHongzhou Yang pio: pinctrl@0x10005000 { 115359f9365SHongzhou Yang compatible = "mediatek,mt8173-pinctrl"; 116359f9365SHongzhou Yang reg = <0 0x1000B000 0 0x1000>; 117359f9365SHongzhou Yang mediatek,pctl-regmap = <&syscfg_pctl_a>; 118359f9365SHongzhou Yang pins-are-numbered; 119359f9365SHongzhou Yang gpio-controller; 120359f9365SHongzhou Yang #gpio-cells = <2>; 121359f9365SHongzhou Yang interrupt-controller; 122359f9365SHongzhou Yang #interrupt-cells = <2>; 123359f9365SHongzhou Yang interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 124359f9365SHongzhou Yang <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 125359f9365SHongzhou Yang <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 126359f9365SHongzhou Yang }; 127359f9365SHongzhou Yang 128b3a37248SEddie Huang sysirq: intpol-controller@10200620 { 129b3a37248SEddie Huang compatible = "mediatek,mt8173-sysirq", 130b3a37248SEddie Huang "mediatek,mt6577-sysirq"; 131b3a37248SEddie Huang interrupt-controller; 132b3a37248SEddie Huang #interrupt-cells = <3>; 133b3a37248SEddie Huang interrupt-parent = <&gic>; 134b3a37248SEddie Huang reg = <0 0x10200620 0 0x20>; 135b3a37248SEddie Huang }; 136b3a37248SEddie Huang 137b3a37248SEddie Huang gic: interrupt-controller@10220000 { 138b3a37248SEddie Huang compatible = "arm,gic-400"; 139b3a37248SEddie Huang #interrupt-cells = <3>; 140b3a37248SEddie Huang interrupt-parent = <&gic>; 141b3a37248SEddie Huang interrupt-controller; 142b3a37248SEddie Huang reg = <0 0x10221000 0 0x1000>, 143b3a37248SEddie Huang <0 0x10222000 0 0x2000>, 144b3a37248SEddie Huang <0 0x10224000 0 0x2000>, 145b3a37248SEddie Huang <0 0x10226000 0 0x2000>; 146b3a37248SEddie Huang interrupts = <GIC_PPI 9 147b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 148b3a37248SEddie Huang }; 149b3a37248SEddie Huang 150b3a37248SEddie Huang uart0: serial@11002000 { 151b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 152b3a37248SEddie Huang "mediatek,mt6577-uart"; 153b3a37248SEddie Huang reg = <0 0x11002000 0 0x400>; 154b3a37248SEddie Huang interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 155b3a37248SEddie Huang clocks = <&uart_clk>; 156b3a37248SEddie Huang status = "disabled"; 157b3a37248SEddie Huang }; 158b3a37248SEddie Huang 159b3a37248SEddie Huang uart1: serial@11003000 { 160b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 161b3a37248SEddie Huang "mediatek,mt6577-uart"; 162b3a37248SEddie Huang reg = <0 0x11003000 0 0x400>; 163b3a37248SEddie Huang interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 164b3a37248SEddie Huang clocks = <&uart_clk>; 165b3a37248SEddie Huang status = "disabled"; 166b3a37248SEddie Huang }; 167b3a37248SEddie Huang 168b3a37248SEddie Huang uart2: serial@11004000 { 169b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 170b3a37248SEddie Huang "mediatek,mt6577-uart"; 171b3a37248SEddie Huang reg = <0 0x11004000 0 0x400>; 172b3a37248SEddie Huang interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 173b3a37248SEddie Huang clocks = <&uart_clk>; 174b3a37248SEddie Huang status = "disabled"; 175b3a37248SEddie Huang }; 176b3a37248SEddie Huang 177b3a37248SEddie Huang uart3: serial@11005000 { 178b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 179b3a37248SEddie Huang "mediatek,mt6577-uart"; 180b3a37248SEddie Huang reg = <0 0x11005000 0 0x400>; 181b3a37248SEddie Huang interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 182b3a37248SEddie Huang clocks = <&uart_clk>; 183b3a37248SEddie Huang status = "disabled"; 184b3a37248SEddie Huang }; 185b3a37248SEddie Huang }; 186b3a37248SEddie Huang 187b3a37248SEddie Huang}; 188b3a37248SEddie Huang 189