1b3a37248SEddie Huang/* 2b3a37248SEddie Huang * Copyright (c) 2014 MediaTek Inc. 3b3a37248SEddie Huang * Author: Eddie Huang <eddie.huang@mediatek.com> 4b3a37248SEddie Huang * 5b3a37248SEddie Huang * This program is free software; you can redistribute it and/or modify 6b3a37248SEddie Huang * it under the terms of the GNU General Public License version 2 as 7b3a37248SEddie Huang * published by the Free Software Foundation. 8b3a37248SEddie Huang * 9b3a37248SEddie Huang * This program is distributed in the hope that it will be useful, 10b3a37248SEddie Huang * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11b3a37248SEddie Huang * GNU General Public License for more details. 12b3a37248SEddie Huang */ 13b3a37248SEddie Huang 14f2ce7014SSascha Hauer#include <dt-bindings/clock/mt8173-clk.h> 15b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/irq.h> 16b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/arm-gic.h> 176cf15fc2SSascha Hauer#include <dt-bindings/reset-controller/mt8173-resets.h> 18359f9365SHongzhou Yang#include "mt8173-pinfunc.h" 19b3a37248SEddie Huang 20b3a37248SEddie Huang/ { 21b3a37248SEddie Huang compatible = "mediatek,mt8173"; 22b3a37248SEddie Huang interrupt-parent = <&sysirq>; 23b3a37248SEddie Huang #address-cells = <2>; 24b3a37248SEddie Huang #size-cells = <2>; 25b3a37248SEddie Huang 26b3a37248SEddie Huang cpus { 27b3a37248SEddie Huang #address-cells = <1>; 28b3a37248SEddie Huang #size-cells = <0>; 29b3a37248SEddie Huang 30b3a37248SEddie Huang cpu-map { 31b3a37248SEddie Huang cluster0 { 32b3a37248SEddie Huang core0 { 33b3a37248SEddie Huang cpu = <&cpu0>; 34b3a37248SEddie Huang }; 35b3a37248SEddie Huang core1 { 36b3a37248SEddie Huang cpu = <&cpu1>; 37b3a37248SEddie Huang }; 38b3a37248SEddie Huang }; 39b3a37248SEddie Huang 40b3a37248SEddie Huang cluster1 { 41b3a37248SEddie Huang core0 { 42b3a37248SEddie Huang cpu = <&cpu2>; 43b3a37248SEddie Huang }; 44b3a37248SEddie Huang core1 { 45b3a37248SEddie Huang cpu = <&cpu3>; 46b3a37248SEddie Huang }; 47b3a37248SEddie Huang }; 48b3a37248SEddie Huang }; 49b3a37248SEddie Huang 50b3a37248SEddie Huang cpu0: cpu@0 { 51b3a37248SEddie Huang device_type = "cpu"; 52b3a37248SEddie Huang compatible = "arm,cortex-a53"; 53b3a37248SEddie Huang reg = <0x000>; 54b3a37248SEddie Huang }; 55b3a37248SEddie Huang 56b3a37248SEddie Huang cpu1: cpu@1 { 57b3a37248SEddie Huang device_type = "cpu"; 58b3a37248SEddie Huang compatible = "arm,cortex-a53"; 59b3a37248SEddie Huang reg = <0x001>; 60b3a37248SEddie Huang enable-method = "psci"; 61b3a37248SEddie Huang }; 62b3a37248SEddie Huang 63b3a37248SEddie Huang cpu2: cpu@100 { 64b3a37248SEddie Huang device_type = "cpu"; 65b3a37248SEddie Huang compatible = "arm,cortex-a57"; 66b3a37248SEddie Huang reg = <0x100>; 67b3a37248SEddie Huang enable-method = "psci"; 68b3a37248SEddie Huang }; 69b3a37248SEddie Huang 70b3a37248SEddie Huang cpu3: cpu@101 { 71b3a37248SEddie Huang device_type = "cpu"; 72b3a37248SEddie Huang compatible = "arm,cortex-a57"; 73b3a37248SEddie Huang reg = <0x101>; 74b3a37248SEddie Huang enable-method = "psci"; 75b3a37248SEddie Huang }; 76b3a37248SEddie Huang }; 77b3a37248SEddie Huang 78b3a37248SEddie Huang psci { 79b3a37248SEddie Huang compatible = "arm,psci"; 80b3a37248SEddie Huang method = "smc"; 81b3a37248SEddie Huang cpu_suspend = <0x84000001>; 82b3a37248SEddie Huang cpu_off = <0x84000002>; 83b3a37248SEddie Huang cpu_on = <0x84000003>; 84b3a37248SEddie Huang }; 85b3a37248SEddie Huang 86f2ce7014SSascha Hauer clk26m: oscillator@0 { 87f2ce7014SSascha Hauer compatible = "fixed-clock"; 88f2ce7014SSascha Hauer #clock-cells = <0>; 89f2ce7014SSascha Hauer clock-frequency = <26000000>; 90f2ce7014SSascha Hauer clock-output-names = "clk26m"; 91f2ce7014SSascha Hauer }; 92f2ce7014SSascha Hauer 93f2ce7014SSascha Hauer clk32k: oscillator@1 { 94f2ce7014SSascha Hauer compatible = "fixed-clock"; 95f2ce7014SSascha Hauer #clock-cells = <0>; 96f2ce7014SSascha Hauer clock-frequency = <32000>; 97f2ce7014SSascha Hauer clock-output-names = "clk32k"; 98f2ce7014SSascha Hauer }; 99f2ce7014SSascha Hauer 100b3a37248SEddie Huang timer { 101b3a37248SEddie Huang compatible = "arm,armv8-timer"; 102b3a37248SEddie Huang interrupt-parent = <&gic>; 103b3a37248SEddie Huang interrupts = <GIC_PPI 13 104b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 105b3a37248SEddie Huang <GIC_PPI 14 106b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 107b3a37248SEddie Huang <GIC_PPI 11 108b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 109b3a37248SEddie Huang <GIC_PPI 10 110b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 111b3a37248SEddie Huang }; 112b3a37248SEddie Huang 113b3a37248SEddie Huang soc { 114b3a37248SEddie Huang #address-cells = <2>; 115b3a37248SEddie Huang #size-cells = <2>; 116b3a37248SEddie Huang compatible = "simple-bus"; 117b3a37248SEddie Huang ranges; 118b3a37248SEddie Huang 119f2ce7014SSascha Hauer topckgen: clock-controller@10000000 { 120f2ce7014SSascha Hauer compatible = "mediatek,mt8173-topckgen"; 121f2ce7014SSascha Hauer reg = <0 0x10000000 0 0x1000>; 122f2ce7014SSascha Hauer #clock-cells = <1>; 123f2ce7014SSascha Hauer }; 124f2ce7014SSascha Hauer 125f2ce7014SSascha Hauer infracfg: power-controller@10001000 { 126f2ce7014SSascha Hauer compatible = "mediatek,mt8173-infracfg", "syscon"; 127f2ce7014SSascha Hauer reg = <0 0x10001000 0 0x1000>; 128f2ce7014SSascha Hauer #clock-cells = <1>; 129f2ce7014SSascha Hauer #reset-cells = <1>; 130f2ce7014SSascha Hauer }; 131f2ce7014SSascha Hauer 132f2ce7014SSascha Hauer pericfg: power-controller@10003000 { 133f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pericfg", "syscon"; 134f2ce7014SSascha Hauer reg = <0 0x10003000 0 0x1000>; 135f2ce7014SSascha Hauer #clock-cells = <1>; 136f2ce7014SSascha Hauer #reset-cells = <1>; 137f2ce7014SSascha Hauer }; 138f2ce7014SSascha Hauer 139f2ce7014SSascha Hauer syscfg_pctl_a: syscfg_pctl_a@10005000 { 140f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 141f2ce7014SSascha Hauer reg = <0 0x10005000 0 0x1000>; 142f2ce7014SSascha Hauer }; 143f2ce7014SSascha Hauer 144f2ce7014SSascha Hauer pio: pinctrl@0x10005000 { 145359f9365SHongzhou Yang compatible = "mediatek,mt8173-pinctrl"; 1466769b93cSYingjoe Chen reg = <0 0x1000b000 0 0x1000>; 147359f9365SHongzhou Yang mediatek,pctl-regmap = <&syscfg_pctl_a>; 148359f9365SHongzhou Yang pins-are-numbered; 149359f9365SHongzhou Yang gpio-controller; 150359f9365SHongzhou Yang #gpio-cells = <2>; 151359f9365SHongzhou Yang interrupt-controller; 152359f9365SHongzhou Yang #interrupt-cells = <2>; 153359f9365SHongzhou Yang interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 154359f9365SHongzhou Yang <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 155359f9365SHongzhou Yang <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 156359f9365SHongzhou Yang }; 157359f9365SHongzhou Yang 1586769b93cSYingjoe Chen syscfg_pctl_a: syscfg_pctl_a@10005000 { 1596769b93cSYingjoe Chen compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 1606769b93cSYingjoe Chen reg = <0 0x10005000 0 0x1000>; 1616769b93cSYingjoe Chen }; 1626769b93cSYingjoe Chen 16313421b3eSEddie Huang watchdog: watchdog@10007000 { 16413421b3eSEddie Huang compatible = "mediatek,mt8173-wdt", 16513421b3eSEddie Huang "mediatek,mt6589-wdt"; 16613421b3eSEddie Huang reg = <0 0x10007000 0 0x100>; 16713421b3eSEddie Huang }; 16813421b3eSEddie Huang 1696cf15fc2SSascha Hauer pwrap: pwrap@1000d000 { 1706cf15fc2SSascha Hauer compatible = "mediatek,mt8173-pwrap"; 1716cf15fc2SSascha Hauer reg = <0 0x1000d000 0 0x1000>; 1726cf15fc2SSascha Hauer reg-names = "pwrap"; 1736cf15fc2SSascha Hauer interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1746cf15fc2SSascha Hauer resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 1756cf15fc2SSascha Hauer reset-names = "pwrap"; 1766cf15fc2SSascha Hauer clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 1776cf15fc2SSascha Hauer clock-names = "spi", "wrap"; 1786cf15fc2SSascha Hauer }; 1796cf15fc2SSascha Hauer 180b3a37248SEddie Huang sysirq: intpol-controller@10200620 { 181b3a37248SEddie Huang compatible = "mediatek,mt8173-sysirq", 182b3a37248SEddie Huang "mediatek,mt6577-sysirq"; 183b3a37248SEddie Huang interrupt-controller; 184b3a37248SEddie Huang #interrupt-cells = <3>; 185b3a37248SEddie Huang interrupt-parent = <&gic>; 186b3a37248SEddie Huang reg = <0 0x10200620 0 0x20>; 187b3a37248SEddie Huang }; 188b3a37248SEddie Huang 189f2ce7014SSascha Hauer apmixedsys: clock-controller@10209000 { 190f2ce7014SSascha Hauer compatible = "mediatek,mt8173-apmixedsys"; 191f2ce7014SSascha Hauer reg = <0 0x10209000 0 0x1000>; 192f2ce7014SSascha Hauer #clock-cells = <1>; 193f2ce7014SSascha Hauer }; 194f2ce7014SSascha Hauer 195b3a37248SEddie Huang gic: interrupt-controller@10220000 { 196b3a37248SEddie Huang compatible = "arm,gic-400"; 197b3a37248SEddie Huang #interrupt-cells = <3>; 198b3a37248SEddie Huang interrupt-parent = <&gic>; 199b3a37248SEddie Huang interrupt-controller; 200b3a37248SEddie Huang reg = <0 0x10221000 0 0x1000>, 201b3a37248SEddie Huang <0 0x10222000 0 0x2000>, 202b3a37248SEddie Huang <0 0x10224000 0 0x2000>, 203b3a37248SEddie Huang <0 0x10226000 0 0x2000>; 204b3a37248SEddie Huang interrupts = <GIC_PPI 9 205b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 206b3a37248SEddie Huang }; 207b3a37248SEddie Huang 208b3a37248SEddie Huang uart0: serial@11002000 { 209b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 210b3a37248SEddie Huang "mediatek,mt6577-uart"; 211b3a37248SEddie Huang reg = <0 0x11002000 0 0x400>; 212b3a37248SEddie Huang interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 2130e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 2140e84faa1SSascha Hauer clock-names = "baud", "bus"; 215b3a37248SEddie Huang status = "disabled"; 216b3a37248SEddie Huang }; 217b3a37248SEddie Huang 218b3a37248SEddie Huang uart1: serial@11003000 { 219b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 220b3a37248SEddie Huang "mediatek,mt6577-uart"; 221b3a37248SEddie Huang reg = <0 0x11003000 0 0x400>; 222b3a37248SEddie Huang interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 2230e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 2240e84faa1SSascha Hauer clock-names = "baud", "bus"; 225b3a37248SEddie Huang status = "disabled"; 226b3a37248SEddie Huang }; 227b3a37248SEddie Huang 228b3a37248SEddie Huang uart2: serial@11004000 { 229b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 230b3a37248SEddie Huang "mediatek,mt6577-uart"; 231b3a37248SEddie Huang reg = <0 0x11004000 0 0x400>; 232b3a37248SEddie Huang interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 2330e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 2340e84faa1SSascha Hauer clock-names = "baud", "bus"; 235b3a37248SEddie Huang status = "disabled"; 236b3a37248SEddie Huang }; 237b3a37248SEddie Huang 238b3a37248SEddie Huang uart3: serial@11005000 { 239b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 240b3a37248SEddie Huang "mediatek,mt6577-uart"; 241b3a37248SEddie Huang reg = <0 0x11005000 0 0x400>; 242b3a37248SEddie Huang interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 2430e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 2440e84faa1SSascha Hauer clock-names = "baud", "bus"; 245b3a37248SEddie Huang status = "disabled"; 246b3a37248SEddie Huang }; 247b3a37248SEddie Huang }; 248b3a37248SEddie Huang}; 249b3a37248SEddie Huang 250