1b3a37248SEddie Huang/* 2b3a37248SEddie Huang * Copyright (c) 2014 MediaTek Inc. 3b3a37248SEddie Huang * Author: Eddie Huang <eddie.huang@mediatek.com> 4b3a37248SEddie Huang * 5b3a37248SEddie Huang * This program is free software; you can redistribute it and/or modify 6b3a37248SEddie Huang * it under the terms of the GNU General Public License version 2 as 7b3a37248SEddie Huang * published by the Free Software Foundation. 8b3a37248SEddie Huang * 9b3a37248SEddie Huang * This program is distributed in the hope that it will be useful, 10b3a37248SEddie Huang * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11b3a37248SEddie Huang * GNU General Public License for more details. 12b3a37248SEddie Huang */ 13b3a37248SEddie Huang 14f2ce7014SSascha Hauer#include <dt-bindings/clock/mt8173-clk.h> 15b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/irq.h> 16b3a37248SEddie Huang#include <dt-bindings/interrupt-controller/arm-gic.h> 175ff6b3a6SYong Wu#include <dt-bindings/memory/mt8173-larb-port.h> 18bfcce47aSChunfeng Yun#include <dt-bindings/phy/phy.h> 19c02e0e86SKoro Chen#include <dt-bindings/power/mt8173-power.h> 20967313e2SPhilipp Zabel#include <dt-bindings/reset/mt8173-resets.h> 21c2e66b8fSHoulong Wei#include <dt-bindings/gce/mt8173-gce.h> 22359f9365SHongzhou Yang#include "mt8173-pinfunc.h" 23b3a37248SEddie Huang 24b3a37248SEddie Huang/ { 25b3a37248SEddie Huang compatible = "mediatek,mt8173"; 26b3a37248SEddie Huang interrupt-parent = <&sysirq>; 27b3a37248SEddie Huang #address-cells = <2>; 28b3a37248SEddie Huang #size-cells = <2>; 29b3a37248SEddie Huang 3081ad4dbaSCK Hu aliases { 3181ad4dbaSCK Hu ovl0 = &ovl0; 3281ad4dbaSCK Hu ovl1 = &ovl1; 3381ad4dbaSCK Hu rdma0 = &rdma0; 3481ad4dbaSCK Hu rdma1 = &rdma1; 3581ad4dbaSCK Hu rdma2 = &rdma2; 3681ad4dbaSCK Hu wdma0 = &wdma0; 3781ad4dbaSCK Hu wdma1 = &wdma1; 3881ad4dbaSCK Hu color0 = &color0; 3981ad4dbaSCK Hu color1 = &color1; 4081ad4dbaSCK Hu split0 = &split0; 4181ad4dbaSCK Hu split1 = &split1; 4281ad4dbaSCK Hu dpi0 = &dpi0; 4381ad4dbaSCK Hu dsi0 = &dsi0; 4481ad4dbaSCK Hu dsi1 = &dsi1; 45989b292aSMinghsiu Tsai mdp_rdma0 = &mdp_rdma0; 46989b292aSMinghsiu Tsai mdp_rdma1 = &mdp_rdma1; 47989b292aSMinghsiu Tsai mdp_rsz0 = &mdp_rsz0; 48989b292aSMinghsiu Tsai mdp_rsz1 = &mdp_rsz1; 49989b292aSMinghsiu Tsai mdp_rsz2 = &mdp_rsz2; 50989b292aSMinghsiu Tsai mdp_wdma0 = &mdp_wdma0; 51989b292aSMinghsiu Tsai mdp_wrot0 = &mdp_wrot0; 52989b292aSMinghsiu Tsai mdp_wrot1 = &mdp_wrot1; 5381ad4dbaSCK Hu }; 5481ad4dbaSCK Hu 55da85a3afSAndrew-sh Cheng cluster0_opp: opp_table0 { 56da85a3afSAndrew-sh Cheng compatible = "operating-points-v2"; 57da85a3afSAndrew-sh Cheng opp-shared; 58da85a3afSAndrew-sh Cheng opp-507000000 { 59da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <507000000>; 60da85a3afSAndrew-sh Cheng opp-microvolt = <859000>; 61da85a3afSAndrew-sh Cheng }; 62da85a3afSAndrew-sh Cheng opp-702000000 { 63da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <702000000>; 64da85a3afSAndrew-sh Cheng opp-microvolt = <908000>; 65da85a3afSAndrew-sh Cheng }; 66da85a3afSAndrew-sh Cheng opp-1001000000 { 67da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1001000000>; 68da85a3afSAndrew-sh Cheng opp-microvolt = <983000>; 69da85a3afSAndrew-sh Cheng }; 70da85a3afSAndrew-sh Cheng opp-1105000000 { 71da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1105000000>; 72da85a3afSAndrew-sh Cheng opp-microvolt = <1009000>; 73da85a3afSAndrew-sh Cheng }; 74da85a3afSAndrew-sh Cheng opp-1209000000 { 75da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1209000000>; 76da85a3afSAndrew-sh Cheng opp-microvolt = <1034000>; 77da85a3afSAndrew-sh Cheng }; 78da85a3afSAndrew-sh Cheng opp-1300000000 { 79da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1300000000>; 80da85a3afSAndrew-sh Cheng opp-microvolt = <1057000>; 81da85a3afSAndrew-sh Cheng }; 82da85a3afSAndrew-sh Cheng opp-1508000000 { 83da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1508000000>; 84da85a3afSAndrew-sh Cheng opp-microvolt = <1109000>; 85da85a3afSAndrew-sh Cheng }; 86da85a3afSAndrew-sh Cheng opp-1703000000 { 87da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1703000000>; 88da85a3afSAndrew-sh Cheng opp-microvolt = <1125000>; 89da85a3afSAndrew-sh Cheng }; 90da85a3afSAndrew-sh Cheng }; 91da85a3afSAndrew-sh Cheng 92da85a3afSAndrew-sh Cheng cluster1_opp: opp_table1 { 93da85a3afSAndrew-sh Cheng compatible = "operating-points-v2"; 94da85a3afSAndrew-sh Cheng opp-shared; 95da85a3afSAndrew-sh Cheng opp-507000000 { 96da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <507000000>; 97da85a3afSAndrew-sh Cheng opp-microvolt = <828000>; 98da85a3afSAndrew-sh Cheng }; 99da85a3afSAndrew-sh Cheng opp-702000000 { 100da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <702000000>; 101da85a3afSAndrew-sh Cheng opp-microvolt = <867000>; 102da85a3afSAndrew-sh Cheng }; 103da85a3afSAndrew-sh Cheng opp-1001000000 { 104da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1001000000>; 105da85a3afSAndrew-sh Cheng opp-microvolt = <927000>; 106da85a3afSAndrew-sh Cheng }; 107da85a3afSAndrew-sh Cheng opp-1209000000 { 108da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1209000000>; 109da85a3afSAndrew-sh Cheng opp-microvolt = <968000>; 110da85a3afSAndrew-sh Cheng }; 111da85a3afSAndrew-sh Cheng opp-1404000000 { 112da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1404000000>; 113da85a3afSAndrew-sh Cheng opp-microvolt = <1007000>; 114da85a3afSAndrew-sh Cheng }; 115da85a3afSAndrew-sh Cheng opp-1612000000 { 116da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1612000000>; 117da85a3afSAndrew-sh Cheng opp-microvolt = <1049000>; 118da85a3afSAndrew-sh Cheng }; 119da85a3afSAndrew-sh Cheng opp-1807000000 { 120da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <1807000000>; 121da85a3afSAndrew-sh Cheng opp-microvolt = <1089000>; 122da85a3afSAndrew-sh Cheng }; 123da85a3afSAndrew-sh Cheng opp-2106000000 { 124da85a3afSAndrew-sh Cheng opp-hz = /bits/ 64 <2106000000>; 125da85a3afSAndrew-sh Cheng opp-microvolt = <1125000>; 126da85a3afSAndrew-sh Cheng }; 127da85a3afSAndrew-sh Cheng }; 128da85a3afSAndrew-sh Cheng 129b3a37248SEddie Huang cpus { 130b3a37248SEddie Huang #address-cells = <1>; 131b3a37248SEddie Huang #size-cells = <0>; 132b3a37248SEddie Huang 133b3a37248SEddie Huang cpu-map { 134b3a37248SEddie Huang cluster0 { 135b3a37248SEddie Huang core0 { 136b3a37248SEddie Huang cpu = <&cpu0>; 137b3a37248SEddie Huang }; 138b3a37248SEddie Huang core1 { 139b3a37248SEddie Huang cpu = <&cpu1>; 140b3a37248SEddie Huang }; 141b3a37248SEddie Huang }; 142b3a37248SEddie Huang 143b3a37248SEddie Huang cluster1 { 144b3a37248SEddie Huang core0 { 145b3a37248SEddie Huang cpu = <&cpu2>; 146b3a37248SEddie Huang }; 147b3a37248SEddie Huang core1 { 148b3a37248SEddie Huang cpu = <&cpu3>; 149b3a37248SEddie Huang }; 150b3a37248SEddie Huang }; 151b3a37248SEddie Huang }; 152b3a37248SEddie Huang 153b3a37248SEddie Huang cpu0: cpu@0 { 154b3a37248SEddie Huang device_type = "cpu"; 155b3a37248SEddie Huang compatible = "arm,cortex-a53"; 156b3a37248SEddie Huang reg = <0x000>; 157ad4df7a5SHoward Chen enable-method = "psci"; 158ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 159acbf76eeSArnd Bergmann #cooling-cells = <2>; 16019f62c76Smichael.kao dynamic-power-coefficient = <263>; 161da85a3afSAndrew-sh Cheng clocks = <&infracfg CLK_INFRA_CA53SEL>, 162da85a3afSAndrew-sh Cheng <&apmixedsys CLK_APMIXED_MAINPLL>; 163da85a3afSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 164da85a3afSAndrew-sh Cheng operating-points-v2 = <&cluster0_opp>; 165b3a37248SEddie Huang }; 166b3a37248SEddie Huang 167b3a37248SEddie Huang cpu1: cpu@1 { 168b3a37248SEddie Huang device_type = "cpu"; 169b3a37248SEddie Huang compatible = "arm,cortex-a53"; 170b3a37248SEddie Huang reg = <0x001>; 171b3a37248SEddie Huang enable-method = "psci"; 172ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 173a06e5c05SViresh Kumar #cooling-cells = <2>; 17419f62c76Smichael.kao dynamic-power-coefficient = <263>; 175da85a3afSAndrew-sh Cheng clocks = <&infracfg CLK_INFRA_CA53SEL>, 176da85a3afSAndrew-sh Cheng <&apmixedsys CLK_APMIXED_MAINPLL>; 177da85a3afSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 178da85a3afSAndrew-sh Cheng operating-points-v2 = <&cluster0_opp>; 179b3a37248SEddie Huang }; 180b3a37248SEddie Huang 181b3a37248SEddie Huang cpu2: cpu@100 { 182b3a37248SEddie Huang device_type = "cpu"; 1835c6e116dSSeiya Wang compatible = "arm,cortex-a72"; 184b3a37248SEddie Huang reg = <0x100>; 185b3a37248SEddie Huang enable-method = "psci"; 186ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 187acbf76eeSArnd Bergmann #cooling-cells = <2>; 18819f62c76Smichael.kao dynamic-power-coefficient = <530>; 1895c6e116dSSeiya Wang clocks = <&infracfg CLK_INFRA_CA72SEL>, 190da85a3afSAndrew-sh Cheng <&apmixedsys CLK_APMIXED_MAINPLL>; 191da85a3afSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 192da85a3afSAndrew-sh Cheng operating-points-v2 = <&cluster1_opp>; 193b3a37248SEddie Huang }; 194b3a37248SEddie Huang 195b3a37248SEddie Huang cpu3: cpu@101 { 196b3a37248SEddie Huang device_type = "cpu"; 1975c6e116dSSeiya Wang compatible = "arm,cortex-a72"; 198b3a37248SEddie Huang reg = <0x101>; 199b3a37248SEddie Huang enable-method = "psci"; 200ad4df7a5SHoward Chen cpu-idle-states = <&CPU_SLEEP_0>; 201a06e5c05SViresh Kumar #cooling-cells = <2>; 20219f62c76Smichael.kao dynamic-power-coefficient = <530>; 2035c6e116dSSeiya Wang clocks = <&infracfg CLK_INFRA_CA72SEL>, 204da85a3afSAndrew-sh Cheng <&apmixedsys CLK_APMIXED_MAINPLL>; 205da85a3afSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 206da85a3afSAndrew-sh Cheng operating-points-v2 = <&cluster1_opp>; 207ad4df7a5SHoward Chen }; 208ad4df7a5SHoward Chen 209ad4df7a5SHoward Chen idle-states { 210a13f18f5SLorenzo Pieralisi entry-method = "psci"; 211ad4df7a5SHoward Chen 212ad4df7a5SHoward Chen CPU_SLEEP_0: cpu-sleep-0 { 213ad4df7a5SHoward Chen compatible = "arm,idle-state"; 214ad4df7a5SHoward Chen local-timer-stop; 215ad4df7a5SHoward Chen entry-latency-us = <639>; 216ad4df7a5SHoward Chen exit-latency-us = <680>; 217ad4df7a5SHoward Chen min-residency-us = <1088>; 218ad4df7a5SHoward Chen arm,psci-suspend-param = <0x0010000>; 219ad4df7a5SHoward Chen }; 220b3a37248SEddie Huang }; 221b3a37248SEddie Huang }; 222b3a37248SEddie Huang 223a4599f6eSSeiya Wang pmu_a53 { 224a4599f6eSSeiya Wang compatible = "arm,cortex-a53-pmu"; 225a4599f6eSSeiya Wang interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, 226a4599f6eSSeiya Wang <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>; 227a4599f6eSSeiya Wang interrupt-affinity = <&cpu0>, <&cpu1>; 228a4599f6eSSeiya Wang }; 229a4599f6eSSeiya Wang 230a4599f6eSSeiya Wang pmu_a72 { 231a4599f6eSSeiya Wang compatible = "arm,cortex-a72-pmu"; 232a4599f6eSSeiya Wang interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>, 233a4599f6eSSeiya Wang <GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>; 234a4599f6eSSeiya Wang interrupt-affinity = <&cpu2>, <&cpu3>; 235a4599f6eSSeiya Wang }; 236a4599f6eSSeiya Wang 237b3a37248SEddie Huang psci { 23805bdabe7SFan Chen compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 239b3a37248SEddie Huang method = "smc"; 240b3a37248SEddie Huang cpu_suspend = <0x84000001>; 241b3a37248SEddie Huang cpu_off = <0x84000002>; 242b3a37248SEddie Huang cpu_on = <0x84000003>; 243b3a37248SEddie Huang }; 244b3a37248SEddie Huang 245f2ce7014SSascha Hauer clk26m: oscillator@0 { 246f2ce7014SSascha Hauer compatible = "fixed-clock"; 247f2ce7014SSascha Hauer #clock-cells = <0>; 248f2ce7014SSascha Hauer clock-frequency = <26000000>; 249f2ce7014SSascha Hauer clock-output-names = "clk26m"; 250f2ce7014SSascha Hauer }; 251f2ce7014SSascha Hauer 252f2ce7014SSascha Hauer clk32k: oscillator@1 { 253f2ce7014SSascha Hauer compatible = "fixed-clock"; 254f2ce7014SSascha Hauer #clock-cells = <0>; 255f2ce7014SSascha Hauer clock-frequency = <32000>; 256f2ce7014SSascha Hauer clock-output-names = "clk32k"; 257f2ce7014SSascha Hauer }; 258f2ce7014SSascha Hauer 25967e56c56SJames Liao cpum_ck: oscillator@2 { 26067e56c56SJames Liao compatible = "fixed-clock"; 26167e56c56SJames Liao #clock-cells = <0>; 26267e56c56SJames Liao clock-frequency = <0>; 26367e56c56SJames Liao clock-output-names = "cpum_ck"; 26467e56c56SJames Liao }; 26567e56c56SJames Liao 266962f5143Sdawei.chien@mediatek.com thermal-zones { 267962f5143Sdawei.chien@mediatek.com cpu_thermal: cpu_thermal { 268962f5143Sdawei.chien@mediatek.com polling-delay-passive = <1000>; /* milliseconds */ 269962f5143Sdawei.chien@mediatek.com polling-delay = <1000>; /* milliseconds */ 270962f5143Sdawei.chien@mediatek.com 271962f5143Sdawei.chien@mediatek.com thermal-sensors = <&thermal>; 272962f5143Sdawei.chien@mediatek.com sustainable-power = <1500>; /* milliwatts */ 273962f5143Sdawei.chien@mediatek.com 274962f5143Sdawei.chien@mediatek.com trips { 275962f5143Sdawei.chien@mediatek.com threshold: trip-point@0 { 276962f5143Sdawei.chien@mediatek.com temperature = <68000>; 277962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 278962f5143Sdawei.chien@mediatek.com type = "passive"; 279962f5143Sdawei.chien@mediatek.com }; 280962f5143Sdawei.chien@mediatek.com 281962f5143Sdawei.chien@mediatek.com target: trip-point@1 { 282962f5143Sdawei.chien@mediatek.com temperature = <85000>; 283962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 284962f5143Sdawei.chien@mediatek.com type = "passive"; 285962f5143Sdawei.chien@mediatek.com }; 286962f5143Sdawei.chien@mediatek.com 287962f5143Sdawei.chien@mediatek.com cpu_crit: cpu_crit@0 { 288962f5143Sdawei.chien@mediatek.com temperature = <115000>; 289962f5143Sdawei.chien@mediatek.com hysteresis = <2000>; 290962f5143Sdawei.chien@mediatek.com type = "critical"; 291962f5143Sdawei.chien@mediatek.com }; 292962f5143Sdawei.chien@mediatek.com }; 293962f5143Sdawei.chien@mediatek.com 294962f5143Sdawei.chien@mediatek.com cooling-maps { 295962f5143Sdawei.chien@mediatek.com map@0 { 296962f5143Sdawei.chien@mediatek.com trip = <&target>; 297398ed292SViresh Kumar cooling-device = <&cpu0 0 0>, 298398ed292SViresh Kumar <&cpu1 0 0>; 2997fcef92dSDaniel Kurtz contribution = <3072>; 300962f5143Sdawei.chien@mediatek.com }; 301962f5143Sdawei.chien@mediatek.com map@1 { 302962f5143Sdawei.chien@mediatek.com trip = <&target>; 303398ed292SViresh Kumar cooling-device = <&cpu2 0 0>, 304398ed292SViresh Kumar <&cpu3 0 0>; 3057fcef92dSDaniel Kurtz contribution = <1024>; 306962f5143Sdawei.chien@mediatek.com }; 307962f5143Sdawei.chien@mediatek.com }; 308962f5143Sdawei.chien@mediatek.com }; 309962f5143Sdawei.chien@mediatek.com }; 310962f5143Sdawei.chien@mediatek.com 311404b2819SAndrew-CT Chen reserved-memory { 312404b2819SAndrew-CT Chen #address-cells = <2>; 313404b2819SAndrew-CT Chen #size-cells = <2>; 314404b2819SAndrew-CT Chen ranges; 315404b2819SAndrew-CT Chen vpu_dma_reserved: vpu_dma_mem_region { 316404b2819SAndrew-CT Chen compatible = "shared-dma-pool"; 317404b2819SAndrew-CT Chen reg = <0 0xb7000000 0 0x500000>; 318404b2819SAndrew-CT Chen alignment = <0x1000>; 319404b2819SAndrew-CT Chen no-map; 320404b2819SAndrew-CT Chen }; 321404b2819SAndrew-CT Chen }; 322404b2819SAndrew-CT Chen 323b3a37248SEddie Huang timer { 324b3a37248SEddie Huang compatible = "arm,armv8-timer"; 325b3a37248SEddie Huang interrupt-parent = <&gic>; 326b3a37248SEddie Huang interrupts = <GIC_PPI 13 327b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 328b3a37248SEddie Huang <GIC_PPI 14 329b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 330b3a37248SEddie Huang <GIC_PPI 11 331b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 332b3a37248SEddie Huang <GIC_PPI 10 333b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 334b3a37248SEddie Huang }; 335b3a37248SEddie Huang 336b3a37248SEddie Huang soc { 337b3a37248SEddie Huang #address-cells = <2>; 338b3a37248SEddie Huang #size-cells = <2>; 339b3a37248SEddie Huang compatible = "simple-bus"; 340b3a37248SEddie Huang ranges; 341b3a37248SEddie Huang 342f2ce7014SSascha Hauer topckgen: clock-controller@10000000 { 343f2ce7014SSascha Hauer compatible = "mediatek,mt8173-topckgen"; 344f2ce7014SSascha Hauer reg = <0 0x10000000 0 0x1000>; 345f2ce7014SSascha Hauer #clock-cells = <1>; 346f2ce7014SSascha Hauer }; 347f2ce7014SSascha Hauer 348f2ce7014SSascha Hauer infracfg: power-controller@10001000 { 349f2ce7014SSascha Hauer compatible = "mediatek,mt8173-infracfg", "syscon"; 350f2ce7014SSascha Hauer reg = <0 0x10001000 0 0x1000>; 351f2ce7014SSascha Hauer #clock-cells = <1>; 352f2ce7014SSascha Hauer #reset-cells = <1>; 353f2ce7014SSascha Hauer }; 354f2ce7014SSascha Hauer 355f2ce7014SSascha Hauer pericfg: power-controller@10003000 { 356f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pericfg", "syscon"; 357f2ce7014SSascha Hauer reg = <0 0x10003000 0 0x1000>; 358f2ce7014SSascha Hauer #clock-cells = <1>; 359f2ce7014SSascha Hauer #reset-cells = <1>; 360f2ce7014SSascha Hauer }; 361f2ce7014SSascha Hauer 362f2ce7014SSascha Hauer syscfg_pctl_a: syscfg_pctl_a@10005000 { 363f2ce7014SSascha Hauer compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 364f2ce7014SSascha Hauer reg = <0 0x10005000 0 0x1000>; 365f2ce7014SSascha Hauer }; 366f2ce7014SSascha Hauer 3679977a8c3SMathieu Malaterre pio: pinctrl@10005000 { 368359f9365SHongzhou Yang compatible = "mediatek,mt8173-pinctrl"; 3696769b93cSYingjoe Chen reg = <0 0x1000b000 0 0x1000>; 370359f9365SHongzhou Yang mediatek,pctl-regmap = <&syscfg_pctl_a>; 371359f9365SHongzhou Yang pins-are-numbered; 372359f9365SHongzhou Yang gpio-controller; 373359f9365SHongzhou Yang #gpio-cells = <2>; 374359f9365SHongzhou Yang interrupt-controller; 375359f9365SHongzhou Yang #interrupt-cells = <2>; 376359f9365SHongzhou Yang interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 377359f9365SHongzhou Yang <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 378359f9365SHongzhou Yang <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 379091cf598SEddie Huang 380a10b57f4SCK Hu hdmi_pin: xxx { 381a10b57f4SCK Hu 382a10b57f4SCK Hu /*hdmi htplg pin*/ 383a10b57f4SCK Hu pins1 { 384a10b57f4SCK Hu pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>; 385a10b57f4SCK Hu input-enable; 386a10b57f4SCK Hu bias-pull-down; 387a10b57f4SCK Hu }; 388a10b57f4SCK Hu }; 389a10b57f4SCK Hu 390091cf598SEddie Huang i2c0_pins_a: i2c0 { 391091cf598SEddie Huang pins1 { 392091cf598SEddie Huang pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 393091cf598SEddie Huang <MT8173_PIN_46_SCL0__FUNC_SCL0>; 394091cf598SEddie Huang bias-disable; 395091cf598SEddie Huang }; 396359f9365SHongzhou Yang }; 397359f9365SHongzhou Yang 398091cf598SEddie Huang i2c1_pins_a: i2c1 { 399091cf598SEddie Huang pins1 { 400091cf598SEddie Huang pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 401091cf598SEddie Huang <MT8173_PIN_126_SCL1__FUNC_SCL1>; 402091cf598SEddie Huang bias-disable; 403091cf598SEddie Huang }; 404091cf598SEddie Huang }; 405091cf598SEddie Huang 406091cf598SEddie Huang i2c2_pins_a: i2c2 { 407091cf598SEddie Huang pins1 { 408091cf598SEddie Huang pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 409091cf598SEddie Huang <MT8173_PIN_44_SCL2__FUNC_SCL2>; 410091cf598SEddie Huang bias-disable; 411091cf598SEddie Huang }; 412091cf598SEddie Huang }; 413091cf598SEddie Huang 414091cf598SEddie Huang i2c3_pins_a: i2c3 { 415091cf598SEddie Huang pins1 { 416091cf598SEddie Huang pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 417091cf598SEddie Huang <MT8173_PIN_107_SCL3__FUNC_SCL3>; 418091cf598SEddie Huang bias-disable; 419091cf598SEddie Huang }; 420091cf598SEddie Huang }; 421091cf598SEddie Huang 422091cf598SEddie Huang i2c4_pins_a: i2c4 { 423091cf598SEddie Huang pins1 { 424091cf598SEddie Huang pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 425091cf598SEddie Huang <MT8173_PIN_134_SCL4__FUNC_SCL4>; 426091cf598SEddie Huang bias-disable; 427091cf598SEddie Huang }; 428091cf598SEddie Huang }; 429091cf598SEddie Huang 430091cf598SEddie Huang i2c6_pins_a: i2c6 { 431091cf598SEddie Huang pins1 { 432091cf598SEddie Huang pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 433091cf598SEddie Huang <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 434091cf598SEddie Huang bias-disable; 435091cf598SEddie Huang }; 436091cf598SEddie Huang }; 4376769b93cSYingjoe Chen }; 4386769b93cSYingjoe Chen 439c010ff53SSascha Hauer scpsys: scpsys@10006000 { 440c010ff53SSascha Hauer compatible = "mediatek,mt8173-scpsys"; 441c010ff53SSascha Hauer #power-domain-cells = <1>; 442c010ff53SSascha Hauer reg = <0 0x10006000 0 0x1000>; 443c010ff53SSascha Hauer clocks = <&clk26m>, 444e34573c9SJames Liao <&topckgen CLK_TOP_MM_SEL>, 445e34573c9SJames Liao <&topckgen CLK_TOP_VENC_SEL>, 446e34573c9SJames Liao <&topckgen CLK_TOP_VENC_LT_SEL>; 447e34573c9SJames Liao clock-names = "mfg", "mm", "venc", "venc_lt"; 448c010ff53SSascha Hauer infracfg = <&infracfg>; 449c010ff53SSascha Hauer }; 450c010ff53SSascha Hauer 45113421b3eSEddie Huang watchdog: watchdog@10007000 { 45213421b3eSEddie Huang compatible = "mediatek,mt8173-wdt", 45313421b3eSEddie Huang "mediatek,mt6589-wdt"; 45413421b3eSEddie Huang reg = <0 0x10007000 0 0x100>; 45513421b3eSEddie Huang }; 45613421b3eSEddie Huang 457b2c76e27SDaniel Kurtz timer: timer@10008000 { 458b2c76e27SDaniel Kurtz compatible = "mediatek,mt8173-timer", 459b2c76e27SDaniel Kurtz "mediatek,mt6577-timer"; 460b2c76e27SDaniel Kurtz reg = <0 0x10008000 0 0x1000>; 461b2c76e27SDaniel Kurtz interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 462b2c76e27SDaniel Kurtz clocks = <&infracfg CLK_INFRA_CLK_13M>, 463b2c76e27SDaniel Kurtz <&topckgen CLK_TOP_RTC_SEL>; 464b2c76e27SDaniel Kurtz }; 465b2c76e27SDaniel Kurtz 4666cf15fc2SSascha Hauer pwrap: pwrap@1000d000 { 4676cf15fc2SSascha Hauer compatible = "mediatek,mt8173-pwrap"; 4686cf15fc2SSascha Hauer reg = <0 0x1000d000 0 0x1000>; 4696cf15fc2SSascha Hauer reg-names = "pwrap"; 4706cf15fc2SSascha Hauer interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 4716cf15fc2SSascha Hauer resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 4726cf15fc2SSascha Hauer reset-names = "pwrap"; 4736cf15fc2SSascha Hauer clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 4746cf15fc2SSascha Hauer clock-names = "spi", "wrap"; 4756cf15fc2SSascha Hauer }; 4766cf15fc2SSascha Hauer 477a10b57f4SCK Hu cec: cec@10013000 { 478a10b57f4SCK Hu compatible = "mediatek,mt8173-cec"; 479a10b57f4SCK Hu reg = <0 0x10013000 0 0xbc>; 480a10b57f4SCK Hu interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; 481a10b57f4SCK Hu clocks = <&infracfg CLK_INFRA_CEC>; 482a10b57f4SCK Hu status = "disabled"; 483a10b57f4SCK Hu }; 484a10b57f4SCK Hu 485404b2819SAndrew-CT Chen vpu: vpu@10020000 { 486404b2819SAndrew-CT Chen compatible = "mediatek,mt8173-vpu"; 487404b2819SAndrew-CT Chen reg = <0 0x10020000 0 0x30000>, 488404b2819SAndrew-CT Chen <0 0x10050000 0 0x100>; 489404b2819SAndrew-CT Chen reg-names = "tcm", "cfg_reg"; 490404b2819SAndrew-CT Chen interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 491404b2819SAndrew-CT Chen clocks = <&topckgen CLK_TOP_SCP_SEL>; 492404b2819SAndrew-CT Chen clock-names = "main"; 493404b2819SAndrew-CT Chen memory-region = <&vpu_dma_reserved>; 494404b2819SAndrew-CT Chen }; 495404b2819SAndrew-CT Chen 496b3a37248SEddie Huang sysirq: intpol-controller@10200620 { 497b3a37248SEddie Huang compatible = "mediatek,mt8173-sysirq", 498b3a37248SEddie Huang "mediatek,mt6577-sysirq"; 499b3a37248SEddie Huang interrupt-controller; 500b3a37248SEddie Huang #interrupt-cells = <3>; 501b3a37248SEddie Huang interrupt-parent = <&gic>; 502b3a37248SEddie Huang reg = <0 0x10200620 0 0x20>; 503b3a37248SEddie Huang }; 504b3a37248SEddie Huang 5055ff6b3a6SYong Wu iommu: iommu@10205000 { 5065ff6b3a6SYong Wu compatible = "mediatek,mt8173-m4u"; 5075ff6b3a6SYong Wu reg = <0 0x10205000 0 0x1000>; 5085ff6b3a6SYong Wu interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 5095ff6b3a6SYong Wu clocks = <&infracfg CLK_INFRA_M4U>; 5105ff6b3a6SYong Wu clock-names = "bclk"; 5115ff6b3a6SYong Wu mediatek,larbs = <&larb0 &larb1 &larb2 5125ff6b3a6SYong Wu &larb3 &larb4 &larb5>; 5135ff6b3a6SYong Wu #iommu-cells = <1>; 5145ff6b3a6SYong Wu }; 5155ff6b3a6SYong Wu 51693e9f5eeSandrew-ct.chen@mediatek.com efuse: efuse@10206000 { 51793e9f5eeSandrew-ct.chen@mediatek.com compatible = "mediatek,mt8173-efuse"; 51893e9f5eeSandrew-ct.chen@mediatek.com reg = <0 0x10206000 0 0x1000>; 5196de18454Sdawei.chien@mediatek.com #address-cells = <1>; 5206de18454Sdawei.chien@mediatek.com #size-cells = <1>; 5216de18454Sdawei.chien@mediatek.com thermal_calibration: calib@528 { 5226de18454Sdawei.chien@mediatek.com reg = <0x528 0xc>; 5236de18454Sdawei.chien@mediatek.com }; 52493e9f5eeSandrew-ct.chen@mediatek.com }; 52593e9f5eeSandrew-ct.chen@mediatek.com 526f2ce7014SSascha Hauer apmixedsys: clock-controller@10209000 { 527f2ce7014SSascha Hauer compatible = "mediatek,mt8173-apmixedsys"; 528f2ce7014SSascha Hauer reg = <0 0x10209000 0 0x1000>; 529f2ce7014SSascha Hauer #clock-cells = <1>; 530f2ce7014SSascha Hauer }; 531f2ce7014SSascha Hauer 532a10b57f4SCK Hu hdmi_phy: hdmi-phy@10209100 { 533a10b57f4SCK Hu compatible = "mediatek,mt8173-hdmi-phy"; 534a10b57f4SCK Hu reg = <0 0x10209100 0 0x24>; 535a10b57f4SCK Hu clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; 536a10b57f4SCK Hu clock-names = "pll_ref"; 537a10b57f4SCK Hu clock-output-names = "hdmitx_dig_cts"; 538a10b57f4SCK Hu mediatek,ibias = <0xa>; 539a10b57f4SCK Hu mediatek,ibias_up = <0x1c>; 540a10b57f4SCK Hu #clock-cells = <0>; 541a10b57f4SCK Hu #phy-cells = <0>; 542a10b57f4SCK Hu status = "disabled"; 543a10b57f4SCK Hu }; 544a10b57f4SCK Hu 545c2e66b8fSHoulong Wei gce: mailbox@10212000 { 546c2e66b8fSHoulong Wei compatible = "mediatek,mt8173-gce"; 547c2e66b8fSHoulong Wei reg = <0 0x10212000 0 0x1000>; 548c2e66b8fSHoulong Wei interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 549c2e66b8fSHoulong Wei clocks = <&infracfg CLK_INFRA_GCE>; 550c2e66b8fSHoulong Wei clock-names = "gce"; 551c2e66b8fSHoulong Wei #mbox-cells = <3>; 552c2e66b8fSHoulong Wei }; 553c2e66b8fSHoulong Wei 55481ad4dbaSCK Hu mipi_tx0: mipi-dphy@10215000 { 55581ad4dbaSCK Hu compatible = "mediatek,mt8173-mipi-tx"; 55681ad4dbaSCK Hu reg = <0 0x10215000 0 0x1000>; 55781ad4dbaSCK Hu clocks = <&clk26m>; 55881ad4dbaSCK Hu clock-output-names = "mipi_tx0_pll"; 55981ad4dbaSCK Hu #clock-cells = <0>; 56081ad4dbaSCK Hu #phy-cells = <0>; 56181ad4dbaSCK Hu status = "disabled"; 56281ad4dbaSCK Hu }; 56381ad4dbaSCK Hu 56481ad4dbaSCK Hu mipi_tx1: mipi-dphy@10216000 { 56581ad4dbaSCK Hu compatible = "mediatek,mt8173-mipi-tx"; 56681ad4dbaSCK Hu reg = <0 0x10216000 0 0x1000>; 56781ad4dbaSCK Hu clocks = <&clk26m>; 56881ad4dbaSCK Hu clock-output-names = "mipi_tx1_pll"; 56981ad4dbaSCK Hu #clock-cells = <0>; 57081ad4dbaSCK Hu #phy-cells = <0>; 57181ad4dbaSCK Hu status = "disabled"; 57281ad4dbaSCK Hu }; 57381ad4dbaSCK Hu 574b3a37248SEddie Huang gic: interrupt-controller@10220000 { 575b3a37248SEddie Huang compatible = "arm,gic-400"; 576b3a37248SEddie Huang #interrupt-cells = <3>; 577b3a37248SEddie Huang interrupt-parent = <&gic>; 578b3a37248SEddie Huang interrupt-controller; 579b3a37248SEddie Huang reg = <0 0x10221000 0 0x1000>, 580b3a37248SEddie Huang <0 0x10222000 0 0x2000>, 581b3a37248SEddie Huang <0 0x10224000 0 0x2000>, 582b3a37248SEddie Huang <0 0x10226000 0 0x2000>; 583b3a37248SEddie Huang interrupts = <GIC_PPI 9 584b3a37248SEddie Huang (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 585b3a37248SEddie Huang }; 586b3a37248SEddie Huang 587748c7d4dSSascha Hauer auxadc: auxadc@11001000 { 588748c7d4dSSascha Hauer compatible = "mediatek,mt8173-auxadc"; 589748c7d4dSSascha Hauer reg = <0 0x11001000 0 0x1000>; 590a3207d64SMatthias Brugger clocks = <&pericfg CLK_PERI_AUXADC>; 591a3207d64SMatthias Brugger clock-names = "main"; 592a3207d64SMatthias Brugger #io-channel-cells = <1>; 593748c7d4dSSascha Hauer }; 594748c7d4dSSascha Hauer 595b3a37248SEddie Huang uart0: serial@11002000 { 596b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 597b3a37248SEddie Huang "mediatek,mt6577-uart"; 598b3a37248SEddie Huang reg = <0 0x11002000 0 0x400>; 599b3a37248SEddie Huang interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 6000e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 6010e84faa1SSascha Hauer clock-names = "baud", "bus"; 602b3a37248SEddie Huang status = "disabled"; 603b3a37248SEddie Huang }; 604b3a37248SEddie Huang 605b3a37248SEddie Huang uart1: serial@11003000 { 606b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 607b3a37248SEddie Huang "mediatek,mt6577-uart"; 608b3a37248SEddie Huang reg = <0 0x11003000 0 0x400>; 609b3a37248SEddie Huang interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 6100e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 6110e84faa1SSascha Hauer clock-names = "baud", "bus"; 612b3a37248SEddie Huang status = "disabled"; 613b3a37248SEddie Huang }; 614b3a37248SEddie Huang 615b3a37248SEddie Huang uart2: serial@11004000 { 616b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 617b3a37248SEddie Huang "mediatek,mt6577-uart"; 618b3a37248SEddie Huang reg = <0 0x11004000 0 0x400>; 619b3a37248SEddie Huang interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 6200e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 6210e84faa1SSascha Hauer clock-names = "baud", "bus"; 622b3a37248SEddie Huang status = "disabled"; 623b3a37248SEddie Huang }; 624b3a37248SEddie Huang 625b3a37248SEddie Huang uart3: serial@11005000 { 626b3a37248SEddie Huang compatible = "mediatek,mt8173-uart", 627b3a37248SEddie Huang "mediatek,mt6577-uart"; 628b3a37248SEddie Huang reg = <0 0x11005000 0 0x400>; 629b3a37248SEddie Huang interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 6300e84faa1SSascha Hauer clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 6310e84faa1SSascha Hauer clock-names = "baud", "bus"; 632b3a37248SEddie Huang status = "disabled"; 633b3a37248SEddie Huang }; 634091cf598SEddie Huang 635091cf598SEddie Huang i2c0: i2c@11007000 { 636091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 637091cf598SEddie Huang reg = <0 0x11007000 0 0x70>, 638091cf598SEddie Huang <0 0x11000100 0 0x80>; 639091cf598SEddie Huang interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 640091cf598SEddie Huang clock-div = <16>; 641091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C0>, 642091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 643091cf598SEddie Huang clock-names = "main", "dma"; 644091cf598SEddie Huang pinctrl-names = "default"; 645091cf598SEddie Huang pinctrl-0 = <&i2c0_pins_a>; 646091cf598SEddie Huang #address-cells = <1>; 647091cf598SEddie Huang #size-cells = <0>; 648091cf598SEddie Huang status = "disabled"; 649091cf598SEddie Huang }; 650091cf598SEddie Huang 651091cf598SEddie Huang i2c1: i2c@11008000 { 652091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 653091cf598SEddie Huang reg = <0 0x11008000 0 0x70>, 654091cf598SEddie Huang <0 0x11000180 0 0x80>; 655091cf598SEddie Huang interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 656091cf598SEddie Huang clock-div = <16>; 657091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C1>, 658091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 659091cf598SEddie Huang clock-names = "main", "dma"; 660091cf598SEddie Huang pinctrl-names = "default"; 661091cf598SEddie Huang pinctrl-0 = <&i2c1_pins_a>; 662091cf598SEddie Huang #address-cells = <1>; 663091cf598SEddie Huang #size-cells = <0>; 664091cf598SEddie Huang status = "disabled"; 665091cf598SEddie Huang }; 666091cf598SEddie Huang 667091cf598SEddie Huang i2c2: i2c@11009000 { 668091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 669091cf598SEddie Huang reg = <0 0x11009000 0 0x70>, 670091cf598SEddie Huang <0 0x11000200 0 0x80>; 671091cf598SEddie Huang interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 672091cf598SEddie Huang clock-div = <16>; 673091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C2>, 674091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 675091cf598SEddie Huang clock-names = "main", "dma"; 676091cf598SEddie Huang pinctrl-names = "default"; 677091cf598SEddie Huang pinctrl-0 = <&i2c2_pins_a>; 678091cf598SEddie Huang #address-cells = <1>; 679091cf598SEddie Huang #size-cells = <0>; 680091cf598SEddie Huang status = "disabled"; 681091cf598SEddie Huang }; 682091cf598SEddie Huang 683b0c936f5SLeilk Liu spi: spi@1100a000 { 684b0c936f5SLeilk Liu compatible = "mediatek,mt8173-spi"; 685b0c936f5SLeilk Liu #address-cells = <1>; 686b0c936f5SLeilk Liu #size-cells = <0>; 687b0c936f5SLeilk Liu reg = <0 0x1100a000 0 0x1000>; 688b0c936f5SLeilk Liu interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 689b0c936f5SLeilk Liu clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 690b0c936f5SLeilk Liu <&topckgen CLK_TOP_SPI_SEL>, 691b0c936f5SLeilk Liu <&pericfg CLK_PERI_SPI0>; 692b0c936f5SLeilk Liu clock-names = "parent-clk", "sel-clk", "spi-clk"; 693b0c936f5SLeilk Liu status = "disabled"; 694b0c936f5SLeilk Liu }; 695b0c936f5SLeilk Liu 696748c7d4dSSascha Hauer thermal: thermal@1100b000 { 697748c7d4dSSascha Hauer #thermal-sensor-cells = <0>; 698748c7d4dSSascha Hauer compatible = "mediatek,mt8173-thermal"; 699748c7d4dSSascha Hauer reg = <0 0x1100b000 0 0x1000>; 700748c7d4dSSascha Hauer interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 701748c7d4dSSascha Hauer clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 702748c7d4dSSascha Hauer clock-names = "therm", "auxadc"; 703748c7d4dSSascha Hauer resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 704748c7d4dSSascha Hauer mediatek,auxadc = <&auxadc>; 705748c7d4dSSascha Hauer mediatek,apmixedsys = <&apmixedsys>; 7066de18454Sdawei.chien@mediatek.com nvmem-cells = <&thermal_calibration>; 7076de18454Sdawei.chien@mediatek.com nvmem-cell-names = "calibration-data"; 708748c7d4dSSascha Hauer }; 709748c7d4dSSascha Hauer 71086cb8a88SBayi Cheng nor_flash: spi@1100d000 { 71186cb8a88SBayi Cheng compatible = "mediatek,mt8173-nor"; 71286cb8a88SBayi Cheng reg = <0 0x1100d000 0 0xe0>; 71386cb8a88SBayi Cheng clocks = <&pericfg CLK_PERI_SPI>, 71486cb8a88SBayi Cheng <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 71586cb8a88SBayi Cheng clock-names = "spi", "sf"; 71686cb8a88SBayi Cheng #address-cells = <1>; 71786cb8a88SBayi Cheng #size-cells = <0>; 71886cb8a88SBayi Cheng status = "disabled"; 71986cb8a88SBayi Cheng }; 72086cb8a88SBayi Cheng 7211ee35c05SYingjoe Chen i2c3: i2c@11010000 { 722091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 723091cf598SEddie Huang reg = <0 0x11010000 0 0x70>, 724091cf598SEddie Huang <0 0x11000280 0 0x80>; 725091cf598SEddie Huang interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 726091cf598SEddie Huang clock-div = <16>; 727091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C3>, 728091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 729091cf598SEddie Huang clock-names = "main", "dma"; 730091cf598SEddie Huang pinctrl-names = "default"; 731091cf598SEddie Huang pinctrl-0 = <&i2c3_pins_a>; 732091cf598SEddie Huang #address-cells = <1>; 733091cf598SEddie Huang #size-cells = <0>; 734091cf598SEddie Huang status = "disabled"; 735091cf598SEddie Huang }; 736091cf598SEddie Huang 7371ee35c05SYingjoe Chen i2c4: i2c@11011000 { 738091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 739091cf598SEddie Huang reg = <0 0x11011000 0 0x70>, 740091cf598SEddie Huang <0 0x11000300 0 0x80>; 741091cf598SEddie Huang interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 742091cf598SEddie Huang clock-div = <16>; 743091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C4>, 744091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 745091cf598SEddie Huang clock-names = "main", "dma"; 746091cf598SEddie Huang pinctrl-names = "default"; 747091cf598SEddie Huang pinctrl-0 = <&i2c4_pins_a>; 748091cf598SEddie Huang #address-cells = <1>; 749091cf598SEddie Huang #size-cells = <0>; 750091cf598SEddie Huang status = "disabled"; 751091cf598SEddie Huang }; 752091cf598SEddie Huang 753a10b57f4SCK Hu hdmiddc0: i2c@11012000 { 754a10b57f4SCK Hu compatible = "mediatek,mt8173-hdmi-ddc"; 755a10b57f4SCK Hu interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 756a10b57f4SCK Hu reg = <0 0x11012000 0 0x1C>; 757a10b57f4SCK Hu clocks = <&pericfg CLK_PERI_I2C5>; 758a10b57f4SCK Hu clock-names = "ddc-i2c"; 759a10b57f4SCK Hu }; 760a10b57f4SCK Hu 7611ee35c05SYingjoe Chen i2c6: i2c@11013000 { 762091cf598SEddie Huang compatible = "mediatek,mt8173-i2c"; 763091cf598SEddie Huang reg = <0 0x11013000 0 0x70>, 764091cf598SEddie Huang <0 0x11000080 0 0x80>; 765091cf598SEddie Huang interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 766091cf598SEddie Huang clock-div = <16>; 767091cf598SEddie Huang clocks = <&pericfg CLK_PERI_I2C6>, 768091cf598SEddie Huang <&pericfg CLK_PERI_AP_DMA>; 769091cf598SEddie Huang clock-names = "main", "dma"; 770091cf598SEddie Huang pinctrl-names = "default"; 771091cf598SEddie Huang pinctrl-0 = <&i2c6_pins_a>; 772091cf598SEddie Huang #address-cells = <1>; 773091cf598SEddie Huang #size-cells = <0>; 774091cf598SEddie Huang status = "disabled"; 775091cf598SEddie Huang }; 776c02e0e86SKoro Chen 777c02e0e86SKoro Chen afe: audio-controller@11220000 { 778c02e0e86SKoro Chen compatible = "mediatek,mt8173-afe-pcm"; 779c02e0e86SKoro Chen reg = <0 0x11220000 0 0x1000>; 780c02e0e86SKoro Chen interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 781c02e0e86SKoro Chen power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; 782c02e0e86SKoro Chen clocks = <&infracfg CLK_INFRA_AUDIO>, 783c02e0e86SKoro Chen <&topckgen CLK_TOP_AUDIO_SEL>, 784c02e0e86SKoro Chen <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 785c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL1_DIV0>, 786c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL2_DIV0>, 787c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S0_M_SEL>, 788c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S1_M_SEL>, 789c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S2_M_SEL>, 790c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S3_M_SEL>, 791c02e0e86SKoro Chen <&topckgen CLK_TOP_I2S3_B_SEL>; 792c02e0e86SKoro Chen clock-names = "infra_sys_audio_clk", 793c02e0e86SKoro Chen "top_pdn_audio", 794c02e0e86SKoro Chen "top_pdn_aud_intbus", 795c02e0e86SKoro Chen "bck0", 796c02e0e86SKoro Chen "bck1", 797c02e0e86SKoro Chen "i2s0_m", 798c02e0e86SKoro Chen "i2s1_m", 799c02e0e86SKoro Chen "i2s2_m", 800c02e0e86SKoro Chen "i2s3_m", 801c02e0e86SKoro Chen "i2s3_b"; 802c02e0e86SKoro Chen assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 803c02e0e86SKoro Chen <&topckgen CLK_TOP_AUD_2_SEL>; 804c02e0e86SKoro Chen assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 805c02e0e86SKoro Chen <&topckgen CLK_TOP_APLL2>; 806c02e0e86SKoro Chen }; 8079719fa5aSEddie Huang 8089719fa5aSEddie Huang mmc0: mmc@11230000 { 809689362b3SChaotian Jing compatible = "mediatek,mt8173-mmc"; 8109719fa5aSEddie Huang reg = <0 0x11230000 0 0x1000>; 8119719fa5aSEddie Huang interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 8129719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_0>, 8139719fa5aSEddie Huang <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 8149719fa5aSEddie Huang clock-names = "source", "hclk"; 8159719fa5aSEddie Huang status = "disabled"; 8169719fa5aSEddie Huang }; 8179719fa5aSEddie Huang 8189719fa5aSEddie Huang mmc1: mmc@11240000 { 819689362b3SChaotian Jing compatible = "mediatek,mt8173-mmc"; 8209719fa5aSEddie Huang reg = <0 0x11240000 0 0x1000>; 8219719fa5aSEddie Huang interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 8229719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_1>, 8239719fa5aSEddie Huang <&topckgen CLK_TOP_AXI_SEL>; 8249719fa5aSEddie Huang clock-names = "source", "hclk"; 8259719fa5aSEddie Huang status = "disabled"; 8269719fa5aSEddie Huang }; 8279719fa5aSEddie Huang 8289719fa5aSEddie Huang mmc2: mmc@11250000 { 829689362b3SChaotian Jing compatible = "mediatek,mt8173-mmc"; 8309719fa5aSEddie Huang reg = <0 0x11250000 0 0x1000>; 8319719fa5aSEddie Huang interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 8329719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_2>, 8339719fa5aSEddie Huang <&topckgen CLK_TOP_AXI_SEL>; 8349719fa5aSEddie Huang clock-names = "source", "hclk"; 8359719fa5aSEddie Huang status = "disabled"; 8369719fa5aSEddie Huang }; 8379719fa5aSEddie Huang 8389719fa5aSEddie Huang mmc3: mmc@11260000 { 839689362b3SChaotian Jing compatible = "mediatek,mt8173-mmc"; 8409719fa5aSEddie Huang reg = <0 0x11260000 0 0x1000>; 8419719fa5aSEddie Huang interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 8429719fa5aSEddie Huang clocks = <&pericfg CLK_PERI_MSDC30_3>, 8439719fa5aSEddie Huang <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 8449719fa5aSEddie Huang clock-names = "source", "hclk"; 8459719fa5aSEddie Huang status = "disabled"; 8469719fa5aSEddie Huang }; 84767e56c56SJames Liao 848c0891284SChunfeng Yun ssusb: usb@11271000 { 849c0891284SChunfeng Yun compatible = "mediatek,mt8173-mtu3"; 850c0891284SChunfeng Yun reg = <0 0x11271000 0 0x3000>, 851bfcce47aSChunfeng Yun <0 0x11280700 0 0x0100>; 852c0891284SChunfeng Yun reg-names = "mac", "ippc"; 853c0891284SChunfeng Yun interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>; 854ebf61c63Schunfeng.yun@mediatek.com phys = <&u2port0 PHY_TYPE_USB2>, 855ebf61c63Schunfeng.yun@mediatek.com <&u3port0 PHY_TYPE_USB3>, 856ebf61c63Schunfeng.yun@mediatek.com <&u2port1 PHY_TYPE_USB2>; 857bfcce47aSChunfeng Yun power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 858cf1fcd45SChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 859cf1fcd45SChunfeng Yun clock-names = "sys_ck", "ref_ck"; 860cf1fcd45SChunfeng Yun mediatek,syscon-wakeup = <&pericfg 0x400 1>; 861c0891284SChunfeng Yun #address-cells = <2>; 862c0891284SChunfeng Yun #size-cells = <2>; 863c0891284SChunfeng Yun ranges; 864c0891284SChunfeng Yun status = "disabled"; 865c0891284SChunfeng Yun 866c0891284SChunfeng Yun usb_host: xhci@11270000 { 867c0891284SChunfeng Yun compatible = "mediatek,mt8173-xhci"; 868c0891284SChunfeng Yun reg = <0 0x11270000 0 0x1000>; 869c0891284SChunfeng Yun reg-names = "mac"; 870c0891284SChunfeng Yun interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 871c0891284SChunfeng Yun power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 872cb6efc7bSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 873cb6efc7bSChunfeng Yun clock-names = "sys_ck", "ref_ck"; 874c0891284SChunfeng Yun status = "disabled"; 875c0891284SChunfeng Yun }; 876bfcce47aSChunfeng Yun }; 877bfcce47aSChunfeng Yun 878bfcce47aSChunfeng Yun u3phy: usb-phy@11290000 { 879bfcce47aSChunfeng Yun compatible = "mediatek,mt8173-u3phy"; 880bfcce47aSChunfeng Yun reg = <0 0x11290000 0 0x800>; 881bfcce47aSChunfeng Yun #address-cells = <2>; 882bfcce47aSChunfeng Yun #size-cells = <2>; 883bfcce47aSChunfeng Yun ranges; 884bfcce47aSChunfeng Yun status = "okay"; 885bfcce47aSChunfeng Yun 886ebf61c63Schunfeng.yun@mediatek.com u2port0: usb-phy@11290800 { 887ebf61c63Schunfeng.yun@mediatek.com reg = <0 0x11290800 0 0x100>; 88810f84a7aSchunfeng.yun@mediatek.com clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 88910f84a7aSchunfeng.yun@mediatek.com clock-names = "ref"; 890bfcce47aSChunfeng Yun #phy-cells = <1>; 891bfcce47aSChunfeng Yun status = "okay"; 892bfcce47aSChunfeng Yun }; 893bfcce47aSChunfeng Yun 894ebf61c63Schunfeng.yun@mediatek.com u3port0: usb-phy@11290900 { 895ebf61c63Schunfeng.yun@mediatek.com reg = <0 0x11290900 0 0x700>; 89610f84a7aSchunfeng.yun@mediatek.com clocks = <&clk26m>; 89710f84a7aSchunfeng.yun@mediatek.com clock-names = "ref"; 898ebf61c63Schunfeng.yun@mediatek.com #phy-cells = <1>; 899ebf61c63Schunfeng.yun@mediatek.com status = "okay"; 900ebf61c63Schunfeng.yun@mediatek.com }; 901ebf61c63Schunfeng.yun@mediatek.com 902ebf61c63Schunfeng.yun@mediatek.com u2port1: usb-phy@11291000 { 903ebf61c63Schunfeng.yun@mediatek.com reg = <0 0x11291000 0 0x100>; 90410f84a7aSchunfeng.yun@mediatek.com clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 90510f84a7aSchunfeng.yun@mediatek.com clock-names = "ref"; 906bfcce47aSChunfeng Yun #phy-cells = <1>; 907bfcce47aSChunfeng Yun status = "okay"; 908bfcce47aSChunfeng Yun }; 909bfcce47aSChunfeng Yun }; 910bfcce47aSChunfeng Yun 91167e56c56SJames Liao mmsys: clock-controller@14000000 { 91267e56c56SJames Liao compatible = "mediatek,mt8173-mmsys", "syscon"; 91367e56c56SJames Liao reg = <0 0x14000000 0 0x1000>; 91481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 915fc6634acSBibby Hsieh assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; 916fc6634acSBibby Hsieh assigned-clock-rates = <400000000>; 91767e56c56SJames Liao #clock-cells = <1>; 91867e56c56SJames Liao }; 91967e56c56SJames Liao 920989b292aSMinghsiu Tsai mdp_rdma0: rdma@14001000 { 9218127881fSDaniel Kurtz compatible = "mediatek,mt8173-mdp-rdma", 9228127881fSDaniel Kurtz "mediatek,mt8173-mdp"; 923989b292aSMinghsiu Tsai reg = <0 0x14001000 0 0x1000>; 924989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RDMA0>, 925989b292aSMinghsiu Tsai <&mmsys CLK_MM_MUTEX_32K>; 926989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 927989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_RDMA0>; 928989b292aSMinghsiu Tsai mediatek,larb = <&larb0>; 9298127881fSDaniel Kurtz mediatek,vpu = <&vpu>; 930989b292aSMinghsiu Tsai }; 931989b292aSMinghsiu Tsai 932989b292aSMinghsiu Tsai mdp_rdma1: rdma@14002000 { 933989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rdma"; 934989b292aSMinghsiu Tsai reg = <0 0x14002000 0 0x1000>; 935989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RDMA1>, 936989b292aSMinghsiu Tsai <&mmsys CLK_MM_MUTEX_32K>; 937989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 938989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_RDMA1>; 939989b292aSMinghsiu Tsai mediatek,larb = <&larb4>; 940989b292aSMinghsiu Tsai }; 941989b292aSMinghsiu Tsai 942989b292aSMinghsiu Tsai mdp_rsz0: rsz@14003000 { 943989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rsz"; 944989b292aSMinghsiu Tsai reg = <0 0x14003000 0 0x1000>; 945989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RSZ0>; 946989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 947989b292aSMinghsiu Tsai }; 948989b292aSMinghsiu Tsai 949989b292aSMinghsiu Tsai mdp_rsz1: rsz@14004000 { 950989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rsz"; 951989b292aSMinghsiu Tsai reg = <0 0x14004000 0 0x1000>; 952989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RSZ1>; 953989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 954989b292aSMinghsiu Tsai }; 955989b292aSMinghsiu Tsai 956989b292aSMinghsiu Tsai mdp_rsz2: rsz@14005000 { 957989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-rsz"; 958989b292aSMinghsiu Tsai reg = <0 0x14005000 0 0x1000>; 959989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_RSZ2>; 960989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 961989b292aSMinghsiu Tsai }; 962989b292aSMinghsiu Tsai 963989b292aSMinghsiu Tsai mdp_wdma0: wdma@14006000 { 964989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-wdma"; 965989b292aSMinghsiu Tsai reg = <0 0x14006000 0 0x1000>; 966989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_WDMA>; 967989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 968989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_WDMA>; 969989b292aSMinghsiu Tsai mediatek,larb = <&larb0>; 970989b292aSMinghsiu Tsai }; 971989b292aSMinghsiu Tsai 972989b292aSMinghsiu Tsai mdp_wrot0: wrot@14007000 { 973989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-wrot"; 974989b292aSMinghsiu Tsai reg = <0 0x14007000 0 0x1000>; 975989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_WROT0>; 976989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 977989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_WROT0>; 978989b292aSMinghsiu Tsai mediatek,larb = <&larb0>; 979989b292aSMinghsiu Tsai }; 980989b292aSMinghsiu Tsai 981989b292aSMinghsiu Tsai mdp_wrot1: wrot@14008000 { 982989b292aSMinghsiu Tsai compatible = "mediatek,mt8173-mdp-wrot"; 983989b292aSMinghsiu Tsai reg = <0 0x14008000 0 0x1000>; 984989b292aSMinghsiu Tsai clocks = <&mmsys CLK_MM_MDP_WROT1>; 985989b292aSMinghsiu Tsai power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 986989b292aSMinghsiu Tsai iommus = <&iommu M4U_PORT_MDP_WROT1>; 987989b292aSMinghsiu Tsai mediatek,larb = <&larb4>; 988989b292aSMinghsiu Tsai }; 989989b292aSMinghsiu Tsai 99081ad4dbaSCK Hu ovl0: ovl@1400c000 { 99181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-ovl"; 99281ad4dbaSCK Hu reg = <0 0x1400c000 0 0x1000>; 99381ad4dbaSCK Hu interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 99481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 99581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_OVL0>; 99681ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_OVL0>; 99781ad4dbaSCK Hu mediatek,larb = <&larb0>; 99881ad4dbaSCK Hu }; 99981ad4dbaSCK Hu 100081ad4dbaSCK Hu ovl1: ovl@1400d000 { 100181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-ovl"; 100281ad4dbaSCK Hu reg = <0 0x1400d000 0 0x1000>; 100381ad4dbaSCK Hu interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; 100481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 100581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_OVL1>; 100681ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_OVL1>; 100781ad4dbaSCK Hu mediatek,larb = <&larb4>; 100881ad4dbaSCK Hu }; 100981ad4dbaSCK Hu 101081ad4dbaSCK Hu rdma0: rdma@1400e000 { 101181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-rdma"; 101281ad4dbaSCK Hu reg = <0 0x1400e000 0 0x1000>; 101381ad4dbaSCK Hu interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 101481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 101581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_RDMA0>; 101681ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_RDMA0>; 101781ad4dbaSCK Hu mediatek,larb = <&larb0>; 101881ad4dbaSCK Hu }; 101981ad4dbaSCK Hu 102081ad4dbaSCK Hu rdma1: rdma@1400f000 { 102181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-rdma"; 102281ad4dbaSCK Hu reg = <0 0x1400f000 0 0x1000>; 102381ad4dbaSCK Hu interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; 102481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 102581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_RDMA1>; 102681ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_RDMA1>; 102781ad4dbaSCK Hu mediatek,larb = <&larb4>; 102881ad4dbaSCK Hu }; 102981ad4dbaSCK Hu 103081ad4dbaSCK Hu rdma2: rdma@14010000 { 103181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-rdma"; 103281ad4dbaSCK Hu reg = <0 0x14010000 0 0x1000>; 103381ad4dbaSCK Hu interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; 103481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 103581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_RDMA2>; 103681ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_RDMA2>; 103781ad4dbaSCK Hu mediatek,larb = <&larb4>; 103881ad4dbaSCK Hu }; 103981ad4dbaSCK Hu 104081ad4dbaSCK Hu wdma0: wdma@14011000 { 104181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-wdma"; 104281ad4dbaSCK Hu reg = <0 0x14011000 0 0x1000>; 104381ad4dbaSCK Hu interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 104481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 104581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_WDMA0>; 104681ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_WDMA0>; 104781ad4dbaSCK Hu mediatek,larb = <&larb0>; 104881ad4dbaSCK Hu }; 104981ad4dbaSCK Hu 105081ad4dbaSCK Hu wdma1: wdma@14012000 { 105181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-wdma"; 105281ad4dbaSCK Hu reg = <0 0x14012000 0 0x1000>; 105381ad4dbaSCK Hu interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; 105481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 105581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_WDMA1>; 105681ad4dbaSCK Hu iommus = <&iommu M4U_PORT_DISP_WDMA1>; 105781ad4dbaSCK Hu mediatek,larb = <&larb4>; 105881ad4dbaSCK Hu }; 105981ad4dbaSCK Hu 106081ad4dbaSCK Hu color0: color@14013000 { 106181ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-color"; 106281ad4dbaSCK Hu reg = <0 0x14013000 0 0x1000>; 106381ad4dbaSCK Hu interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; 106481ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 106581ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_COLOR0>; 106681ad4dbaSCK Hu }; 106781ad4dbaSCK Hu 106881ad4dbaSCK Hu color1: color@14014000 { 106981ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-color"; 107081ad4dbaSCK Hu reg = <0 0x14014000 0 0x1000>; 107181ad4dbaSCK Hu interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 107281ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 107381ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_COLOR1>; 107481ad4dbaSCK Hu }; 107581ad4dbaSCK Hu 107681ad4dbaSCK Hu aal@14015000 { 107781ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-aal"; 107881ad4dbaSCK Hu reg = <0 0x14015000 0 0x1000>; 107981ad4dbaSCK Hu interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 108081ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 108181ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_AAL>; 108281ad4dbaSCK Hu }; 108381ad4dbaSCK Hu 108481ad4dbaSCK Hu gamma@14016000 { 108581ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-gamma"; 108681ad4dbaSCK Hu reg = <0 0x14016000 0 0x1000>; 108781ad4dbaSCK Hu interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 108881ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 108981ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_GAMMA>; 109081ad4dbaSCK Hu }; 109181ad4dbaSCK Hu 109281ad4dbaSCK Hu merge@14017000 { 109381ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-merge"; 109481ad4dbaSCK Hu reg = <0 0x14017000 0 0x1000>; 109581ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 109681ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_MERGE>; 109781ad4dbaSCK Hu }; 109881ad4dbaSCK Hu 109981ad4dbaSCK Hu split0: split@14018000 { 110081ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-split"; 110181ad4dbaSCK Hu reg = <0 0x14018000 0 0x1000>; 110281ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 110381ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_SPLIT0>; 110481ad4dbaSCK Hu }; 110581ad4dbaSCK Hu 110681ad4dbaSCK Hu split1: split@14019000 { 110781ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-split"; 110881ad4dbaSCK Hu reg = <0 0x14019000 0 0x1000>; 110981ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 111081ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_SPLIT1>; 111181ad4dbaSCK Hu }; 111281ad4dbaSCK Hu 111381ad4dbaSCK Hu ufoe@1401a000 { 111481ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-ufoe"; 111581ad4dbaSCK Hu reg = <0 0x1401a000 0 0x1000>; 111681ad4dbaSCK Hu interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 111781ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 111881ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_UFOE>; 111981ad4dbaSCK Hu }; 112081ad4dbaSCK Hu 112181ad4dbaSCK Hu dsi0: dsi@1401b000 { 112281ad4dbaSCK Hu compatible = "mediatek,mt8173-dsi"; 112381ad4dbaSCK Hu reg = <0 0x1401b000 0 0x1000>; 112481ad4dbaSCK Hu interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 112581ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 112681ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DSI0_ENGINE>, 112781ad4dbaSCK Hu <&mmsys CLK_MM_DSI0_DIGITAL>, 112881ad4dbaSCK Hu <&mipi_tx0>; 112981ad4dbaSCK Hu clock-names = "engine", "digital", "hs"; 113081ad4dbaSCK Hu phys = <&mipi_tx0>; 113181ad4dbaSCK Hu phy-names = "dphy"; 113281ad4dbaSCK Hu status = "disabled"; 113381ad4dbaSCK Hu }; 113481ad4dbaSCK Hu 113581ad4dbaSCK Hu dsi1: dsi@1401c000 { 113681ad4dbaSCK Hu compatible = "mediatek,mt8173-dsi"; 113781ad4dbaSCK Hu reg = <0 0x1401c000 0 0x1000>; 113881ad4dbaSCK Hu interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 113981ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 114081ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DSI1_ENGINE>, 114181ad4dbaSCK Hu <&mmsys CLK_MM_DSI1_DIGITAL>, 114281ad4dbaSCK Hu <&mipi_tx1>; 114381ad4dbaSCK Hu clock-names = "engine", "digital", "hs"; 114481ad4dbaSCK Hu phy = <&mipi_tx1>; 114581ad4dbaSCK Hu phy-names = "dphy"; 114681ad4dbaSCK Hu status = "disabled"; 114781ad4dbaSCK Hu }; 114881ad4dbaSCK Hu 114981ad4dbaSCK Hu dpi0: dpi@1401d000 { 115081ad4dbaSCK Hu compatible = "mediatek,mt8173-dpi"; 115181ad4dbaSCK Hu reg = <0 0x1401d000 0 0x1000>; 115281ad4dbaSCK Hu interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 115381ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 115481ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DPI_PIXEL>, 115581ad4dbaSCK Hu <&mmsys CLK_MM_DPI_ENGINE>, 115681ad4dbaSCK Hu <&apmixedsys CLK_APMIXED_TVDPLL>; 115781ad4dbaSCK Hu clock-names = "pixel", "engine", "pll"; 115881ad4dbaSCK Hu status = "disabled"; 1159a10b57f4SCK Hu 1160a10b57f4SCK Hu port { 1161a10b57f4SCK Hu dpi0_out: endpoint { 1162a10b57f4SCK Hu remote-endpoint = <&hdmi0_in>; 1163a10b57f4SCK Hu }; 1164a10b57f4SCK Hu }; 116581ad4dbaSCK Hu }; 116681ad4dbaSCK Hu 116761aee934SYH Huang pwm0: pwm@1401e000 { 116861aee934SYH Huang compatible = "mediatek,mt8173-disp-pwm", 116961aee934SYH Huang "mediatek,mt6595-disp-pwm"; 117061aee934SYH Huang reg = <0 0x1401e000 0 0x1000>; 117161aee934SYH Huang #pwm-cells = <2>; 117261aee934SYH Huang clocks = <&mmsys CLK_MM_DISP_PWM026M>, 117361aee934SYH Huang <&mmsys CLK_MM_DISP_PWM0MM>; 117461aee934SYH Huang clock-names = "main", "mm"; 117561aee934SYH Huang status = "disabled"; 117661aee934SYH Huang }; 117761aee934SYH Huang 117861aee934SYH Huang pwm1: pwm@1401f000 { 117961aee934SYH Huang compatible = "mediatek,mt8173-disp-pwm", 118061aee934SYH Huang "mediatek,mt6595-disp-pwm"; 118161aee934SYH Huang reg = <0 0x1401f000 0 0x1000>; 118261aee934SYH Huang #pwm-cells = <2>; 118361aee934SYH Huang clocks = <&mmsys CLK_MM_DISP_PWM126M>, 118461aee934SYH Huang <&mmsys CLK_MM_DISP_PWM1MM>; 118561aee934SYH Huang clock-names = "main", "mm"; 118661aee934SYH Huang status = "disabled"; 118761aee934SYH Huang }; 118861aee934SYH Huang 118981ad4dbaSCK Hu mutex: mutex@14020000 { 119081ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-mutex"; 119181ad4dbaSCK Hu reg = <0 0x14020000 0 0x1000>; 119281ad4dbaSCK Hu interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 119381ad4dbaSCK Hu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 119481ad4dbaSCK Hu clocks = <&mmsys CLK_MM_MUTEX_32K>; 119581ad4dbaSCK Hu }; 119681ad4dbaSCK Hu 11975ff6b3a6SYong Wu larb0: larb@14021000 { 11985ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 11995ff6b3a6SYong Wu reg = <0 0x14021000 0 0x1000>; 12005ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 12015ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 12025ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_LARB0>, 12035ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_LARB0>; 12045ff6b3a6SYong Wu clock-names = "apb", "smi"; 12055ff6b3a6SYong Wu }; 12065ff6b3a6SYong Wu 12075ff6b3a6SYong Wu smi_common: smi@14022000 { 12085ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-common"; 12095ff6b3a6SYong Wu reg = <0 0x14022000 0 0x1000>; 12105ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 12115ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_COMMON>, 12125ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_COMMON>; 12135ff6b3a6SYong Wu clock-names = "apb", "smi"; 12145ff6b3a6SYong Wu }; 12155ff6b3a6SYong Wu 121681ad4dbaSCK Hu od@14023000 { 121781ad4dbaSCK Hu compatible = "mediatek,mt8173-disp-od"; 121881ad4dbaSCK Hu reg = <0 0x14023000 0 0x1000>; 121981ad4dbaSCK Hu clocks = <&mmsys CLK_MM_DISP_OD>; 122081ad4dbaSCK Hu }; 122181ad4dbaSCK Hu 1222a10b57f4SCK Hu hdmi0: hdmi@14025000 { 1223a10b57f4SCK Hu compatible = "mediatek,mt8173-hdmi"; 1224a10b57f4SCK Hu reg = <0 0x14025000 0 0x400>; 1225a10b57f4SCK Hu interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>; 1226a10b57f4SCK Hu clocks = <&mmsys CLK_MM_HDMI_PIXEL>, 1227a10b57f4SCK Hu <&mmsys CLK_MM_HDMI_PLLCK>, 1228a10b57f4SCK Hu <&mmsys CLK_MM_HDMI_AUDIO>, 1229a10b57f4SCK Hu <&mmsys CLK_MM_HDMI_SPDIF>; 1230a10b57f4SCK Hu clock-names = "pixel", "pll", "bclk", "spdif"; 1231a10b57f4SCK Hu pinctrl-names = "default"; 1232a10b57f4SCK Hu pinctrl-0 = <&hdmi_pin>; 1233a10b57f4SCK Hu phys = <&hdmi_phy>; 1234a10b57f4SCK Hu phy-names = "hdmi"; 1235a10b57f4SCK Hu mediatek,syscon-hdmi = <&mmsys 0x900>; 1236a10b57f4SCK Hu assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; 1237a10b57f4SCK Hu assigned-clock-parents = <&hdmi_phy>; 1238a10b57f4SCK Hu status = "disabled"; 1239a10b57f4SCK Hu 1240a10b57f4SCK Hu ports { 1241a10b57f4SCK Hu #address-cells = <1>; 1242a10b57f4SCK Hu #size-cells = <0>; 1243a10b57f4SCK Hu 1244a10b57f4SCK Hu port@0 { 1245a10b57f4SCK Hu reg = <0>; 1246a10b57f4SCK Hu 1247a10b57f4SCK Hu hdmi0_in: endpoint { 1248a10b57f4SCK Hu remote-endpoint = <&dpi0_out>; 1249a10b57f4SCK Hu }; 1250a10b57f4SCK Hu }; 1251a10b57f4SCK Hu }; 1252a10b57f4SCK Hu }; 1253a10b57f4SCK Hu 12545ff6b3a6SYong Wu larb4: larb@14027000 { 12555ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 12565ff6b3a6SYong Wu reg = <0 0x14027000 0 0x1000>; 12575ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 12585ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 12595ff6b3a6SYong Wu clocks = <&mmsys CLK_MM_SMI_LARB4>, 12605ff6b3a6SYong Wu <&mmsys CLK_MM_SMI_LARB4>; 12615ff6b3a6SYong Wu clock-names = "apb", "smi"; 12625ff6b3a6SYong Wu }; 12635ff6b3a6SYong Wu 126467e56c56SJames Liao imgsys: clock-controller@15000000 { 126567e56c56SJames Liao compatible = "mediatek,mt8173-imgsys", "syscon"; 126667e56c56SJames Liao reg = <0 0x15000000 0 0x1000>; 126767e56c56SJames Liao #clock-cells = <1>; 126867e56c56SJames Liao }; 126967e56c56SJames Liao 12705ff6b3a6SYong Wu larb2: larb@15001000 { 12715ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 12725ff6b3a6SYong Wu reg = <0 0x15001000 0 0x1000>; 12735ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 12745ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>; 12755ff6b3a6SYong Wu clocks = <&imgsys CLK_IMG_LARB2_SMI>, 12765ff6b3a6SYong Wu <&imgsys CLK_IMG_LARB2_SMI>; 12775ff6b3a6SYong Wu clock-names = "apb", "smi"; 12785ff6b3a6SYong Wu }; 12795ff6b3a6SYong Wu 128067e56c56SJames Liao vdecsys: clock-controller@16000000 { 128167e56c56SJames Liao compatible = "mediatek,mt8173-vdecsys", "syscon"; 128267e56c56SJames Liao reg = <0 0x16000000 0 0x1000>; 128367e56c56SJames Liao #clock-cells = <1>; 128467e56c56SJames Liao }; 128567e56c56SJames Liao 128660eaae2bSTiffany Lin vcodec_dec: vcodec@16000000 { 128760eaae2bSTiffany Lin compatible = "mediatek,mt8173-vcodec-dec"; 128860eaae2bSTiffany Lin reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */ 128960eaae2bSTiffany Lin <0 0x16020000 0 0x1000>, /* VDEC_MISC */ 129060eaae2bSTiffany Lin <0 0x16021000 0 0x800>, /* VDEC_LD */ 129160eaae2bSTiffany Lin <0 0x16021800 0 0x800>, /* VDEC_TOP */ 129260eaae2bSTiffany Lin <0 0x16022000 0 0x1000>, /* VDEC_CM */ 129360eaae2bSTiffany Lin <0 0x16023000 0 0x1000>, /* VDEC_AD */ 129460eaae2bSTiffany Lin <0 0x16024000 0 0x1000>, /* VDEC_AV */ 129560eaae2bSTiffany Lin <0 0x16025000 0 0x1000>, /* VDEC_PP */ 129660eaae2bSTiffany Lin <0 0x16026800 0 0x800>, /* VDEC_HWD */ 129760eaae2bSTiffany Lin <0 0x16027000 0 0x800>, /* VDEC_HWQ */ 129860eaae2bSTiffany Lin <0 0x16027800 0 0x800>, /* VDEC_HWB */ 129960eaae2bSTiffany Lin <0 0x16028400 0 0x400>; /* VDEC_HWG */ 130060eaae2bSTiffany Lin interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; 130160eaae2bSTiffany Lin mediatek,larb = <&larb1>; 130260eaae2bSTiffany Lin iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, 130360eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_PP_EXT>, 130460eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, 130560eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, 130660eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, 130760eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, 130860eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, 130960eaae2bSTiffany Lin <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; 131060eaae2bSTiffany Lin mediatek,vpu = <&vpu>; 131160eaae2bSTiffany Lin power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 131260eaae2bSTiffany Lin clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, 131360eaae2bSTiffany Lin <&topckgen CLK_TOP_UNIVPLL_D2>, 131460eaae2bSTiffany Lin <&topckgen CLK_TOP_CCI400_SEL>, 131560eaae2bSTiffany Lin <&topckgen CLK_TOP_VDEC_SEL>, 131660eaae2bSTiffany Lin <&topckgen CLK_TOP_VCODECPLL>, 131760eaae2bSTiffany Lin <&apmixedsys CLK_APMIXED_VENCPLL>, 131860eaae2bSTiffany Lin <&topckgen CLK_TOP_VENC_LT_SEL>, 131960eaae2bSTiffany Lin <&topckgen CLK_TOP_VCODECPLL_370P5>; 132060eaae2bSTiffany Lin clock-names = "vcodecpll", 132160eaae2bSTiffany Lin "univpll_d2", 132260eaae2bSTiffany Lin "clk_cci400_sel", 132360eaae2bSTiffany Lin "vdec_sel", 132460eaae2bSTiffany Lin "vdecpll", 132560eaae2bSTiffany Lin "vencpll", 132660eaae2bSTiffany Lin "venc_lt_sel", 132760eaae2bSTiffany Lin "vdec_bus_clk_src"; 1328fbbad028SYunfei Dong assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>, 1329fbbad028SYunfei Dong <&topckgen CLK_TOP_CCI400_SEL>, 1330fbbad028SYunfei Dong <&topckgen CLK_TOP_VDEC_SEL>, 1331fbbad028SYunfei Dong <&apmixedsys CLK_APMIXED_VCODECPLL>, 1332fbbad028SYunfei Dong <&apmixedsys CLK_APMIXED_VENCPLL>; 1333fbbad028SYunfei Dong assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>, 1334fbbad028SYunfei Dong <&topckgen CLK_TOP_UNIVPLL_D2>, 1335fbbad028SYunfei Dong <&topckgen CLK_TOP_VCODECPLL>; 1336fbbad028SYunfei Dong assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>; 133760eaae2bSTiffany Lin }; 133860eaae2bSTiffany Lin 13395ff6b3a6SYong Wu larb1: larb@16010000 { 13405ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 13415ff6b3a6SYong Wu reg = <0 0x16010000 0 0x1000>; 13425ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 13435ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 13445ff6b3a6SYong Wu clocks = <&vdecsys CLK_VDEC_CKEN>, 13455ff6b3a6SYong Wu <&vdecsys CLK_VDEC_LARB_CKEN>; 13465ff6b3a6SYong Wu clock-names = "apb", "smi"; 13475ff6b3a6SYong Wu }; 13485ff6b3a6SYong Wu 134967e56c56SJames Liao vencsys: clock-controller@18000000 { 135067e56c56SJames Liao compatible = "mediatek,mt8173-vencsys", "syscon"; 135167e56c56SJames Liao reg = <0 0x18000000 0 0x1000>; 135267e56c56SJames Liao #clock-cells = <1>; 135367e56c56SJames Liao }; 135467e56c56SJames Liao 13555ff6b3a6SYong Wu larb3: larb@18001000 { 13565ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 13575ff6b3a6SYong Wu reg = <0 0x18001000 0 0x1000>; 13585ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 13595ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 13605ff6b3a6SYong Wu clocks = <&vencsys CLK_VENC_CKE1>, 13615ff6b3a6SYong Wu <&vencsys CLK_VENC_CKE0>; 13625ff6b3a6SYong Wu clock-names = "apb", "smi"; 13635ff6b3a6SYong Wu }; 13645ff6b3a6SYong Wu 13658eb80252STiffany Lin vcodec_enc: vcodec@18002000 { 13668eb80252STiffany Lin compatible = "mediatek,mt8173-vcodec-enc"; 13678eb80252STiffany Lin reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */ 13688eb80252STiffany Lin <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ 13698eb80252STiffany Lin interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>, 13708eb80252STiffany Lin <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; 13718eb80252STiffany Lin mediatek,larb = <&larb3>, 13728eb80252STiffany Lin <&larb5>; 13738eb80252STiffany Lin iommus = <&iommu M4U_PORT_VENC_RCPU>, 13748eb80252STiffany Lin <&iommu M4U_PORT_VENC_REC>, 13758eb80252STiffany Lin <&iommu M4U_PORT_VENC_BSDMA>, 13768eb80252STiffany Lin <&iommu M4U_PORT_VENC_SV_COMV>, 13778eb80252STiffany Lin <&iommu M4U_PORT_VENC_RD_COMV>, 13788eb80252STiffany Lin <&iommu M4U_PORT_VENC_CUR_LUMA>, 13798eb80252STiffany Lin <&iommu M4U_PORT_VENC_CUR_CHROMA>, 13808eb80252STiffany Lin <&iommu M4U_PORT_VENC_REF_LUMA>, 13818eb80252STiffany Lin <&iommu M4U_PORT_VENC_REF_CHROMA>, 13828eb80252STiffany Lin <&iommu M4U_PORT_VENC_NBM_RDMA>, 13838eb80252STiffany Lin <&iommu M4U_PORT_VENC_NBM_WDMA>, 13848eb80252STiffany Lin <&iommu M4U_PORT_VENC_RCPU_SET2>, 13858eb80252STiffany Lin <&iommu M4U_PORT_VENC_REC_FRM_SET2>, 13868eb80252STiffany Lin <&iommu M4U_PORT_VENC_BSDMA_SET2>, 13878eb80252STiffany Lin <&iommu M4U_PORT_VENC_SV_COMA_SET2>, 13888eb80252STiffany Lin <&iommu M4U_PORT_VENC_RD_COMA_SET2>, 13898eb80252STiffany Lin <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, 13908eb80252STiffany Lin <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, 13918eb80252STiffany Lin <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, 13928eb80252STiffany Lin <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; 13938eb80252STiffany Lin mediatek,vpu = <&vpu>; 13948eb80252STiffany Lin clocks = <&topckgen CLK_TOP_VENCPLL_D2>, 13958eb80252STiffany Lin <&topckgen CLK_TOP_VENC_SEL>, 13968eb80252STiffany Lin <&topckgen CLK_TOP_UNIVPLL1_D2>, 13978eb80252STiffany Lin <&topckgen CLK_TOP_VENC_LT_SEL>; 13988eb80252STiffany Lin clock-names = "venc_sel_src", 13998eb80252STiffany Lin "venc_sel", 14008eb80252STiffany Lin "venc_lt_sel_src", 14018eb80252STiffany Lin "venc_lt_sel"; 1402fbbad028SYunfei Dong assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>, 1403fbbad028SYunfei Dong <&topckgen CLK_TOP_VENC_LT_SEL>; 1404fbbad028SYunfei Dong assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>, 1405fbbad028SYunfei Dong <&topckgen CLK_TOP_UNIVPLL1_D2>; 14068eb80252STiffany Lin }; 14078eb80252STiffany Lin 14081180beb0SHsin-Yi Wang jpegdec: jpegdec@18004000 { 14091180beb0SHsin-Yi Wang compatible = "mediatek,mt8173-jpgdec"; 14101180beb0SHsin-Yi Wang reg = <0 0x18004000 0 0x1000>; 14111180beb0SHsin-Yi Wang interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW>; 14121180beb0SHsin-Yi Wang clocks = <&vencsys CLK_VENC_CKE0>, 14131180beb0SHsin-Yi Wang <&vencsys CLK_VENC_CKE3>; 14141180beb0SHsin-Yi Wang clock-names = "jpgdec-smi", 14151180beb0SHsin-Yi Wang "jpgdec"; 14161180beb0SHsin-Yi Wang power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 14171180beb0SHsin-Yi Wang mediatek,larb = <&larb3>; 14181180beb0SHsin-Yi Wang iommus = <&iommu M4U_PORT_JPGDEC_WDMA>, 14191180beb0SHsin-Yi Wang <&iommu M4U_PORT_JPGDEC_BSDMA>; 14201180beb0SHsin-Yi Wang }; 14211180beb0SHsin-Yi Wang 142267e56c56SJames Liao vencltsys: clock-controller@19000000 { 142367e56c56SJames Liao compatible = "mediatek,mt8173-vencltsys", "syscon"; 142467e56c56SJames Liao reg = <0 0x19000000 0 0x1000>; 142567e56c56SJames Liao #clock-cells = <1>; 142667e56c56SJames Liao }; 14275ff6b3a6SYong Wu 14285ff6b3a6SYong Wu larb5: larb@19001000 { 14295ff6b3a6SYong Wu compatible = "mediatek,mt8173-smi-larb"; 14305ff6b3a6SYong Wu reg = <0 0x19001000 0 0x1000>; 14315ff6b3a6SYong Wu mediatek,smi = <&smi_common>; 14325ff6b3a6SYong Wu power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; 14335ff6b3a6SYong Wu clocks = <&vencltsys CLK_VENCLT_CKE1>, 14345ff6b3a6SYong Wu <&vencltsys CLK_VENCLT_CKE0>; 14355ff6b3a6SYong Wu clock-names = "apb", "smi"; 14365ff6b3a6SYong Wu }; 1437b3a37248SEddie Huang }; 1438b3a37248SEddie Huang}; 1439b3a37248SEddie Huang 1440