1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright 2016 MediaTek Inc. 4 */ 5 6#include <dt-bindings/input/input.h> 7#include <dt-bindings/input/linux-event-codes.h> 8#include <dt-bindings/regulator/dlg,da9211-regulator.h> 9#include <dt-bindings/gpio/gpio.h> 10#include "mt8173.dtsi" 11 12/ { 13 aliases { 14 mmc0 = &mmc0; 15 mmc1 = &mmc1; 16 mmc2 = &mmc3; 17 }; 18 19 memory@40000000 { 20 device_type = "memory"; 21 reg = <0 0x40000000 0 0x80000000>; 22 }; 23 24 backlight: backlight { 25 compatible = "pwm-backlight"; 26 pwms = <&pwm0 0 1000000>; 27 power-supply = <&bl_fixed_reg>; 28 enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>; 29 30 pinctrl-names = "default"; 31 pinctrl-0 = <&disp_pwm0_pins>; 32 status = "okay"; 33 }; 34 35 bl_fixed_reg: fixedregulator2 { 36 compatible = "regulator-fixed"; 37 regulator-name = "bl_fixed"; 38 regulator-min-microvolt = <1800000>; 39 regulator-max-microvolt = <1800000>; 40 startup-delay-us = <1000>; 41 enable-active-high; 42 gpio = <&pio 32 GPIO_ACTIVE_HIGH>; 43 pinctrl-names = "default"; 44 pinctrl-0 = <&bl_fixed_pins>; 45 }; 46 47 chosen { 48 stdout-path = "serial0:115200n8"; 49 }; 50 51 gpio_keys: gpio-keys { 52 compatible = "gpio-keys"; 53 pinctrl-names = "default"; 54 pinctrl-0 = <&gpio_keys_pins>; 55 56 lid { 57 label = "Lid"; 58 gpios = <&pio 69 GPIO_ACTIVE_LOW>; 59 linux,code = <SW_LID>; 60 linux,input-type = <EV_SW>; 61 gpio-key,wakeup; 62 }; 63 64 power { 65 label = "Power"; 66 gpios = <&pio 14 GPIO_ACTIVE_HIGH>; 67 linux,code = <KEY_POWER>; 68 debounce-interval = <30>; 69 gpio-key,wakeup; 70 }; 71 72 tablet_mode { 73 label = "Tablet_mode"; 74 gpios = <&pio 121 GPIO_ACTIVE_HIGH>; 75 linux,code = <SW_TABLET_MODE>; 76 linux,input-type = <EV_SW>; 77 gpio-key,wakeup; 78 }; 79 80 volume_down { 81 label = "Volume_down"; 82 gpios = <&pio 123 GPIO_ACTIVE_LOW>; 83 linux,code = <KEY_VOLUMEDOWN>; 84 }; 85 86 volume_up { 87 label = "Volume_up"; 88 gpios = <&pio 124 GPIO_ACTIVE_LOW>; 89 linux,code = <KEY_VOLUMEUP>; 90 }; 91 }; 92 93 panel: panel { 94 compatible = "lg,lp120up1"; 95 power-supply = <&panel_fixed_3v3>; 96 backlight = <&backlight>; 97 98 port { 99 panel_in: endpoint { 100 remote-endpoint = <&ps8640_out>; 101 }; 102 }; 103 }; 104 105 panel_fixed_3v3: regulator1 { 106 compatible = "regulator-fixed"; 107 regulator-name = "PANEL_3V3"; 108 regulator-min-microvolt = <3300000>; 109 regulator-max-microvolt = <3300000>; 110 enable-active-high; 111 gpio = <&pio 41 GPIO_ACTIVE_HIGH>; 112 pinctrl-names = "default"; 113 pinctrl-0 = <&panel_fixed_pins>; 114 }; 115 116 ps8640_fixed_1v2: regulator2 { 117 compatible = "regulator-fixed"; 118 regulator-name = "PS8640_1V2"; 119 regulator-min-microvolt = <1200000>; 120 regulator-max-microvolt = <1200000>; 121 regulator-enable-ramp-delay = <2000>; 122 enable-active-high; 123 regulator-boot-on; 124 gpio = <&pio 30 GPIO_ACTIVE_HIGH>; 125 pinctrl-names = "default"; 126 pinctrl-0 = <&ps8640_fixed_pins>; 127 }; 128 129 sdio_fixed_3v3: fixedregulator0 { 130 compatible = "regulator-fixed"; 131 regulator-name = "3V3"; 132 regulator-min-microvolt = <3300000>; 133 regulator-max-microvolt = <3300000>; 134 gpio = <&pio 85 GPIO_ACTIVE_HIGH>; 135 pinctrl-names = "default"; 136 pinctrl-0 = <&sdio_fixed_3v3_pins>; 137 }; 138 139 sound: sound { 140 compatible = "mediatek,mt8173-rt5650"; 141 mediatek,audio-codec = <&rt5650 &hdmi0>; 142 mediatek,platform = <&afe>; 143 pinctrl-names = "default"; 144 pinctrl-0 = <&aud_i2s2>; 145 146 mediatek,mclk = <1>; 147 codec-capture { 148 sound-dai = <&rt5650 1>; 149 }; 150 }; 151 152 hdmicon: connector { 153 compatible = "hdmi-connector"; 154 label = "hdmi"; 155 type = "a"; 156 ddc-i2c-bus = <&hdmiddc0>; 157 158 port { 159 hdmi_connector_in: endpoint { 160 remote-endpoint = <&hdmi0_out>; 161 }; 162 }; 163 }; 164}; 165 166&cec { 167 status = "okay"; 168}; 169 170&cpu0 { 171 proc-supply = <&mt6397_vpca15_reg>; 172}; 173 174&cpu1 { 175 proc-supply = <&mt6397_vpca15_reg>; 176}; 177 178&cpu2 { 179 proc-supply = <&da9211_vcpu_reg>; 180 sram-supply = <&mt6397_vsramca7_reg>; 181}; 182 183&cpu3 { 184 proc-supply = <&da9211_vcpu_reg>; 185 sram-supply = <&mt6397_vsramca7_reg>; 186}; 187 188&cpu_thermal { 189 sustainable-power = <4500>; /* milliwatts */ 190 trips { 191 threshold: trip-point0 { 192 temperature = <60000>; 193 }; 194 195 target: trip-point1 { 196 temperature = <65000>; 197 }; 198 }; 199}; 200 201&dsi0 { 202 status = "okay"; 203 ports { 204 port { 205 dsi0_out: endpoint { 206 remote-endpoint = <&ps8640_in>; 207 }; 208 }; 209 }; 210}; 211 212&dpi0 { 213 status = "okay"; 214}; 215 216&hdmi0 { 217 status = "okay"; 218 ports { 219 port@1 { 220 reg = <1>; 221 222 hdmi0_out: endpoint { 223 remote-endpoint = <&hdmi_connector_in>; 224 }; 225 }; 226 }; 227}; 228 229&hdmi_phy { 230 status = "okay"; 231 mediatek,ibias = <0xc>; 232}; 233 234&i2c0 { 235 status = "okay"; 236 237 rt5650: audio-codec@1a { 238 compatible = "realtek,rt5650"; 239 reg = <0x1a>; 240 avdd-supply = <&mt6397_vgp1_reg>; 241 cpvdd-supply = <&mt6397_vcama_reg>; 242 interrupt-parent = <&pio>; 243 interrupts = <3 IRQ_TYPE_EDGE_BOTH>; 244 pinctrl-names = "default"; 245 pinctrl-0 = <&rt5650_irq>; 246 #sound-dai-cells = <1>; 247 realtek,dmic1-data-pin = <2>; 248 realtek,jd-mode = <2>; 249 }; 250 251 ps8640: edp-bridge@8 { 252 compatible = "parade,ps8640"; 253 reg = <0x8>; 254 powerdown-gpios = <&pio 127 GPIO_ACTIVE_LOW>; 255 reset-gpios = <&pio 115 GPIO_ACTIVE_LOW>; 256 pinctrl-names = "default"; 257 pinctrl-0 = <&ps8640_pins>; 258 vdd12-supply = <&ps8640_fixed_1v2>; 259 vdd33-supply = <&mt6397_vgp2_reg>; 260 261 ports { 262 #address-cells = <1>; 263 #size-cells = <0>; 264 265 port@0 { 266 reg = <0>; 267 268 ps8640_in: endpoint { 269 remote-endpoint = <&dsi0_out>; 270 }; 271 }; 272 273 port@1 { 274 reg = <1>; 275 276 ps8640_out: endpoint { 277 remote-endpoint = <&panel_in>; 278 }; 279 }; 280 }; 281 }; 282}; 283 284&i2c1 { 285 clock-frequency = <1500000>; 286 status = "okay"; 287 288 da9211: da9211@68 { 289 compatible = "dlg,da9211"; 290 reg = <0x68>; 291 interrupt-parent = <&pio>; 292 interrupts = <15 IRQ_TYPE_LEVEL_LOW>; 293 294 regulators { 295 da9211_vcpu_reg: BUCKA { 296 regulator-name = "VBUCKA"; 297 regulator-min-microvolt = < 700000>; 298 regulator-max-microvolt = <1310000>; 299 regulator-min-microamp = <2000000>; 300 regulator-max-microamp = <4400000>; 301 regulator-ramp-delay = <10000>; 302 regulator-always-on; 303 regulator-allowed-modes = <DA9211_BUCK_MODE_SYNC 304 DA9211_BUCK_MODE_AUTO>; 305 }; 306 307 da9211_vgpu_reg: BUCKB { 308 regulator-name = "VBUCKB"; 309 regulator-min-microvolt = < 700000>; 310 regulator-max-microvolt = <1310000>; 311 regulator-min-microamp = <2000000>; 312 regulator-max-microamp = <3000000>; 313 regulator-ramp-delay = <10000>; 314 }; 315 }; 316 }; 317}; 318 319&i2c2 { 320 status = "okay"; 321 322 tpm: tpm@20 { 323 compatible = "infineon,slb9645tt"; 324 reg = <0x20>; 325 powered-while-suspended; 326 }; 327}; 328 329&i2c3 { 330 clock-frequency = <400000>; 331 status = "okay"; 332 333 touchscreen: touchscreen@10 { 334 compatible = "elan,ekth3500"; 335 reg = <0x10>; 336 interrupt-parent = <&pio>; 337 interrupts = <88 IRQ_TYPE_LEVEL_LOW>; 338 }; 339}; 340 341&i2c4 { 342 clock-frequency = <400000>; 343 status = "okay"; 344 pinctrl-names = "default"; 345 pinctrl-0 = <&trackpad_irq>; 346 347 trackpad: trackpad@15 { 348 compatible = "elan,ekth3000"; 349 interrupt-parent = <&pio>; 350 interrupts = <117 IRQ_TYPE_LEVEL_LOW>; 351 reg = <0x15>; 352 vcc-supply = <&mt6397_vgp6_reg>; 353 wakeup-source; 354 }; 355}; 356 357&mipi_tx0 { 358 status = "okay"; 359}; 360 361&mmc0 { 362 status = "okay"; 363 pinctrl-names = "default", "state_uhs"; 364 pinctrl-0 = <&mmc0_pins_default>; 365 pinctrl-1 = <&mmc0_pins_uhs>; 366 bus-width = <8>; 367 max-frequency = <200000000>; 368 cap-mmc-highspeed; 369 mmc-hs200-1_8v; 370 mmc-hs400-1_8v; 371 cap-mmc-hw-reset; 372 hs400-ds-delay = <0x14015>; 373 mediatek,hs200-cmd-int-delay=<30>; 374 mediatek,hs400-cmd-int-delay=<14>; 375 mediatek,hs400-cmd-resp-sel-rising; 376 vmmc-supply = <&mt6397_vemc_3v3_reg>; 377 vqmmc-supply = <&mt6397_vio18_reg>; 378 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; 379 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 380 non-removable; 381}; 382 383&mmc1 { 384 status = "okay"; 385 pinctrl-names = "default", "state_uhs"; 386 pinctrl-0 = <&mmc1_pins_default>; 387 pinctrl-1 = <&mmc1_pins_uhs>; 388 bus-width = <4>; 389 max-frequency = <200000000>; 390 cap-sd-highspeed; 391 sd-uhs-sdr50; 392 sd-uhs-sdr104; 393 cd-gpios = <&pio 1 GPIO_ACTIVE_LOW>; 394 vmmc-supply = <&mt6397_vmch_reg>; 395 vqmmc-supply = <&mt6397_vmc_reg>; 396}; 397 398&mmc3 { 399 status = "okay"; 400 pinctrl-names = "default", "state_uhs"; 401 pinctrl-0 = <&mmc3_pins_default>; 402 pinctrl-1 = <&mmc3_pins_uhs>; 403 bus-width = <4>; 404 max-frequency = <200000000>; 405 cap-sd-highspeed; 406 sd-uhs-sdr50; 407 sd-uhs-sdr104; 408 keep-power-in-suspend; 409 enable-sdio-wakeup; 410 cap-sdio-irq; 411 vmmc-supply = <&sdio_fixed_3v3>; 412 vqmmc-supply = <&mt6397_vgp3_reg>; 413 non-removable; 414 cap-power-off-card; 415 416 #address-cells = <1>; 417 #size-cells = <0>; 418 419 btmrvl: btmrvl@2 { 420 compatible = "marvell,sd8897-bt"; 421 reg = <2>; 422 interrupt-parent = <&pio>; 423 interrupts = <119 IRQ_TYPE_LEVEL_LOW>; 424 marvell,wakeup-pin = /bits/ 16 <0x0d>; 425 marvell,wakeup-gap-ms = /bits/ 16 <0x64>; 426 }; 427 428 mwifiex: mwifiex@1 { 429 compatible = "marvell,sd8897"; 430 reg = <1>; 431 interrupt-parent = <&pio>; 432 interrupts = <38 IRQ_TYPE_LEVEL_LOW>; 433 marvell,wakeup-pin = <3>; 434 }; 435}; 436 437&nor_flash { 438 status = "okay"; 439 pinctrl-names = "default"; 440 pinctrl-0 = <&nor_gpio1_pins>; 441 442 flash@0 { 443 compatible = "jedec,spi-nor"; 444 reg = <0>; 445 spi-max-frequency = <50000000>; 446 }; 447}; 448 449&pio { 450 gpio-line-names = "EC_INT_1V8", 451 "SD_CD_L", 452 "ALC5514_IRQ", 453 "ALC5650_IRQ", 454 /* 455 * AP_FLASH_WP_L is crossystem ABI. Schematics 456 * call it SFWP_B. 457 */ 458 "AP_FLASH_WP_L", 459 "SFIN", 460 "SFCS0", 461 "SFHOLD", 462 "SFOUT", 463 "SFCK", 464 "WRAP_EVENT_S_EINT10", 465 "PMU_INT", 466 "I2S2_WS_ALC5650", 467 "I2S2_BCK_ALC5650", 468 "PWR_BTN_1V8", 469 "DA9212_IRQ", 470 "IDDIG", 471 "WATCHDOG", 472 "CEC", 473 "HDMISCK", 474 "HDMISD", 475 "HTPLG", 476 "MSDC3_DAT0", 477 "MSDC3_DAT1", 478 "MSDC3_DAT2", 479 "MSDC3_DAT3", 480 "MSDC3_CLK", 481 "MSDC3_CMD", 482 "USB_C0_OC_FLAGB", 483 "USBA_OC1_L", 484 "PS8640_1V2_ENABLE", 485 "THERM_ALERT_N", 486 "PANEL_LCD_POWER_EN", 487 "ANX7688_CHIP_PD_C", 488 "EC_IN_RW_1V8", 489 "ANX7688_1V_EN_C", 490 "USB_DP_HPD_C", 491 "TPM_DAVINT_N", 492 "MARVELL8897_IRQ", 493 "EN_USB_A0_PWR", 494 "USBA_A0_OC_L", 495 "EN_PP3300_DX_EDP", 496 "", 497 "SOC_I2C2_1V8_SDA_400K", 498 "SOC_I2C2_1V8_SCL_400K", 499 "SOC_I2C0_1V8_SDA_400K", 500 "SOC_I2C0_1V8_SCL_400K", 501 "EMMC_ID1", 502 "EMMC_ID0", 503 "MEM_CONFIG3", 504 "EMMC_ID2", 505 "MEM_CONFIG1", 506 "MEM_CONFIG2", 507 "BRD_ID2", 508 "MEM_CONFIG0", 509 "BRD_ID0", 510 "BRD_ID1", 511 "EMMC_DAT0", 512 "EMMC_DAT1", 513 "EMMC_DAT2", 514 "EMMC_DAT3", 515 "EMMC_DAT4", 516 "EMMC_DAT5", 517 "EMMC_DAT6", 518 "EMMC_DAT7", 519 "EMMC_CLK", 520 "EMMC_CMD", 521 "EMMC_RCLK", 522 "PLT_RST_L", 523 "LID_OPEN_1V8_L", 524 "AUDIO_SPI_MISO_R", 525 "", 526 "AC_OK_1V8", 527 "SD_DATA0", 528 "SD_DATA1", 529 "SD_DATA2", 530 "SD_DATA3", 531 "SD_CLK", 532 "SD_CMD", 533 "PWRAP_SPI0_MI", 534 "PWRAP_SPI0_MO", 535 "PWRAP_SPI0_CK", 536 "PWRAP_SPI0_CSN", 537 "", 538 "", 539 "WIFI_PDN", 540 "RTC32K_1V8", 541 "DISP_PWM0", 542 "TOUCHSCREEN_INT_L", 543 "", 544 "SRCLKENA0", 545 "SRCLKENA1", 546 "PS8640_MODE_CONF", 547 "TOUCHSCREEN_RESET_R", 548 "PLATFORM_PROCHOT_L", 549 "PANEL_POWER_EN", 550 "REC_MODE_L", 551 "EC_FW_UPDATE_L", 552 "ACCEL2_INT_L", 553 "HDMI_DP_INT", 554 "ACCELGYRO3_INT_L", 555 "ACCELGYRO4_INT_L", 556 "SPI_EC_CLK", 557 "SPI_EC_MI", 558 "SPI_EC_MO", 559 "SPI_EC_CSN", 560 "SOC_I2C3_1V8_SDA_400K", 561 "SOC_I2C3_1V8_SCL_400K", 562 "", 563 "", 564 "", 565 "", 566 "", 567 "", 568 "", 569 "PS8640_SYSRSTN_1V8", 570 "APIN_MAX98090_DOUT2", 571 "TP_INT_1V8_L_R", 572 "RST_USB_HUB_R", 573 "BT_WAKE_L", 574 "ACCEL1_INT_L", 575 "TABLET_MODE_L", 576 "", 577 "V_UP_IN_L_R", 578 "V_DOWN_IN_L_R", 579 "SOC_I2C1_1V8_SDA_1M", 580 "SOC_I2C1_1V8_SCL_1M", 581 "PS8640_PDN_1V8", 582 "MAX98090_LRCLK", 583 "MAX98090_BCLK", 584 "MAX98090_MCLK", 585 "APOUT_MAX98090_DIN", 586 "APIN_MAX98090_DOUT", 587 "SOC_I2C4_1V8_SDA_400K", 588 "SOC_I2C4_1V8_SCL_400K"; 589 590 aud_i2s2: aud_i2s2 { 591 pins1 { 592 pinmux = <MT8173_PIN_128_I2S0_LRCK__FUNC_I2S1_WS>, 593 <MT8173_PIN_129_I2S0_BCK__FUNC_I2S1_BCK>, 594 <MT8173_PIN_130_I2S0_MCK__FUNC_I2S1_MCK>, 595 <MT8173_PIN_131_I2S0_DATA0__FUNC_I2S1_DO_1>, 596 <MT8173_PIN_12_EINT12__FUNC_I2S2_WS>, 597 <MT8173_PIN_13_EINT13__FUNC_I2S2_BCK>, 598 <MT8173_PIN_132_I2S0_DATA1__FUNC_I2S2_DI_2>; 599 bias-pull-down; 600 }; 601 }; 602 603 bl_fixed_pins: bl_fixed_pins { 604 pins1 { 605 pinmux = <MT8173_PIN_32_UTXD2__FUNC_GPIO32>; 606 output-low; 607 }; 608 }; 609 610 bt_wake_pins: bt_wake_pins { 611 pins1 { 612 pinmux = <MT8173_PIN_119_KPROW0__FUNC_GPIO119>; 613 bias-pull-up; 614 }; 615 }; 616 617 disp_pwm0_pins: disp_pwm0_pins { 618 pins1 { 619 pinmux = <MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0>; 620 output-low; 621 }; 622 }; 623 624 gpio_keys_pins: gpio_keys_pins { 625 volume_pins { 626 pinmux = <MT8173_PIN_123_KPCOL1__FUNC_GPIO123>, 627 <MT8173_PIN_124_KPCOL2__FUNC_GPIO124>; 628 bias-pull-up; 629 }; 630 631 tablet_mode_pins { 632 pinmux = <MT8173_PIN_121_KPROW2__FUNC_GPIO121>; 633 bias-pull-up; 634 }; 635 }; 636 637 hdmi_mux_pins: hdmi_mux_pins { 638 pins1 { 639 pinmux = <MT8173_PIN_36_DAISYNC__FUNC_GPIO36>; 640 }; 641 }; 642 643 i2c1_pins_a: i2c1 { 644 da9211_pins { 645 pinmux = <MT8173_PIN_15_EINT15__FUNC_GPIO15>; 646 bias-pull-up; 647 }; 648 }; 649 650 mmc0_pins_default: mmc0default { 651 pins_cmd_dat { 652 pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>, 653 <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>, 654 <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>, 655 <MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>, 656 <MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>, 657 <MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>, 658 <MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>, 659 <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>, 660 <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>; 661 bias-pull-up; 662 }; 663 664 pins_clk { 665 pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>; 666 bias-pull-down; 667 }; 668 669 pins_rst { 670 pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>; 671 bias-pull-up; 672 }; 673 }; 674 675 mmc1_pins_default: mmc1default { 676 pins_cmd_dat { 677 pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>, 678 <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>, 679 <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>, 680 <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>, 681 <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>; 682 input-enable; 683 drive-strength = <MTK_DRIVE_4mA>; 684 bias-pull-up = <MTK_PUPD_SET_R1R0_10>; 685 }; 686 687 pins_clk { 688 pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>; 689 bias-pull-down; 690 drive-strength = <MTK_DRIVE_4mA>; 691 }; 692 693 pins_insert { 694 pinmux = <MT8173_PIN_1_EINT1__FUNC_GPIO1>; 695 bias-pull-up; 696 }; 697 }; 698 699 mmc3_pins_default: mmc3default { 700 pins_dat { 701 pinmux = <MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0>, 702 <MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1>, 703 <MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2>, 704 <MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3>; 705 input-enable; 706 drive-strength = <MTK_DRIVE_8mA>; 707 bias-pull-up = <MTK_PUPD_SET_R1R0_10>; 708 }; 709 710 pins_cmd { 711 pinmux = <MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD>; 712 input-enable; 713 drive-strength = <MTK_DRIVE_8mA>; 714 bias-pull-up = <MTK_PUPD_SET_R1R0_10>; 715 }; 716 717 pins_clk { 718 pinmux = <MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK>; 719 bias-pull-down; 720 drive-strength = <MTK_DRIVE_8mA>; 721 }; 722 }; 723 724 mmc0_pins_uhs: mmc0 { 725 pins_cmd_dat { 726 pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>, 727 <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>, 728 <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>, 729 <MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>, 730 <MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>, 731 <MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>, 732 <MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>, 733 <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>, 734 <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>; 735 input-enable; 736 drive-strength = <MTK_DRIVE_6mA>; 737 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 738 }; 739 740 pins_clk { 741 pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>; 742 drive-strength = <MTK_DRIVE_6mA>; 743 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 744 }; 745 746 pins_ds { 747 pinmux = <MT8173_PIN_67_MSDC0_DSL__FUNC_MSDC0_DSL>; 748 drive-strength = <MTK_DRIVE_10mA>; 749 bias-pull-down = <MTK_PUPD_SET_R1R0_01>; 750 }; 751 752 pins_rst { 753 pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>; 754 bias-pull-up; 755 }; 756 }; 757 758 mmc1_pins_uhs: mmc1 { 759 pins_cmd_dat { 760 pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>, 761 <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>, 762 <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>, 763 <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>, 764 <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>; 765 input-enable; 766 drive-strength = <MTK_DRIVE_6mA>; 767 bias-pull-up = <MTK_PUPD_SET_R1R0_10>; 768 }; 769 770 pins_clk { 771 pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>; 772 drive-strength = <MTK_DRIVE_8mA>; 773 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 774 }; 775 }; 776 777 mmc3_pins_uhs: mmc3 { 778 pins_dat { 779 pinmux = <MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0>, 780 <MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1>, 781 <MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2>, 782 <MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3>; 783 input-enable; 784 drive-strength = <MTK_DRIVE_8mA>; 785 bias-pull-up = <MTK_PUPD_SET_R1R0_10>; 786 }; 787 788 pins_cmd { 789 pinmux = <MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD>; 790 input-enable; 791 drive-strength = <MTK_DRIVE_8mA>; 792 bias-pull-up = <MTK_PUPD_SET_R1R0_10>; 793 }; 794 795 pins_clk { 796 pinmux = <MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK>; 797 drive-strength = <MTK_DRIVE_8mA>; 798 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 799 }; 800 }; 801 802 nor_gpio1_pins: nor { 803 pins1 { 804 pinmux = <MT8173_PIN_6_EINT6__FUNC_SFCS0>, 805 <MT8173_PIN_7_EINT7__FUNC_SFHOLD>, 806 <MT8173_PIN_8_EINT8__FUNC_SFIN>; 807 input-enable; 808 drive-strength = <MTK_DRIVE_4mA>; 809 bias-pull-up; 810 }; 811 812 pins2 { 813 pinmux = <MT8173_PIN_5_EINT5__FUNC_SFOUT>; 814 drive-strength = <MTK_DRIVE_4mA>; 815 bias-pull-up; 816 }; 817 818 pins_clk { 819 pinmux = <MT8173_PIN_9_EINT9__FUNC_SFCK>; 820 input-enable; 821 drive-strength = <MTK_DRIVE_4mA>; 822 bias-pull-up; 823 }; 824 }; 825 826 panel_fixed_pins: panel_fixed_pins { 827 pins1 { 828 pinmux = <MT8173_PIN_41_CMMCLK__FUNC_GPIO41>; 829 }; 830 }; 831 832 ps8640_pins: ps8640_pins { 833 pins1 { 834 pinmux = <MT8173_PIN_92_PCM_CLK__FUNC_GPIO92>, 835 <MT8173_PIN_115_URTS0__FUNC_GPIO115>, 836 <MT8173_PIN_127_LCM_RST__FUNC_GPIO127>; 837 }; 838 }; 839 840 ps8640_fixed_pins: ps8640_fixed_pins { 841 pins1 { 842 pinmux = <MT8173_PIN_30_URTS2__FUNC_GPIO30>; 843 }; 844 }; 845 846 rt5650_irq: rt5650_irq { 847 pins1 { 848 pinmux = <MT8173_PIN_3_EINT3__FUNC_GPIO3>; 849 bias-pull-down; 850 }; 851 }; 852 853 sdio_fixed_3v3_pins: sdio_fixed_3v3_pins { 854 pins1 { 855 pinmux = <MT8173_PIN_85_AUD_DAT_MOSI__FUNC_GPIO85>; 856 output-low; 857 }; 858 }; 859 860 spi_pins_a: spi1 { 861 pins1 { 862 pinmux = <MT8173_PIN_0_EINT0__FUNC_GPIO0>; 863 bias-pull-up; 864 }; 865 866 pins_spi { 867 pinmux = <MT8173_PIN_102_MSDC2_DAT2__FUNC_SPI_CK_1_>, 868 <MT8173_PIN_103_MSDC2_DAT3__FUNC_SPI_MI_1_>, 869 <MT8173_PIN_104_MSDC2_CLK__FUNC_SPI_MO_1_>, 870 <MT8173_PIN_105_MSDC2_CMD__FUNC_SPI_CS_1_>; 871 bias-disable; 872 }; 873 }; 874 875 trackpad_irq: trackpad_irq { 876 pins1 { 877 pinmux = <MT8173_PIN_117_URXD3__FUNC_GPIO117>; 878 input-enable; 879 bias-pull-up; 880 }; 881 }; 882 883 usb_pins: usb { 884 pins1 { 885 pinmux = <MT8173_PIN_101_MSDC2_DAT1__FUNC_GPIO101>; 886 output-high; 887 bias-disable; 888 }; 889 }; 890 891 wifi_wake_pins: wifi_wake_pins { 892 pins1 { 893 pinmux = <MT8173_PIN_38_CONN_RST__FUNC_GPIO38>; 894 bias-pull-up; 895 }; 896 }; 897}; 898 899&pwm0 { 900 status = "okay"; 901}; 902 903&pwrap { 904 pmic: mt6397 { 905 compatible = "mediatek,mt6397"; 906 #address-cells = <1>; 907 #size-cells = <1>; 908 interrupt-parent = <&pio>; 909 interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; 910 interrupt-controller; 911 #interrupt-cells = <2>; 912 913 clock: mt6397clock { 914 compatible = "mediatek,mt6397-clk"; 915 #clock-cells = <1>; 916 }; 917 918 pio6397: pinctrl { 919 compatible = "mediatek,mt6397-pinctrl"; 920 pins-are-numbered; 921 gpio-controller; 922 #gpio-cells = <2>; 923 }; 924 925 regulator: mt6397regulator { 926 compatible = "mediatek,mt6397-regulator"; 927 928 mt6397_vpca15_reg: buck_vpca15 { 929 regulator-compatible = "buck_vpca15"; 930 regulator-name = "vpca15"; 931 regulator-min-microvolt = < 700000>; 932 regulator-max-microvolt = <1350000>; 933 regulator-ramp-delay = <12500>; 934 regulator-always-on; 935 regulator-allowed-modes = <0 1>; 936 }; 937 938 mt6397_vpca7_reg: buck_vpca7 { 939 regulator-compatible = "buck_vpca7"; 940 regulator-name = "vpca7"; 941 regulator-min-microvolt = < 700000>; 942 regulator-max-microvolt = <1350000>; 943 regulator-ramp-delay = <12500>; 944 regulator-enable-ramp-delay = <115>; 945 regulator-always-on; 946 }; 947 948 mt6397_vsramca15_reg: buck_vsramca15 { 949 regulator-compatible = "buck_vsramca15"; 950 regulator-name = "vsramca15"; 951 regulator-min-microvolt = < 700000>; 952 regulator-max-microvolt = <1350000>; 953 regulator-ramp-delay = <12500>; 954 regulator-always-on; 955 }; 956 957 mt6397_vsramca7_reg: buck_vsramca7 { 958 regulator-compatible = "buck_vsramca7"; 959 regulator-name = "vsramca7"; 960 regulator-min-microvolt = < 700000>; 961 regulator-max-microvolt = <1350000>; 962 regulator-ramp-delay = <12500>; 963 regulator-always-on; 964 }; 965 966 mt6397_vcore_reg: buck_vcore { 967 regulator-compatible = "buck_vcore"; 968 regulator-name = "vcore"; 969 regulator-min-microvolt = < 700000>; 970 regulator-max-microvolt = <1350000>; 971 regulator-ramp-delay = <12500>; 972 regulator-always-on; 973 }; 974 975 mt6397_vgpu_reg: buck_vgpu { 976 regulator-compatible = "buck_vgpu"; 977 regulator-name = "vgpu"; 978 regulator-min-microvolt = < 700000>; 979 regulator-max-microvolt = <1350000>; 980 regulator-ramp-delay = <12500>; 981 regulator-enable-ramp-delay = <115>; 982 }; 983 984 mt6397_vdrm_reg: buck_vdrm { 985 regulator-compatible = "buck_vdrm"; 986 regulator-name = "vdrm"; 987 regulator-min-microvolt = <1200000>; 988 regulator-max-microvolt = <1400000>; 989 regulator-ramp-delay = <12500>; 990 regulator-always-on; 991 }; 992 993 mt6397_vio18_reg: buck_vio18 { 994 regulator-compatible = "buck_vio18"; 995 regulator-name = "vio18"; 996 regulator-min-microvolt = <1620000>; 997 regulator-max-microvolt = <1980000>; 998 regulator-ramp-delay = <12500>; 999 regulator-always-on; 1000 }; 1001 1002 mt6397_vtcxo_reg: ldo_vtcxo { 1003 regulator-compatible = "ldo_vtcxo"; 1004 regulator-name = "vtcxo"; 1005 regulator-always-on; 1006 }; 1007 1008 mt6397_va28_reg: ldo_va28 { 1009 regulator-compatible = "ldo_va28"; 1010 regulator-name = "va28"; 1011 }; 1012 1013 mt6397_vcama_reg: ldo_vcama { 1014 regulator-compatible = "ldo_vcama"; 1015 regulator-name = "vcama"; 1016 regulator-min-microvolt = <1800000>; 1017 regulator-max-microvolt = <1800000>; 1018 regulator-enable-ramp-delay = <218>; 1019 }; 1020 1021 mt6397_vio28_reg: ldo_vio28 { 1022 regulator-compatible = "ldo_vio28"; 1023 regulator-name = "vio28"; 1024 regulator-always-on; 1025 }; 1026 1027 mt6397_vusb_reg: ldo_vusb { 1028 regulator-compatible = "ldo_vusb"; 1029 regulator-name = "vusb"; 1030 }; 1031 1032 mt6397_vmc_reg: ldo_vmc { 1033 regulator-compatible = "ldo_vmc"; 1034 regulator-name = "vmc"; 1035 regulator-min-microvolt = <1800000>; 1036 regulator-max-microvolt = <3300000>; 1037 regulator-enable-ramp-delay = <218>; 1038 }; 1039 1040 mt6397_vmch_reg: ldo_vmch { 1041 regulator-compatible = "ldo_vmch"; 1042 regulator-name = "vmch"; 1043 regulator-min-microvolt = <3000000>; 1044 regulator-max-microvolt = <3300000>; 1045 regulator-enable-ramp-delay = <218>; 1046 }; 1047 1048 mt6397_vemc_3v3_reg: ldo_vemc3v3 { 1049 regulator-compatible = "ldo_vemc3v3"; 1050 regulator-name = "vemc_3v3"; 1051 regulator-min-microvolt = <3000000>; 1052 regulator-max-microvolt = <3300000>; 1053 regulator-enable-ramp-delay = <218>; 1054 }; 1055 1056 mt6397_vgp1_reg: ldo_vgp1 { 1057 regulator-compatible = "ldo_vgp1"; 1058 regulator-name = "vcamd"; 1059 regulator-min-microvolt = <1800000>; 1060 regulator-max-microvolt = <1800000>; 1061 regulator-enable-ramp-delay = <240>; 1062 }; 1063 1064 mt6397_vgp2_reg: ldo_vgp2 { 1065 regulator-compatible = "ldo_vgp2"; 1066 regulator-name = "vcamio"; 1067 regulator-min-microvolt = <3300000>; 1068 regulator-max-microvolt = <3300000>; 1069 regulator-enable-ramp-delay = <218>; 1070 }; 1071 1072 mt6397_vgp3_reg: ldo_vgp3 { 1073 regulator-compatible = "ldo_vgp3"; 1074 regulator-name = "vcamaf"; 1075 regulator-min-microvolt = <1800000>; 1076 regulator-max-microvolt = <1800000>; 1077 regulator-enable-ramp-delay = <218>; 1078 }; 1079 1080 mt6397_vgp4_reg: ldo_vgp4 { 1081 regulator-compatible = "ldo_vgp4"; 1082 regulator-name = "vgp4"; 1083 regulator-min-microvolt = <1200000>; 1084 regulator-max-microvolt = <3300000>; 1085 regulator-enable-ramp-delay = <218>; 1086 }; 1087 1088 mt6397_vgp5_reg: ldo_vgp5 { 1089 regulator-compatible = "ldo_vgp5"; 1090 regulator-name = "vgp5"; 1091 regulator-min-microvolt = <1200000>; 1092 regulator-max-microvolt = <3000000>; 1093 regulator-enable-ramp-delay = <218>; 1094 }; 1095 1096 mt6397_vgp6_reg: ldo_vgp6 { 1097 regulator-compatible = "ldo_vgp6"; 1098 regulator-name = "vgp6"; 1099 regulator-min-microvolt = <3300000>; 1100 regulator-max-microvolt = <3300000>; 1101 regulator-enable-ramp-delay = <218>; 1102 regulator-always-on; 1103 }; 1104 1105 mt6397_vibr_reg: ldo_vibr { 1106 regulator-compatible = "ldo_vibr"; 1107 regulator-name = "vibr"; 1108 regulator-min-microvolt = <1300000>; 1109 regulator-max-microvolt = <3300000>; 1110 regulator-enable-ramp-delay = <218>; 1111 }; 1112 }; 1113 1114 rtc: mt6397rtc { 1115 compatible = "mediatek,mt6397-rtc"; 1116 }; 1117 1118 syscfg_pctl_pmic: syscfg_pctl_pmic@c000 { 1119 compatible = "mediatek,mt6397-pctl-pmic-syscfg", 1120 "syscon"; 1121 reg = <0 0x0000c000 0 0x0108>; 1122 }; 1123 }; 1124}; 1125 1126&spi { 1127 pinctrl-names = "default"; 1128 pinctrl-0 = <&spi_pins_a>; 1129 mediatek,pad-select = <1>; 1130 status = "okay"; 1131 /* clients */ 1132 cros_ec: ec@0 { 1133 compatible = "google,cros-ec-spi"; 1134 reg = <0x0>; 1135 spi-max-frequency = <12000000>; 1136 interrupt-parent = <&pio>; 1137 interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 1138 google,cros-ec-spi-msg-delay = <500>; 1139 1140 i2c_tunnel: i2c-tunnel0 { 1141 compatible = "google,cros-ec-i2c-tunnel"; 1142 google,remote-bus = <0>; 1143 #address-cells = <1>; 1144 #size-cells = <0>; 1145 1146 battery: sbs-battery@b { 1147 compatible = "sbs,sbs-battery"; 1148 reg = <0xb>; 1149 sbs,i2c-retry-count = <2>; 1150 sbs,poll-retry-count = <1>; 1151 }; 1152 }; 1153 }; 1154}; 1155 1156&ssusb { 1157 dr_mode = "host"; 1158 wakeup-source; 1159 vusb33-supply = <&mt6397_vusb_reg>; 1160 status = "okay"; 1161}; 1162 1163&thermal { 1164 bank0-supply = <&mt6397_vpca15_reg>; 1165 bank1-supply = <&da9211_vcpu_reg>; 1166}; 1167 1168&uart0 { 1169 status = "okay"; 1170}; 1171 1172&usb_host { 1173 pinctrl-names = "default"; 1174 pinctrl-0 = <&usb_pins>; 1175 vusb33-supply = <&mt6397_vusb_reg>; 1176 status = "okay"; 1177}; 1178 1179#include <arm/cros-ec-keyboard.dtsi> 1180