1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright 2016 MediaTek Inc.
4 */
5
6#include <dt-bindings/input/input.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/regulator/dlg,da9211-regulator.h>
9#include <dt-bindings/gpio/gpio.h>
10#include "mt8173.dtsi"
11
12/ {
13	memory@40000000 {
14		device_type = "memory";
15		reg = <0 0x40000000 0 0x80000000>;
16	};
17
18	backlight: backlight {
19		compatible = "pwm-backlight";
20		pwms = <&pwm0 0 1000000>;
21		power-supply = <&bl_fixed_reg>;
22		enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>;
23
24		pinctrl-names = "default";
25		pinctrl-0 = <&disp_pwm0_pins>;
26		status = "okay";
27	};
28
29	bl_fixed_reg: fixedregulator2 {
30		compatible = "regulator-fixed";
31		regulator-name = "bl_fixed";
32		regulator-min-microvolt = <1800000>;
33		regulator-max-microvolt = <1800000>;
34		startup-delay-us = <1000>;
35		enable-active-high;
36		gpio = <&pio 32 GPIO_ACTIVE_HIGH>;
37		pinctrl-names = "default";
38		pinctrl-0 = <&bl_fixed_pins>;
39	};
40
41	chosen {
42		stdout-path = "serial0:115200n8";
43	};
44
45	gpio_keys: gpio-keys {
46		compatible = "gpio-keys";
47		pinctrl-names = "default";
48		pinctrl-0 = <&gpio_keys_pins>;
49
50		lid {
51			label = "Lid";
52			gpios = <&pio 69 GPIO_ACTIVE_LOW>;
53			linux,code = <SW_LID>;
54			linux,input-type = <EV_SW>;
55			gpio-key,wakeup;
56		};
57
58		power {
59			label = "Power";
60			gpios = <&pio 14 GPIO_ACTIVE_HIGH>;
61			linux,code = <KEY_POWER>;
62			debounce-interval = <30>;
63			gpio-key,wakeup;
64		};
65
66		tablet_mode {
67			label = "Tablet_mode";
68			gpios = <&pio 121 GPIO_ACTIVE_HIGH>;
69			linux,code = <SW_TABLET_MODE>;
70			linux,input-type = <EV_SW>;
71			gpio-key,wakeup;
72		};
73
74		volume_down {
75			label = "Volume_down";
76			gpios = <&pio 123 GPIO_ACTIVE_LOW>;
77			linux,code = <KEY_VOLUMEDOWN>;
78		};
79
80		volume_up {
81			label = "Volume_up";
82			gpios = <&pio 124 GPIO_ACTIVE_LOW>;
83			linux,code = <KEY_VOLUMEUP>;
84		};
85	};
86
87	panel: panel {
88		compatible = "lg,lp120up1";
89		power-supply = <&panel_fixed_3v3>;
90		ddc-i2c-bus = <&i2c0>;
91		backlight = <&backlight>;
92
93		port {
94			panel_in: endpoint {
95				remote-endpoint = <&ps8640_out>;
96			};
97		};
98	};
99
100	panel_fixed_3v3: regulator1 {
101		compatible = "regulator-fixed";
102		regulator-name = "PANEL_3V3";
103		regulator-min-microvolt = <3300000>;
104		regulator-max-microvolt = <3300000>;
105		enable-active-high;
106		gpio = <&pio 41 GPIO_ACTIVE_HIGH>;
107		pinctrl-names = "default";
108		pinctrl-0 = <&panel_fixed_pins>;
109	};
110
111	ps8640_fixed_1v2: regulator2 {
112		compatible = "regulator-fixed";
113		regulator-name = "PS8640_1V2";
114		regulator-min-microvolt = <1200000>;
115		regulator-max-microvolt = <1200000>;
116		regulator-enable-ramp-delay = <2000>;
117		enable-active-high;
118		regulator-boot-on;
119		gpio = <&pio 30 GPIO_ACTIVE_HIGH>;
120		pinctrl-names = "default";
121		pinctrl-0 = <&ps8640_fixed_pins>;
122	};
123
124	sdio_fixed_3v3: fixedregulator0 {
125		compatible = "regulator-fixed";
126		regulator-name = "3V3";
127		regulator-min-microvolt = <3300000>;
128		regulator-max-microvolt = <3300000>;
129		gpio = <&pio 85 GPIO_ACTIVE_HIGH>;
130		pinctrl-names = "default";
131		pinctrl-0 = <&sdio_fixed_3v3_pins>;
132	};
133
134	sound: sound {
135		compatible = "mediatek,mt8173-rt5650";
136		mediatek,audio-codec = <&rt5650 &hdmi0>;
137		mediatek,platform = <&afe>;
138		pinctrl-names = "default";
139		pinctrl-0 = <&aud_i2s2>;
140
141		mediatek,mclk = <1>;
142		codec-capture {
143			sound-dai = <&rt5650 1>;
144		};
145	};
146
147	hdmicon: connector {
148		compatible = "hdmi-connector";
149		label = "hdmi";
150		type = "a";
151		ddc-i2c-bus = <&hdmiddc0>;
152
153		port {
154			hdmi_connector_in: endpoint {
155				remote-endpoint = <&hdmi0_out>;
156			};
157		};
158	};
159};
160
161&cec {
162	status = "okay";
163};
164
165&cpu0 {
166	proc-supply = <&mt6397_vpca15_reg>;
167};
168
169&cpu1 {
170	proc-supply = <&mt6397_vpca15_reg>;
171};
172
173&cpu2 {
174	proc-supply = <&da9211_vcpu_reg>;
175	sram-supply = <&mt6397_vsramca7_reg>;
176};
177
178&cpu3 {
179	proc-supply = <&da9211_vcpu_reg>;
180	sram-supply = <&mt6397_vsramca7_reg>;
181};
182
183&cpu_thermal {
184	sustainable-power = <4500>; /* milliwatts */
185	trips {
186		threshold: trip-point0 {
187			temperature = <60000>;
188		};
189
190		target: trip-point1 {
191			temperature = <65000>;
192		};
193	};
194};
195
196&dsi0 {
197	status = "okay";
198	ports {
199		port {
200			dsi0_out: endpoint {
201				remote-endpoint = <&ps8640_in>;
202			};
203		};
204	};
205};
206
207&dpi0 {
208	status = "okay";
209};
210
211&hdmi0 {
212	status = "okay";
213	ports {
214		port@1 {
215			reg = <1>;
216
217			hdmi0_out: endpoint {
218				remote-endpoint = <&hdmi_connector_in>;
219			};
220		};
221	};
222};
223
224&hdmi_phy {
225	status = "okay";
226	mediatek,ibias = <0xc>;
227};
228
229&i2c0 {
230	status = "okay";
231
232	rt5650: audio-codec@1a {
233		compatible = "realtek,rt5650";
234		reg = <0x1a>;
235		avdd-supply = <&mt6397_vgp1_reg>;
236		cpvdd-supply = <&mt6397_vcama_reg>;
237		interrupt-parent = <&pio>;
238		interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
239		pinctrl-names = "default";
240		pinctrl-0 = <&rt5650_irq>;
241		#sound-dai-cells = <1>;
242		realtek,dmic1-data-pin = <2>;
243		realtek,jd-mode = <2>;
244	};
245
246	ps8640: edp-bridge@8 {
247		compatible = "parade,ps8640";
248		reg = <0x8>;
249		powerdown-gpios = <&pio 127 GPIO_ACTIVE_LOW>;
250		reset-gpios = <&pio 115 GPIO_ACTIVE_LOW>;
251		pinctrl-names = "default";
252		pinctrl-0 = <&ps8640_pins>;
253		vdd12-supply = <&ps8640_fixed_1v2>;
254		vdd33-supply = <&mt6397_vgp2_reg>;
255
256		ports {
257			#address-cells = <1>;
258			#size-cells = <0>;
259
260			port@0 {
261				reg = <0>;
262
263				ps8640_in: endpoint {
264					remote-endpoint = <&dsi0_out>;
265				};
266			};
267
268			port@1 {
269				reg = <1>;
270
271				ps8640_out: endpoint {
272					remote-endpoint = <&panel_in>;
273				};
274			};
275		};
276	};
277};
278
279&i2c1 {
280	clock-frequency = <1500000>;
281	status = "okay";
282
283	da9211: da9211@68 {
284		compatible = "dlg,da9211";
285		reg = <0x68>;
286		interrupt-parent = <&pio>;
287		interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
288
289		regulators {
290			da9211_vcpu_reg: BUCKA {
291				regulator-name = "VBUCKA";
292				regulator-min-microvolt = < 700000>;
293				regulator-max-microvolt = <1310000>;
294				regulator-min-microamp  = <2000000>;
295				regulator-max-microamp  = <4400000>;
296				regulator-ramp-delay = <10000>;
297				regulator-always-on;
298				regulator-allowed-modes = <DA9211_BUCK_MODE_SYNC
299							   DA9211_BUCK_MODE_AUTO>;
300			};
301
302			da9211_vgpu_reg: BUCKB {
303				regulator-name = "VBUCKB";
304				regulator-min-microvolt = < 700000>;
305				regulator-max-microvolt = <1310000>;
306				regulator-min-microamp  = <2000000>;
307				regulator-max-microamp  = <3000000>;
308				regulator-ramp-delay = <10000>;
309			};
310		};
311	};
312};
313
314&i2c2 {
315	status = "okay";
316
317	tpm: tpm@20 {
318		compatible = "infineon,slb9645tt";
319		reg = <0x20>;
320		powered-while-suspended;
321	};
322};
323
324&i2c3 {
325	clock-frequency = <400000>;
326	status = "okay";
327
328	touchscreen: touchscreen@10 {
329		compatible = "elan,ekth3500";
330		reg = <0x10>;
331		interrupt-parent = <&pio>;
332		interrupts = <88 IRQ_TYPE_LEVEL_LOW>;
333	};
334};
335
336&i2c4 {
337	clock-frequency = <400000>;
338	status = "okay";
339	pinctrl-names = "default";
340	pinctrl-0 = <&trackpad_irq>;
341
342	trackpad: trackpad@15 {
343		compatible = "elan,ekth3000";
344		interrupt-parent = <&pio>;
345		interrupts = <117 IRQ_TYPE_LEVEL_LOW>;
346		reg = <0x15>;
347		vcc-supply = <&mt6397_vgp6_reg>;
348		wakeup-source;
349	};
350};
351
352&mipi_tx0 {
353	status = "okay";
354};
355
356&mmc0 {
357	status = "okay";
358	pinctrl-names = "default", "state_uhs";
359	pinctrl-0 = <&mmc0_pins_default>;
360	pinctrl-1 = <&mmc0_pins_uhs>;
361	bus-width = <8>;
362	max-frequency = <200000000>;
363	cap-mmc-highspeed;
364	mmc-hs200-1_8v;
365	mmc-hs400-1_8v;
366	cap-mmc-hw-reset;
367	hs400-ds-delay = <0x14015>;
368	mediatek,hs200-cmd-int-delay=<30>;
369	mediatek,hs400-cmd-int-delay=<14>;
370	mediatek,hs400-cmd-resp-sel-rising;
371	vmmc-supply = <&mt6397_vemc_3v3_reg>;
372	vqmmc-supply = <&mt6397_vio18_reg>;
373	assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
374	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
375	non-removable;
376};
377
378&mmc1 {
379	status = "okay";
380	pinctrl-names = "default", "state_uhs";
381	pinctrl-0 = <&mmc1_pins_default>;
382	pinctrl-1 = <&mmc1_pins_uhs>;
383	bus-width = <4>;
384	max-frequency = <200000000>;
385	cap-sd-highspeed;
386	sd-uhs-sdr50;
387	sd-uhs-sdr104;
388	cd-gpios = <&pio 1 GPIO_ACTIVE_LOW>;
389	vmmc-supply = <&mt6397_vmch_reg>;
390	vqmmc-supply = <&mt6397_vmc_reg>;
391};
392
393&mmc3 {
394	status = "okay";
395	pinctrl-names = "default", "state_uhs";
396	pinctrl-0 = <&mmc3_pins_default>;
397	pinctrl-1 = <&mmc3_pins_uhs>;
398	bus-width = <4>;
399	max-frequency = <200000000>;
400	cap-sd-highspeed;
401	sd-uhs-sdr50;
402	sd-uhs-sdr104;
403	keep-power-in-suspend;
404	enable-sdio-wakeup;
405	cap-sdio-irq;
406	vmmc-supply = <&sdio_fixed_3v3>;
407	vqmmc-supply = <&mt6397_vgp3_reg>;
408	non-removable;
409	cap-power-off-card;
410
411	#address-cells = <1>;
412	#size-cells = <0>;
413
414	btmrvl: btmrvl@2 {
415		compatible = "marvell,sd8897-bt";
416		reg = <2>;
417		interrupt-parent = <&pio>;
418		interrupts = <119 IRQ_TYPE_LEVEL_LOW>;
419		marvell,wakeup-pin = /bits/ 16 <0x0d>;
420		marvell,wakeup-gap-ms = /bits/ 16 <0x64>;
421	};
422
423	mwifiex: mwifiex@1 {
424		compatible = "marvell,sd8897";
425		reg = <1>;
426		interrupt-parent = <&pio>;
427		interrupts = <38 IRQ_TYPE_LEVEL_LOW>;
428		marvell,wakeup-pin = <3>;
429	};
430};
431
432&nor_flash {
433	status = "okay";
434	pinctrl-names = "default";
435	pinctrl-0 = <&nor_gpio1_pins>;
436	bus-width = <8>;
437	max-frequency = <50000000>;
438	non-removable;
439	flash@0 {
440		compatible = "jedec,spi-nor";
441		reg = <0>;
442	};
443};
444
445&pio {
446	gpio-line-names = "EC_INT_1V8",
447			  "SD_CD_L",
448			  "ALC5514_IRQ",
449			  "ALC5650_IRQ",
450			  /*
451			   * AP_FLASH_WP_L is crossystem ABI. Schematics
452			   * call it SFWP_B.
453			   */
454			  "AP_FLASH_WP_L",
455			  "SFIN",
456			  "SFCS0",
457			  "SFHOLD",
458			  "SFOUT",
459			  "SFCK",
460			  "WRAP_EVENT_S_EINT10",
461			  "PMU_INT",
462			  "I2S2_WS_ALC5650",
463			  "I2S2_BCK_ALC5650",
464			  "PWR_BTN_1V8",
465			  "DA9212_IRQ",
466			  "IDDIG",
467			  "WATCHDOG",
468			  "CEC",
469			  "HDMISCK",
470			  "HDMISD",
471			  "HTPLG",
472			  "MSDC3_DAT0",
473			  "MSDC3_DAT1",
474			  "MSDC3_DAT2",
475			  "MSDC3_DAT3",
476			  "MSDC3_CLK",
477			  "MSDC3_CMD",
478			  "USB_C0_OC_FLAGB",
479			  "USBA_OC1_L",
480			  "PS8640_1V2_ENABLE",
481			  "THERM_ALERT_N",
482			  "PANEL_LCD_POWER_EN",
483			  "ANX7688_CHIP_PD_C",
484			  "EC_IN_RW_1V8",
485			  "ANX7688_1V_EN_C",
486			  "USB_DP_HPD_C",
487			  "TPM_DAVINT_N",
488			  "MARVELL8897_IRQ",
489			  "EN_USB_A0_PWR",
490			  "USBA_A0_OC_L",
491			  "EN_PP3300_DX_EDP",
492			  "",
493			  "SOC_I2C2_1V8_SDA_400K",
494			  "SOC_I2C2_1V8_SCL_400K",
495			  "SOC_I2C0_1V8_SDA_400K",
496			  "SOC_I2C0_1V8_SCL_400K",
497			  "EMMC_ID1",
498			  "EMMC_ID0",
499			  "MEM_CONFIG3",
500			  "EMMC_ID2",
501			  "MEM_CONFIG1",
502			  "MEM_CONFIG2",
503			  "BRD_ID2",
504			  "MEM_CONFIG0",
505			  "BRD_ID0",
506			  "BRD_ID1",
507			  "EMMC_DAT0",
508			  "EMMC_DAT1",
509			  "EMMC_DAT2",
510			  "EMMC_DAT3",
511			  "EMMC_DAT4",
512			  "EMMC_DAT5",
513			  "EMMC_DAT6",
514			  "EMMC_DAT7",
515			  "EMMC_CLK",
516			  "EMMC_CMD",
517			  "EMMC_RCLK",
518			  "PLT_RST_L",
519			  "LID_OPEN_1V8_L",
520			  "AUDIO_SPI_MISO_R",
521			  "",
522			  "AC_OK_1V8",
523			  "SD_DATA0",
524			  "SD_DATA1",
525			  "SD_DATA2",
526			  "SD_DATA3",
527			  "SD_CLK",
528			  "SD_CMD",
529			  "PWRAP_SPI0_MI",
530			  "PWRAP_SPI0_MO",
531			  "PWRAP_SPI0_CK",
532			  "PWRAP_SPI0_CSN",
533			  "",
534			  "",
535			  "WIFI_PDN",
536			  "RTC32K_1V8",
537			  "DISP_PWM0",
538			  "TOUCHSCREEN_INT_L",
539			  "",
540			  "SRCLKENA0",
541			  "SRCLKENA1",
542			  "PS8640_MODE_CONF",
543			  "TOUCHSCREEN_RESET_R",
544			  "PLATFORM_PROCHOT_L",
545			  "PANEL_POWER_EN",
546			  "REC_MODE_L",
547			  "EC_FW_UPDATE_L",
548			  "ACCEL2_INT_L",
549			  "HDMI_DP_INT",
550			  "ACCELGYRO3_INT_L",
551			  "ACCELGYRO4_INT_L",
552			  "SPI_EC_CLK",
553			  "SPI_EC_MI",
554			  "SPI_EC_MO",
555			  "SPI_EC_CSN",
556			  "SOC_I2C3_1V8_SDA_400K",
557			  "SOC_I2C3_1V8_SCL_400K",
558			  "",
559			  "",
560			  "",
561			  "",
562			  "",
563			  "",
564			  "",
565			  "PS8640_SYSRSTN_1V8",
566			  "APIN_MAX98090_DOUT2",
567			  "TP_INT_1V8_L_R",
568			  "RST_USB_HUB_R",
569			  "BT_WAKE_L",
570			  "ACCEL1_INT_L",
571			  "TABLET_MODE_L",
572			  "",
573			  "V_UP_IN_L_R",
574			  "V_DOWN_IN_L_R",
575			  "SOC_I2C1_1V8_SDA_1M",
576			  "SOC_I2C1_1V8_SCL_1M",
577			  "PS8640_PDN_1V8",
578			  "MAX98090_LRCLK",
579			  "MAX98090_BCLK",
580			  "MAX98090_MCLK",
581			  "APOUT_MAX98090_DIN",
582			  "APIN_MAX98090_DOUT",
583			  "SOC_I2C4_1V8_SDA_400K",
584			  "SOC_I2C4_1V8_SCL_400K";
585
586	aud_i2s2: aud_i2s2 {
587		pins1 {
588			pinmux = <MT8173_PIN_128_I2S0_LRCK__FUNC_I2S1_WS>,
589				 <MT8173_PIN_129_I2S0_BCK__FUNC_I2S1_BCK>,
590				 <MT8173_PIN_130_I2S0_MCK__FUNC_I2S1_MCK>,
591				 <MT8173_PIN_131_I2S0_DATA0__FUNC_I2S1_DO_1>,
592				 <MT8173_PIN_12_EINT12__FUNC_I2S2_WS>,
593				 <MT8173_PIN_13_EINT13__FUNC_I2S2_BCK>,
594				 <MT8173_PIN_132_I2S0_DATA1__FUNC_I2S2_DI_2>;
595			bias-pull-down;
596		};
597	};
598
599	bl_fixed_pins: bl_fixed_pins {
600		pins1 {
601			pinmux = <MT8173_PIN_32_UTXD2__FUNC_GPIO32>;
602			output-low;
603		};
604	};
605
606	bt_wake_pins: bt_wake_pins {
607		pins1 {
608			pinmux = <MT8173_PIN_119_KPROW0__FUNC_GPIO119>;
609			bias-pull-up;
610		};
611	};
612
613	disp_pwm0_pins: disp_pwm0_pins {
614		pins1 {
615			pinmux = <MT8173_PIN_87_DISP_PWM0__FUNC_DISP_PWM0>;
616			output-low;
617		};
618	};
619
620	gpio_keys_pins: gpio_keys_pins {
621		volume_pins {
622			pinmux = <MT8173_PIN_123_KPCOL1__FUNC_GPIO123>,
623				 <MT8173_PIN_124_KPCOL2__FUNC_GPIO124>;
624			bias-pull-up;
625		};
626
627		tablet_mode_pins {
628			pinmux = <MT8173_PIN_121_KPROW2__FUNC_GPIO121>;
629			bias-pull-up;
630		};
631	};
632
633	hdmi_mux_pins: hdmi_mux_pins {
634		pins1 {
635			pinmux = <MT8173_PIN_36_DAISYNC__FUNC_GPIO36>;
636		};
637	};
638
639	i2c1_pins_a: i2c1 {
640		da9211_pins {
641			pinmux = <MT8173_PIN_15_EINT15__FUNC_GPIO15>;
642			bias-pull-up;
643		};
644	};
645
646	mmc0_pins_default: mmc0default {
647		pins_cmd_dat {
648			pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
649				 <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
650				 <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
651				 <MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
652				 <MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
653				 <MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
654				 <MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
655				 <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
656				 <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>;
657			bias-pull-up;
658		};
659
660		pins_clk {
661			pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>;
662			bias-pull-down;
663		};
664
665		pins_rst {
666			pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>;
667			bias-pull-up;
668		};
669	};
670
671	mmc1_pins_default: mmc1default {
672		pins_cmd_dat {
673			pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
674				 <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
675				 <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
676				 <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
677				 <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>;
678			input-enable;
679			drive-strength = <MTK_DRIVE_4mA>;
680			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
681		};
682
683		pins_clk {
684			pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>;
685			bias-pull-down;
686			drive-strength = <MTK_DRIVE_4mA>;
687		};
688
689		pins_insert {
690			pinmux = <MT8173_PIN_1_EINT1__FUNC_GPIO1>;
691			bias-pull-up;
692		};
693	};
694
695	mmc3_pins_default: mmc3default {
696		pins_dat {
697			pinmux = <MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0>,
698				 <MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1>,
699				 <MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2>,
700				 <MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3>;
701			input-enable;
702			drive-strength = <MTK_DRIVE_8mA>;
703			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
704		};
705
706		pins_cmd {
707			pinmux = <MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD>;
708			input-enable;
709			drive-strength = <MTK_DRIVE_8mA>;
710			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
711		};
712
713		pins_clk {
714			pinmux = <MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK>;
715			bias-pull-down;
716			drive-strength = <MTK_DRIVE_8mA>;
717		};
718	};
719
720	mmc0_pins_uhs: mmc0 {
721		pins_cmd_dat {
722			pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
723				 <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
724				 <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
725				 <MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
726				 <MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
727				 <MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
728				 <MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
729				 <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
730				 <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>;
731			input-enable;
732			drive-strength = <MTK_DRIVE_6mA>;
733			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
734		};
735
736		pins_clk {
737			pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>;
738			drive-strength = <MTK_DRIVE_6mA>;
739			bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
740		};
741
742		pins_ds {
743			pinmux = <MT8173_PIN_67_MSDC0_DSL__FUNC_MSDC0_DSL>;
744			drive-strength = <MTK_DRIVE_10mA>;
745			bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
746		};
747
748		pins_rst {
749			pinmux = <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>;
750			bias-pull-up;
751		};
752	};
753
754	mmc1_pins_uhs: mmc1 {
755		pins_cmd_dat {
756			pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
757				 <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
758				 <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
759				 <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
760				 <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>;
761			input-enable;
762			drive-strength = <MTK_DRIVE_6mA>;
763			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
764		};
765
766		pins_clk {
767			pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>;
768			drive-strength = <MTK_DRIVE_8mA>;
769			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
770		};
771	};
772
773	mmc3_pins_uhs: mmc3 {
774		pins_dat {
775			pinmux = <MT8173_PIN_22_MSDC3_DAT0__FUNC_MSDC3_DAT0>,
776				 <MT8173_PIN_23_MSDC3_DAT1__FUNC_MSDC3_DAT1>,
777				 <MT8173_PIN_24_MSDC3_DAT2__FUNC_MSDC3_DAT2>,
778				 <MT8173_PIN_25_MSDC3_DAT3__FUNC_MSDC3_DAT3>;
779			input-enable;
780			drive-strength = <MTK_DRIVE_8mA>;
781			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
782		};
783
784		pins_cmd {
785			pinmux = <MT8173_PIN_27_MSDC3_CMD__FUNC_MSDC3_CMD>;
786			input-enable;
787			drive-strength = <MTK_DRIVE_8mA>;
788			bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
789		};
790
791		pins_clk {
792			pinmux = <MT8173_PIN_26_MSDC3_CLK__FUNC_MSDC3_CLK>;
793			drive-strength = <MTK_DRIVE_8mA>;
794			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
795		};
796	};
797
798	nor_gpio1_pins: nor {
799		pins1 {
800			pinmux = <MT8173_PIN_6_EINT6__FUNC_SFCS0>,
801				 <MT8173_PIN_7_EINT7__FUNC_SFHOLD>,
802				 <MT8173_PIN_8_EINT8__FUNC_SFIN>;
803			input-enable;
804			drive-strength = <MTK_DRIVE_4mA>;
805			bias-pull-up;
806		};
807
808		pins2 {
809			pinmux = <MT8173_PIN_5_EINT5__FUNC_SFOUT>;
810			drive-strength = <MTK_DRIVE_4mA>;
811			bias-pull-up;
812		};
813
814		pins_clk {
815			pinmux = <MT8173_PIN_9_EINT9__FUNC_SFCK>;
816			input-enable;
817			drive-strength = <MTK_DRIVE_4mA>;
818			bias-pull-up;
819		};
820	};
821
822	panel_fixed_pins: panel_fixed_pins {
823		pins1 {
824			pinmux = <MT8173_PIN_41_CMMCLK__FUNC_GPIO41>;
825		};
826	};
827
828	ps8640_pins: ps8640_pins {
829		pins1 {
830			pinmux = <MT8173_PIN_92_PCM_CLK__FUNC_GPIO92>,
831				 <MT8173_PIN_115_URTS0__FUNC_GPIO115>,
832				 <MT8173_PIN_127_LCM_RST__FUNC_GPIO127>;
833		};
834	};
835
836	ps8640_fixed_pins: ps8640_fixed_pins {
837		pins1 {
838			pinmux = <MT8173_PIN_30_URTS2__FUNC_GPIO30>;
839		};
840	};
841
842	rt5650_irq: rt5650_irq {
843		pins1 {
844			pinmux = <MT8173_PIN_3_EINT3__FUNC_GPIO3>;
845			bias-pull-down;
846		};
847	};
848
849	sdio_fixed_3v3_pins: sdio_fixed_3v3_pins {
850		pins1 {
851			pinmux = <MT8173_PIN_85_AUD_DAT_MOSI__FUNC_GPIO85>;
852			output-low;
853		};
854	};
855
856	spi_pins_a: spi1 {
857		pins1 {
858			pinmux = <MT8173_PIN_0_EINT0__FUNC_GPIO0>;
859			bias-pull-up;
860		};
861
862		pins_spi {
863			pinmux = <MT8173_PIN_102_MSDC2_DAT2__FUNC_SPI_CK_1_>,
864				 <MT8173_PIN_103_MSDC2_DAT3__FUNC_SPI_MI_1_>,
865				 <MT8173_PIN_104_MSDC2_CLK__FUNC_SPI_MO_1_>,
866				 <MT8173_PIN_105_MSDC2_CMD__FUNC_SPI_CS_1_>;
867			bias-disable;
868		};
869	};
870
871	trackpad_irq: trackpad_irq {
872		pins1 {
873			pinmux = <MT8173_PIN_117_URXD3__FUNC_GPIO117>;
874			input-enable;
875			bias-pull-up;
876		};
877	};
878
879	usb_pins: usb {
880		pins1 {
881			pinmux = <MT8173_PIN_101_MSDC2_DAT1__FUNC_GPIO101>;
882			output-high;
883			bias-disable;
884		};
885	};
886
887	wifi_wake_pins: wifi_wake_pins {
888		pins1 {
889			pinmux = <MT8173_PIN_38_CONN_RST__FUNC_GPIO38>;
890			bias-pull-up;
891		};
892	};
893};
894
895&pwm0 {
896	status = "okay";
897};
898
899&pwrap {
900	pmic: mt6397 {
901		compatible = "mediatek,mt6397";
902		#address-cells = <1>;
903		#size-cells = <1>;
904		interrupt-parent = <&pio>;
905		interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
906		interrupt-controller;
907		#interrupt-cells = <2>;
908
909		clock: mt6397clock {
910			compatible = "mediatek,mt6397-clk";
911			#clock-cells = <1>;
912		};
913
914		pio6397: pinctrl {
915			compatible = "mediatek,mt6397-pinctrl";
916			pins-are-numbered;
917			gpio-controller;
918			#gpio-cells = <2>;
919		};
920
921		regulator: mt6397regulator {
922			compatible = "mediatek,mt6397-regulator";
923
924			mt6397_vpca15_reg: buck_vpca15 {
925				regulator-compatible = "buck_vpca15";
926				regulator-name = "vpca15";
927				regulator-min-microvolt = < 700000>;
928				regulator-max-microvolt = <1350000>;
929				regulator-ramp-delay = <12500>;
930				regulator-always-on;
931				regulator-allowed-modes = <0 1>;
932			};
933
934			mt6397_vpca7_reg: buck_vpca7 {
935				regulator-compatible = "buck_vpca7";
936				regulator-name = "vpca7";
937				regulator-min-microvolt = < 700000>;
938				regulator-max-microvolt = <1350000>;
939				regulator-ramp-delay = <12500>;
940				regulator-enable-ramp-delay = <115>;
941				regulator-always-on;
942			};
943
944			mt6397_vsramca15_reg: buck_vsramca15 {
945				regulator-compatible = "buck_vsramca15";
946				regulator-name = "vsramca15";
947				regulator-min-microvolt = < 700000>;
948				regulator-max-microvolt = <1350000>;
949				regulator-ramp-delay = <12500>;
950				regulator-always-on;
951			};
952
953			mt6397_vsramca7_reg: buck_vsramca7 {
954				regulator-compatible = "buck_vsramca7";
955				regulator-name = "vsramca7";
956				regulator-min-microvolt = < 700000>;
957				regulator-max-microvolt = <1350000>;
958				regulator-ramp-delay = <12500>;
959				regulator-always-on;
960			};
961
962			mt6397_vcore_reg: buck_vcore {
963				regulator-compatible = "buck_vcore";
964				regulator-name = "vcore";
965				regulator-min-microvolt = < 700000>;
966				regulator-max-microvolt = <1350000>;
967				regulator-ramp-delay = <12500>;
968				regulator-always-on;
969			};
970
971			mt6397_vgpu_reg: buck_vgpu {
972				regulator-compatible = "buck_vgpu";
973				regulator-name = "vgpu";
974				regulator-min-microvolt = < 700000>;
975				regulator-max-microvolt = <1350000>;
976				regulator-ramp-delay = <12500>;
977				regulator-enable-ramp-delay = <115>;
978			};
979
980			mt6397_vdrm_reg: buck_vdrm {
981				regulator-compatible = "buck_vdrm";
982				regulator-name = "vdrm";
983				regulator-min-microvolt = <1200000>;
984				regulator-max-microvolt = <1400000>;
985				regulator-ramp-delay = <12500>;
986				regulator-always-on;
987			};
988
989			mt6397_vio18_reg: buck_vio18 {
990				regulator-compatible = "buck_vio18";
991				regulator-name = "vio18";
992				regulator-min-microvolt = <1620000>;
993				regulator-max-microvolt = <1980000>;
994				regulator-ramp-delay = <12500>;
995				regulator-always-on;
996			};
997
998			mt6397_vtcxo_reg: ldo_vtcxo {
999				regulator-compatible = "ldo_vtcxo";
1000				regulator-name = "vtcxo";
1001				regulator-always-on;
1002			};
1003
1004			mt6397_va28_reg: ldo_va28 {
1005				regulator-compatible = "ldo_va28";
1006				regulator-name = "va28";
1007			};
1008
1009			mt6397_vcama_reg: ldo_vcama {
1010				regulator-compatible = "ldo_vcama";
1011				regulator-name = "vcama";
1012				regulator-min-microvolt = <1800000>;
1013				regulator-max-microvolt = <1800000>;
1014				regulator-enable-ramp-delay = <218>;
1015			};
1016
1017			mt6397_vio28_reg: ldo_vio28 {
1018				regulator-compatible = "ldo_vio28";
1019				regulator-name = "vio28";
1020				regulator-always-on;
1021			};
1022
1023			mt6397_vusb_reg: ldo_vusb {
1024				regulator-compatible = "ldo_vusb";
1025				regulator-name = "vusb";
1026			};
1027
1028			mt6397_vmc_reg: ldo_vmc {
1029				regulator-compatible = "ldo_vmc";
1030				regulator-name = "vmc";
1031				regulator-min-microvolt = <1800000>;
1032				regulator-max-microvolt = <3300000>;
1033				regulator-enable-ramp-delay = <218>;
1034			};
1035
1036			mt6397_vmch_reg: ldo_vmch {
1037				regulator-compatible = "ldo_vmch";
1038				regulator-name = "vmch";
1039				regulator-min-microvolt = <3000000>;
1040				regulator-max-microvolt = <3300000>;
1041				regulator-enable-ramp-delay = <218>;
1042			};
1043
1044			mt6397_vemc_3v3_reg: ldo_vemc3v3 {
1045				regulator-compatible = "ldo_vemc3v3";
1046				regulator-name = "vemc_3v3";
1047				regulator-min-microvolt = <3000000>;
1048				regulator-max-microvolt = <3300000>;
1049				regulator-enable-ramp-delay = <218>;
1050			};
1051
1052			mt6397_vgp1_reg: ldo_vgp1 {
1053				regulator-compatible = "ldo_vgp1";
1054				regulator-name = "vcamd";
1055				regulator-min-microvolt = <1800000>;
1056				regulator-max-microvolt = <1800000>;
1057				regulator-enable-ramp-delay = <240>;
1058			};
1059
1060			mt6397_vgp2_reg: ldo_vgp2 {
1061				regulator-compatible = "ldo_vgp2";
1062				regulator-name = "vcamio";
1063				regulator-min-microvolt = <3300000>;
1064				regulator-max-microvolt = <3300000>;
1065				regulator-enable-ramp-delay = <218>;
1066			};
1067
1068			mt6397_vgp3_reg: ldo_vgp3 {
1069				regulator-compatible = "ldo_vgp3";
1070				regulator-name = "vcamaf";
1071				regulator-min-microvolt = <1800000>;
1072				regulator-max-microvolt = <1800000>;
1073				regulator-enable-ramp-delay = <218>;
1074			};
1075
1076			mt6397_vgp4_reg: ldo_vgp4 {
1077				regulator-compatible = "ldo_vgp4";
1078				regulator-name = "vgp4";
1079				regulator-min-microvolt = <1200000>;
1080				regulator-max-microvolt = <3300000>;
1081				regulator-enable-ramp-delay = <218>;
1082			};
1083
1084			mt6397_vgp5_reg: ldo_vgp5 {
1085				regulator-compatible = "ldo_vgp5";
1086				regulator-name = "vgp5";
1087				regulator-min-microvolt = <1200000>;
1088				regulator-max-microvolt = <3000000>;
1089				regulator-enable-ramp-delay = <218>;
1090			};
1091
1092			mt6397_vgp6_reg: ldo_vgp6 {
1093				regulator-compatible = "ldo_vgp6";
1094				regulator-name = "vgp6";
1095				regulator-min-microvolt = <3300000>;
1096				regulator-max-microvolt = <3300000>;
1097				regulator-enable-ramp-delay = <218>;
1098				regulator-always-on;
1099			};
1100
1101			mt6397_vibr_reg: ldo_vibr {
1102				regulator-compatible = "ldo_vibr";
1103				regulator-name = "vibr";
1104				regulator-min-microvolt = <1300000>;
1105				regulator-max-microvolt = <3300000>;
1106				regulator-enable-ramp-delay = <218>;
1107			};
1108		};
1109
1110		rtc: mt6397rtc {
1111			compatible = "mediatek,mt6397-rtc";
1112		};
1113
1114		syscfg_pctl_pmic: syscfg_pctl_pmic@c000 {
1115			compatible = "mediatek,mt6397-pctl-pmic-syscfg",
1116				     "syscon";
1117			reg = <0 0x0000c000 0 0x0108>;
1118		};
1119	};
1120};
1121
1122&spi {
1123	pinctrl-names = "default";
1124	pinctrl-0 = <&spi_pins_a>;
1125	mediatek,pad-select = <1>;
1126	status = "okay";
1127	/* clients */
1128	cros_ec: ec@0 {
1129		compatible = "google,cros-ec-spi";
1130		reg = <0x0>;
1131		spi-max-frequency = <12000000>;
1132		interrupt-parent = <&pio>;
1133		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
1134		google,cros-ec-spi-msg-delay = <500>;
1135
1136		i2c_tunnel: i2c-tunnel0 {
1137			compatible = "google,cros-ec-i2c-tunnel";
1138			google,remote-bus = <0>;
1139			#address-cells = <1>;
1140			#size-cells = <0>;
1141
1142			battery: sbs-battery@b {
1143				compatible = "sbs,sbs-battery";
1144				reg = <0xb>;
1145				sbs,i2c-retry-count = <2>;
1146				sbs,poll-retry-count = <1>;
1147			};
1148		};
1149	};
1150};
1151
1152&ssusb {
1153	dr_mode = "host";
1154	wakeup-source;
1155	vusb33-supply = <&mt6397_vusb_reg>;
1156	status = "okay";
1157};
1158
1159&thermal {
1160	bank0-supply = <&mt6397_vpca15_reg>;
1161	bank1-supply = <&da9211_vcpu_reg>;
1162};
1163
1164&uart0 {
1165	status = "okay";
1166};
1167
1168&usb_host {
1169	pinctrl-names = "default";
1170	pinctrl-0 = <&usb_pins>;
1171	vusb33-supply = <&mt6397_vusb_reg>;
1172	status = "okay";
1173};
1174
1175#include <arm/cros-ec-keyboard.dtsi>
1176