1f40c0f80SSam Shih// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2f40c0f80SSam Shih/*
3f40c0f80SSam Shih * Copyright (C) 2021 MediaTek Inc.
4f40c0f80SSam Shih * Author: Sam.Shih <sam.shih@mediatek.com>
5f40c0f80SSam Shih */
6f40c0f80SSam Shih
7f40c0f80SSam Shih/dts-v1/;
8f40c0f80SSam Shih#include "mt7986b.dtsi"
9f40c0f80SSam Shih
10f40c0f80SSam Shih/ {
11f40c0f80SSam Shih	model = "MediaTek MT7986b RFB";
12f40c0f80SSam Shih	compatible = "mediatek,mt7986b-rfb";
13f40c0f80SSam Shih
14f40c0f80SSam Shih	aliases {
15f40c0f80SSam Shih		serial0 = &uart0;
16f40c0f80SSam Shih	};
17f40c0f80SSam Shih
18f40c0f80SSam Shih	chosen {
19f40c0f80SSam Shih		stdout-path = "serial0:115200n8";
20f40c0f80SSam Shih	};
21f40c0f80SSam Shih
22809967d7SSam Shih	memory@40000000 {
23809967d7SSam Shih		device_type = "memory";
24f40c0f80SSam Shih		reg = <0 0x40000000 0 0x40000000>;
25f40c0f80SSam Shih	};
26f40c0f80SSam Shih};
27f40c0f80SSam Shih
28082ff36bSLorenzo Bianconi&eth {
29082ff36bSLorenzo Bianconi	status = "okay";
30082ff36bSLorenzo Bianconi
31082ff36bSLorenzo Bianconi	gmac0: mac@0 {
32082ff36bSLorenzo Bianconi		compatible = "mediatek,eth-mac";
33082ff36bSLorenzo Bianconi		reg = <0>;
34082ff36bSLorenzo Bianconi		phy-mode = "2500base-x";
35082ff36bSLorenzo Bianconi
36082ff36bSLorenzo Bianconi		fixed-link {
37082ff36bSLorenzo Bianconi			speed = <2500>;
38082ff36bSLorenzo Bianconi			full-duplex;
39082ff36bSLorenzo Bianconi			pause;
40082ff36bSLorenzo Bianconi		};
41082ff36bSLorenzo Bianconi	};
42082ff36bSLorenzo Bianconi
43082ff36bSLorenzo Bianconi	mdio: mdio-bus {
44082ff36bSLorenzo Bianconi		#address-cells = <1>;
45082ff36bSLorenzo Bianconi		#size-cells = <0>;
46082ff36bSLorenzo Bianconi
47082ff36bSLorenzo Bianconi		switch@0 {
48082ff36bSLorenzo Bianconi			compatible = "mediatek,mt7531";
49082ff36bSLorenzo Bianconi			reg = <31>;
50082ff36bSLorenzo Bianconi			reset-gpios = <&pio 5 0>;
51082ff36bSLorenzo Bianconi
52082ff36bSLorenzo Bianconi			ports {
53082ff36bSLorenzo Bianconi				#address-cells = <1>;
54082ff36bSLorenzo Bianconi				#size-cells = <0>;
55082ff36bSLorenzo Bianconi
56082ff36bSLorenzo Bianconi				port@0 {
57082ff36bSLorenzo Bianconi					reg = <0>;
58082ff36bSLorenzo Bianconi					label = "lan0";
59082ff36bSLorenzo Bianconi				};
60082ff36bSLorenzo Bianconi
61082ff36bSLorenzo Bianconi				port@1 {
62082ff36bSLorenzo Bianconi					reg = <1>;
63082ff36bSLorenzo Bianconi					label = "lan1";
64082ff36bSLorenzo Bianconi				};
65082ff36bSLorenzo Bianconi
66082ff36bSLorenzo Bianconi				port@2 {
67082ff36bSLorenzo Bianconi					reg = <2>;
68082ff36bSLorenzo Bianconi					label = "lan2";
69082ff36bSLorenzo Bianconi				};
70082ff36bSLorenzo Bianconi
71082ff36bSLorenzo Bianconi				port@3 {
72082ff36bSLorenzo Bianconi					reg = <3>;
73082ff36bSLorenzo Bianconi					label = "lan3";
74082ff36bSLorenzo Bianconi				};
75082ff36bSLorenzo Bianconi
76082ff36bSLorenzo Bianconi				port@4 {
77082ff36bSLorenzo Bianconi					reg = <4>;
78082ff36bSLorenzo Bianconi					label = "lan4";
79082ff36bSLorenzo Bianconi				};
80082ff36bSLorenzo Bianconi
81082ff36bSLorenzo Bianconi				port@6 {
82082ff36bSLorenzo Bianconi					reg = <6>;
83082ff36bSLorenzo Bianconi					label = "cpu";
84082ff36bSLorenzo Bianconi					ethernet = <&gmac0>;
85082ff36bSLorenzo Bianconi					phy-mode = "2500base-x";
86082ff36bSLorenzo Bianconi
87082ff36bSLorenzo Bianconi					fixed-link {
88082ff36bSLorenzo Bianconi						speed = <2500>;
89082ff36bSLorenzo Bianconi						full-duplex;
90082ff36bSLorenzo Bianconi						pause;
91082ff36bSLorenzo Bianconi					};
92082ff36bSLorenzo Bianconi				};
93082ff36bSLorenzo Bianconi			};
94082ff36bSLorenzo Bianconi		};
95082ff36bSLorenzo Bianconi	};
96082ff36bSLorenzo Bianconi};
97300218b0SPeter Chiu
98300218b0SPeter Chiu&pio {
99300218b0SPeter Chiu	wf_2g_5g_pins: wf-2g-5g-pins {
100300218b0SPeter Chiu		mux {
101300218b0SPeter Chiu			function = "wifi";
102300218b0SPeter Chiu			groups = "wf_2g", "wf_5g";
103300218b0SPeter Chiu		};
104300218b0SPeter Chiu		conf {
105300218b0SPeter Chiu			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
106300218b0SPeter Chiu			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
107300218b0SPeter Chiu			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
108300218b0SPeter Chiu			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
109300218b0SPeter Chiu			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
110300218b0SPeter Chiu			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
111300218b0SPeter Chiu			       "WF1_TOP_CLK", "WF1_TOP_DATA";
112300218b0SPeter Chiu			drive-strength = <4>;
113300218b0SPeter Chiu		};
114300218b0SPeter Chiu	};
115300218b0SPeter Chiu
116300218b0SPeter Chiu	wf_dbdc_pins: wf-dbdc-pins {
117300218b0SPeter Chiu		mux {
118300218b0SPeter Chiu			function = "wifi";
119300218b0SPeter Chiu			groups = "wf_dbdc";
120300218b0SPeter Chiu		};
121300218b0SPeter Chiu		conf {
122300218b0SPeter Chiu			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
123300218b0SPeter Chiu			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
124300218b0SPeter Chiu			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
125300218b0SPeter Chiu			       "WF0_TOP_CLK", "WF0_TOP_DATA";
126300218b0SPeter Chiu			drive-strength = <4>;
127300218b0SPeter Chiu		};
128300218b0SPeter Chiu	};
129300218b0SPeter Chiu};
130*965f2c04SSam Shih
131*965f2c04SSam Shih&uart0 {
132*965f2c04SSam Shih	status = "okay";
133*965f2c04SSam Shih};
134*965f2c04SSam Shih
135*965f2c04SSam Shih&wifi {
136*965f2c04SSam Shih	status = "okay";
137*965f2c04SSam Shih	pinctrl-names = "default", "dbdc";
138*965f2c04SSam Shih	pinctrl-0 = <&wf_2g_5g_pins>;
139*965f2c04SSam Shih	pinctrl-1 = <&wf_dbdc_pins>;
140*965f2c04SSam Shih};
141