1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Authors: Sam.Shih <sam.shih@mediatek.com>
5 *          Frank Wunderlich <frank-w@public-files.de>
6 *          Daniel Golle <daniel@makrotopia.org>
7 */
8
9/dts-v1/;
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/input/input.h>
12#include <dt-bindings/leds/common.h>
13#include <dt-bindings/pinctrl/mt65xx.h>
14
15#include "mt7986a.dtsi"
16
17/ {
18	model = "Bananapi BPI-R3";
19	chassis-type = "embedded";
20	compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
21
22	aliases {
23		serial0 = &uart0;
24		ethernet0 = &gmac0;
25		ethernet1 = &gmac1;
26	};
27
28	chosen {
29		stdout-path = "serial0:115200n8";
30	};
31
32	dcin: regulator-12vd {
33		compatible = "regulator-fixed";
34		regulator-name = "12vd";
35		regulator-min-microvolt = <12000000>;
36		regulator-max-microvolt = <12000000>;
37		regulator-boot-on;
38		regulator-always-on;
39	};
40
41	gpio-keys {
42		compatible = "gpio-keys";
43
44		reset-key {
45			label = "reset";
46			linux,code = <KEY_RESTART>;
47			gpios = <&pio 9 GPIO_ACTIVE_LOW>;
48		};
49
50		wps-key {
51			label = "wps";
52			linux,code = <KEY_WPS_BUTTON>;
53			gpios = <&pio 10 GPIO_ACTIVE_LOW>;
54		};
55	};
56
57	/* i2c of the left SFP cage (wan) */
58	i2c_sfp1: i2c-gpio-0 {
59		compatible = "i2c-gpio";
60		sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
61		scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
62		i2c-gpio,delay-us = <2>;
63		#address-cells = <1>;
64		#size-cells = <0>;
65	};
66
67	/* i2c of the right SFP cage (lan) */
68	i2c_sfp2: i2c-gpio-1 {
69		compatible = "i2c-gpio";
70		sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
71		scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
72		i2c-gpio,delay-us = <2>;
73		#address-cells = <1>;
74		#size-cells = <0>;
75	};
76
77	leds {
78		compatible = "gpio-leds";
79
80		green_led: led-0 {
81			color = <LED_COLOR_ID_GREEN>;
82			function = LED_FUNCTION_POWER;
83			gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
84			default-state = "on";
85		};
86
87		blue_led: led-1 {
88			color = <LED_COLOR_ID_BLUE>;
89			function = LED_FUNCTION_STATUS;
90			gpios = <&pio 86 GPIO_ACTIVE_HIGH>;
91			default-state = "off";
92		};
93	};
94
95	reg_1p8v: regulator-1p8v {
96		compatible = "regulator-fixed";
97		regulator-name = "1.8vd";
98		regulator-min-microvolt = <1800000>;
99		regulator-max-microvolt = <1800000>;
100		regulator-boot-on;
101		regulator-always-on;
102		vin-supply = <&dcin>;
103	};
104
105	reg_3p3v: regulator-3p3v {
106		compatible = "regulator-fixed";
107		regulator-name = "3.3vd";
108		regulator-min-microvolt = <3300000>;
109		regulator-max-microvolt = <3300000>;
110		regulator-boot-on;
111		regulator-always-on;
112		vin-supply = <&dcin>;
113	};
114
115	/* left SFP cage (wan) */
116	sfp1: sfp-1 {
117		compatible = "sff,sfp";
118		i2c-bus = <&i2c_sfp1>;
119		los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
120		mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
121		tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
122		tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
123	};
124
125	/* right SFP cage (lan) */
126	sfp2: sfp-2 {
127		compatible = "sff,sfp";
128		i2c-bus = <&i2c_sfp2>;
129		los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
130		mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
131		tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
132		tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
133	};
134};
135
136&crypto {
137	status = "okay";
138};
139
140&eth {
141	status = "okay";
142
143	gmac0: mac@0 {
144		compatible = "mediatek,eth-mac";
145		reg = <0>;
146		phy-mode = "2500base-x";
147
148		fixed-link {
149			speed = <2500>;
150			full-duplex;
151			pause;
152		};
153	};
154
155	gmac1: mac@1 {
156		compatible = "mediatek,eth-mac";
157		reg = <1>;
158		phy-mode = "2500base-x";
159		sfp = <&sfp1>;
160		managed = "in-band-status";
161	};
162
163	mdio: mdio-bus {
164		#address-cells = <1>;
165		#size-cells = <0>;
166	};
167};
168
169&mdio {
170	switch: switch@31 {
171		compatible = "mediatek,mt7531";
172		reg = <31>;
173		interrupt-controller;
174		#interrupt-cells = <1>;
175		interrupt-parent = <&pio>;
176		interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
177		reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
178	};
179};
180
181&mmc0 {
182	pinctrl-names = "default", "state_uhs";
183	pinctrl-0 = <&mmc0_pins_default>;
184	pinctrl-1 = <&mmc0_pins_uhs>;
185	vmmc-supply = <&reg_3p3v>;
186	vqmmc-supply = <&reg_1p8v>;
187};
188
189&i2c0 {
190	pinctrl-names = "default";
191	pinctrl-0 = <&i2c_pins>;
192	status = "okay";
193};
194
195&pcie {
196	pinctrl-names = "default";
197	pinctrl-0 = <&pcie_pins>;
198	status = "okay";
199};
200
201&pcie_phy {
202	status = "okay";
203};
204
205&pio {
206	i2c_pins: i2c-pins {
207		mux {
208			function = "i2c";
209			groups = "i2c";
210		};
211	};
212
213	mmc0_pins_default: mmc0-pins {
214		mux {
215			function = "emmc";
216			groups = "emmc_51";
217		};
218		conf-cmd-dat {
219			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
220			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
221			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
222			input-enable;
223			drive-strength = <4>;
224			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
225		};
226		conf-clk {
227			pins = "EMMC_CK";
228			drive-strength = <6>;
229			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
230		};
231		conf-ds {
232			pins = "EMMC_DSL";
233			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
234		};
235		conf-rst {
236			pins = "EMMC_RSTB";
237			drive-strength = <4>;
238			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
239		};
240	};
241
242	mmc0_pins_uhs: mmc0-uhs-pins {
243		mux {
244			function = "emmc";
245			groups = "emmc_51";
246		};
247		conf-cmd-dat {
248			pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
249			       "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
250			       "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
251			input-enable;
252			drive-strength = <4>;
253			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
254		};
255		conf-clk {
256			pins = "EMMC_CK";
257			drive-strength = <6>;
258			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
259		};
260		conf-ds {
261			pins = "EMMC_DSL";
262			bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
263		};
264		conf-rst {
265			pins = "EMMC_RSTB";
266			drive-strength = <4>;
267			bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
268		};
269	};
270
271	pcie_pins: pcie-pins {
272		mux {
273			function = "pcie";
274			groups = "pcie_clk", "pcie_pereset";
275		};
276	};
277
278	pwm_pins: pwm-pins {
279		mux {
280			function = "pwm";
281			groups = "pwm0", "pwm1_0";
282		};
283	};
284
285	spi_flash_pins: spi-flash-pins {
286		mux {
287			function = "spi";
288			groups = "spi0", "spi0_wp_hold";
289		};
290	};
291
292	spic_pins: spic-pins {
293		mux {
294			function = "spi";
295			groups = "spi1_0";
296		};
297	};
298
299	uart1_pins: uart1-pins {
300		mux {
301			function = "uart";
302			groups = "uart1_rx_tx";
303		};
304	};
305
306	uart2_pins: uart2-pins {
307		mux {
308			function = "uart";
309			groups = "uart2_0_rx_tx";
310		};
311	};
312
313	wf_2g_5g_pins: wf-2g-5g-pins {
314		mux {
315			function = "wifi";
316			groups = "wf_2g", "wf_5g";
317		};
318		conf {
319			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
320			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
321			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
322			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
323			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
324			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
325			       "WF1_TOP_CLK", "WF1_TOP_DATA";
326			drive-strength = <4>;
327		};
328	};
329
330	wf_dbdc_pins: wf-dbdc-pins {
331		mux {
332			function = "wifi";
333			groups = "wf_dbdc";
334		};
335		conf {
336			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
337			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
338			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
339			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
340			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
341			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
342			       "WF1_TOP_CLK", "WF1_TOP_DATA";
343			drive-strength = <4>;
344		};
345	};
346
347	wf_led_pins: wf-led-pins {
348		mux {
349			function = "led";
350			groups = "wifi_led";
351		};
352	};
353};
354
355&pwm {
356	pinctrl-names = "default";
357	pinctrl-0 = <&pwm_pins>;
358	status = "okay";
359};
360
361&spi0 {
362	pinctrl-names = "default";
363	pinctrl-0 = <&spi_flash_pins>;
364	status = "okay";
365};
366
367&spi1 {
368	pinctrl-names = "default";
369	pinctrl-0 = <&spic_pins>;
370	status = "okay";
371};
372
373&ssusb {
374	status = "okay";
375};
376
377&switch {
378	ports {
379		#address-cells = <1>;
380		#size-cells = <0>;
381
382		port@0 {
383			reg = <0>;
384			label = "wan";
385		};
386
387		port@1 {
388			reg = <1>;
389			label = "lan0";
390		};
391
392		port@2 {
393			reg = <2>;
394			label = "lan1";
395		};
396
397		port@3 {
398			reg = <3>;
399			label = "lan2";
400		};
401
402		port@4 {
403			reg = <4>;
404			label = "lan3";
405		};
406
407		port5: port@5 {
408			reg = <5>;
409			label = "lan4";
410			phy-mode = "2500base-x";
411			sfp = <&sfp2>;
412			managed = "in-band-status";
413		};
414
415		port@6 {
416			reg = <6>;
417			label = "cpu";
418			ethernet = <&gmac0>;
419			phy-mode = "2500base-x";
420
421			fixed-link {
422				speed = <2500>;
423				full-duplex;
424				pause;
425			};
426		};
427	};
428};
429
430&trng {
431	status = "okay";
432};
433
434&uart0 {
435	status = "okay";
436};
437
438&uart1 {
439	pinctrl-names = "default";
440	pinctrl-0 = <&uart1_pins>;
441	status = "okay";
442};
443
444&uart2 {
445	pinctrl-names = "default";
446	pinctrl-0 = <&uart2_pins>;
447	status = "okay";
448};
449
450&usb_phy {
451	status = "okay";
452};
453
454&watchdog {
455	status = "okay";
456};
457
458&wifi {
459	status = "okay";
460	pinctrl-names = "default", "dbdc";
461	pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
462	pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
463};
464
465