1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 MediaTek Inc. 4 * Authors: Sam.Shih <sam.shih@mediatek.com> 5 * Frank Wunderlich <frank-w@public-files.de> 6 * Daniel Golle <daniel@makrotopia.org> 7 */ 8 9/dts-v1/; 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/input/input.h> 12#include <dt-bindings/leds/common.h> 13#include <dt-bindings/pinctrl/mt65xx.h> 14 15#include "mt7986a.dtsi" 16 17/ { 18 model = "Bananapi BPI-R3"; 19 chassis-type = "embedded"; 20 compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; 21 22 aliases { 23 serial0 = &uart0; 24 ethernet0 = &gmac0; 25 ethernet1 = &gmac1; 26 }; 27 28 chosen { 29 stdout-path = "serial0:115200n8"; 30 }; 31 32 dcin: regulator-12vd { 33 compatible = "regulator-fixed"; 34 regulator-name = "12vd"; 35 regulator-min-microvolt = <12000000>; 36 regulator-max-microvolt = <12000000>; 37 regulator-boot-on; 38 regulator-always-on; 39 }; 40 41 gpio-keys { 42 compatible = "gpio-keys"; 43 44 reset-key { 45 label = "reset"; 46 linux,code = <KEY_RESTART>; 47 gpios = <&pio 9 GPIO_ACTIVE_LOW>; 48 }; 49 50 wps-key { 51 label = "wps"; 52 linux,code = <KEY_WPS_BUTTON>; 53 gpios = <&pio 10 GPIO_ACTIVE_LOW>; 54 }; 55 }; 56 57 /* i2c of the left SFP cage (wan) */ 58 i2c_sfp1: i2c-gpio-0 { 59 compatible = "i2c-gpio"; 60 sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 61 scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 62 i2c-gpio,delay-us = <2>; 63 #address-cells = <1>; 64 #size-cells = <0>; 65 }; 66 67 /* i2c of the right SFP cage (lan) */ 68 i2c_sfp2: i2c-gpio-1 { 69 compatible = "i2c-gpio"; 70 sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 71 scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 72 i2c-gpio,delay-us = <2>; 73 #address-cells = <1>; 74 #size-cells = <0>; 75 }; 76 77 leds { 78 compatible = "gpio-leds"; 79 80 green_led: led-0 { 81 color = <LED_COLOR_ID_GREEN>; 82 function = LED_FUNCTION_POWER; 83 gpios = <&pio 69 GPIO_ACTIVE_HIGH>; 84 default-state = "on"; 85 }; 86 87 blue_led: led-1 { 88 color = <LED_COLOR_ID_BLUE>; 89 function = LED_FUNCTION_STATUS; 90 gpios = <&pio 86 GPIO_ACTIVE_HIGH>; 91 default-state = "off"; 92 }; 93 }; 94 95 reg_1p8v: regulator-1p8v { 96 compatible = "regulator-fixed"; 97 regulator-name = "1.8vd"; 98 regulator-min-microvolt = <1800000>; 99 regulator-max-microvolt = <1800000>; 100 regulator-boot-on; 101 regulator-always-on; 102 vin-supply = <&dcin>; 103 }; 104 105 reg_3p3v: regulator-3p3v { 106 compatible = "regulator-fixed"; 107 regulator-name = "3.3vd"; 108 regulator-min-microvolt = <3300000>; 109 regulator-max-microvolt = <3300000>; 110 regulator-boot-on; 111 regulator-always-on; 112 vin-supply = <&dcin>; 113 }; 114 115 /* left SFP cage (wan) */ 116 sfp1: sfp-1 { 117 compatible = "sff,sfp"; 118 i2c-bus = <&i2c_sfp1>; 119 los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>; 120 mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>; 121 tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>; 122 tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; 123 }; 124 125 /* right SFP cage (lan) */ 126 sfp2: sfp-2 { 127 compatible = "sff,sfp"; 128 i2c-bus = <&i2c_sfp2>; 129 los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>; 130 mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>; 131 tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>; 132 tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>; 133 }; 134}; 135 136&crypto { 137 status = "okay"; 138}; 139 140ð { 141 status = "okay"; 142 143 gmac0: mac@0 { 144 compatible = "mediatek,eth-mac"; 145 reg = <0>; 146 phy-mode = "2500base-x"; 147 148 fixed-link { 149 speed = <2500>; 150 full-duplex; 151 pause; 152 }; 153 }; 154 155 gmac1: mac@1 { 156 compatible = "mediatek,eth-mac"; 157 reg = <1>; 158 phy-mode = "2500base-x"; 159 sfp = <&sfp1>; 160 managed = "in-band-status"; 161 }; 162 163 mdio: mdio-bus { 164 #address-cells = <1>; 165 #size-cells = <0>; 166 }; 167}; 168 169&mdio { 170 switch: switch@31 { 171 compatible = "mediatek,mt7531"; 172 reg = <31>; 173 interrupt-controller; 174 #interrupt-cells = <1>; 175 interrupt-parent = <&pio>; 176 interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; 177 reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; 178 }; 179}; 180 181&mmc0 { 182 pinctrl-names = "default", "state_uhs"; 183 pinctrl-0 = <&mmc0_pins_default>; 184 pinctrl-1 = <&mmc0_pins_uhs>; 185 vmmc-supply = <®_3p3v>; 186 vqmmc-supply = <®_1p8v>; 187}; 188 189&i2c0 { 190 pinctrl-names = "default"; 191 pinctrl-0 = <&i2c_pins>; 192 status = "okay"; 193}; 194 195&pcie { 196 pinctrl-names = "default"; 197 pinctrl-0 = <&pcie_pins>; 198 status = "okay"; 199}; 200 201&pcie_phy { 202 status = "okay"; 203}; 204 205&pio { 206 i2c_pins: i2c-pins { 207 mux { 208 function = "i2c"; 209 groups = "i2c"; 210 }; 211 }; 212 213 mmc0_pins_default: mmc0-pins { 214 mux { 215 function = "emmc"; 216 groups = "emmc_51"; 217 }; 218 conf-cmd-dat { 219 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", 220 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", 221 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; 222 input-enable; 223 drive-strength = <4>; 224 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ 225 }; 226 conf-clk { 227 pins = "EMMC_CK"; 228 drive-strength = <6>; 229 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ 230 }; 231 conf-ds { 232 pins = "EMMC_DSL"; 233 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ 234 }; 235 conf-rst { 236 pins = "EMMC_RSTB"; 237 drive-strength = <4>; 238 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ 239 }; 240 }; 241 242 mmc0_pins_uhs: mmc0-uhs-pins { 243 mux { 244 function = "emmc"; 245 groups = "emmc_51"; 246 }; 247 conf-cmd-dat { 248 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", 249 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", 250 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; 251 input-enable; 252 drive-strength = <4>; 253 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ 254 }; 255 conf-clk { 256 pins = "EMMC_CK"; 257 drive-strength = <6>; 258 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ 259 }; 260 conf-ds { 261 pins = "EMMC_DSL"; 262 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ 263 }; 264 conf-rst { 265 pins = "EMMC_RSTB"; 266 drive-strength = <4>; 267 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ 268 }; 269 }; 270 271 pcie_pins: pcie-pins { 272 mux { 273 function = "pcie"; 274 groups = "pcie_clk", "pcie_pereset"; 275 }; 276 }; 277 278 spi_flash_pins: spi-flash-pins { 279 mux { 280 function = "spi"; 281 groups = "spi0", "spi0_wp_hold"; 282 }; 283 }; 284 285 spic_pins: spic-pins { 286 mux { 287 function = "spi"; 288 groups = "spi1_0"; 289 }; 290 }; 291 292 uart1_pins: uart1-pins { 293 mux { 294 function = "uart"; 295 groups = "uart1_rx_tx"; 296 }; 297 }; 298 299 uart2_pins: uart2-pins { 300 mux { 301 function = "uart"; 302 groups = "uart2_0_rx_tx"; 303 }; 304 }; 305 306 wf_2g_5g_pins: wf-2g-5g-pins { 307 mux { 308 function = "wifi"; 309 groups = "wf_2g", "wf_5g"; 310 }; 311 conf { 312 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", 313 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", 314 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", 315 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", 316 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", 317 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", 318 "WF1_TOP_CLK", "WF1_TOP_DATA"; 319 drive-strength = <4>; 320 }; 321 }; 322 323 wf_dbdc_pins: wf-dbdc-pins { 324 mux { 325 function = "wifi"; 326 groups = "wf_dbdc"; 327 }; 328 conf { 329 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", 330 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", 331 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", 332 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", 333 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", 334 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", 335 "WF1_TOP_CLK", "WF1_TOP_DATA"; 336 drive-strength = <4>; 337 }; 338 }; 339 340 wf_led_pins: wf-led-pins { 341 mux { 342 function = "led"; 343 groups = "wifi_led"; 344 }; 345 }; 346}; 347 348&spi0 { 349 pinctrl-names = "default"; 350 pinctrl-0 = <&spi_flash_pins>; 351 status = "okay"; 352}; 353 354&spi1 { 355 pinctrl-names = "default"; 356 pinctrl-0 = <&spic_pins>; 357 status = "okay"; 358}; 359 360&ssusb { 361 status = "okay"; 362}; 363 364&switch { 365 ports { 366 #address-cells = <1>; 367 #size-cells = <0>; 368 369 port@0 { 370 reg = <0>; 371 label = "wan"; 372 }; 373 374 port@1 { 375 reg = <1>; 376 label = "lan0"; 377 }; 378 379 port@2 { 380 reg = <2>; 381 label = "lan1"; 382 }; 383 384 port@3 { 385 reg = <3>; 386 label = "lan2"; 387 }; 388 389 port@4 { 390 reg = <4>; 391 label = "lan3"; 392 }; 393 394 port5: port@5 { 395 reg = <5>; 396 label = "lan4"; 397 phy-mode = "2500base-x"; 398 sfp = <&sfp2>; 399 managed = "in-band-status"; 400 }; 401 402 port@6 { 403 reg = <6>; 404 label = "cpu"; 405 ethernet = <&gmac0>; 406 phy-mode = "2500base-x"; 407 408 fixed-link { 409 speed = <2500>; 410 full-duplex; 411 pause; 412 }; 413 }; 414 }; 415}; 416 417&trng { 418 status = "okay"; 419}; 420 421&uart0 { 422 status = "okay"; 423}; 424 425&uart1 { 426 pinctrl-names = "default"; 427 pinctrl-0 = <&uart1_pins>; 428 status = "okay"; 429}; 430 431&uart2 { 432 pinctrl-names = "default"; 433 pinctrl-0 = <&uart2_pins>; 434 status = "okay"; 435}; 436 437&usb_phy { 438 status = "okay"; 439}; 440 441&watchdog { 442 status = "okay"; 443}; 444 445&wifi { 446 status = "okay"; 447 pinctrl-names = "default", "dbdc"; 448 pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>; 449 pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>; 450}; 451 452