1*8e01fb15SFrank Wunderlich// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2*8e01fb15SFrank Wunderlich/* 3*8e01fb15SFrank Wunderlich * Copyright (C) 2021 MediaTek Inc. 4*8e01fb15SFrank Wunderlich * Author: Sam.Shih <sam.shih@mediatek.com> 5*8e01fb15SFrank Wunderlich */ 6*8e01fb15SFrank Wunderlich 7*8e01fb15SFrank Wunderlich/dts-v1/; 8*8e01fb15SFrank Wunderlich/plugin/; 9*8e01fb15SFrank Wunderlich 10*8e01fb15SFrank Wunderlich/ { 11*8e01fb15SFrank Wunderlich compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; 12*8e01fb15SFrank Wunderlich 13*8e01fb15SFrank Wunderlich fragment@0 { 14*8e01fb15SFrank Wunderlich target-path = "/soc/mmc@11230000"; 15*8e01fb15SFrank Wunderlich __overlay__ { 16*8e01fb15SFrank Wunderlich bus-width = <8>; 17*8e01fb15SFrank Wunderlich max-frequency = <200000000>; 18*8e01fb15SFrank Wunderlich cap-mmc-highspeed; 19*8e01fb15SFrank Wunderlich mmc-hs200-1_8v; 20*8e01fb15SFrank Wunderlich mmc-hs400-1_8v; 21*8e01fb15SFrank Wunderlich hs400-ds-delay = <0x14014>; 22*8e01fb15SFrank Wunderlich non-removable; 23*8e01fb15SFrank Wunderlich no-sd; 24*8e01fb15SFrank Wunderlich no-sdio; 25*8e01fb15SFrank Wunderlich status = "okay"; 26*8e01fb15SFrank Wunderlich }; 27*8e01fb15SFrank Wunderlich }; 28*8e01fb15SFrank Wunderlich}; 29*8e01fb15SFrank Wunderlich 30