1/* 2 * Copyright (c) 2017 MediaTek Inc. 3 * Author: Ming Huang <ming.huang@mediatek.com> 4 * Sean Wang <sean.wang@mediatek.com> 5 * 6 * SPDX-License-Identifier: (GPL-2.0 OR MIT) 7 */ 8 9/dts-v1/; 10#include <dt-bindings/input/input.h> 11 12#include "mt7622.dtsi" 13#include "mt6380.dtsi" 14 15/ { 16 model = "MediaTek MT7622 RFB1 board"; 17 compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622"; 18 19 chosen { 20 bootargs = "console=ttyS0,115200n1"; 21 }; 22 23 gpio-keys { 24 compatible = "gpio-keys-polled"; 25 poll-interval = <100>; 26 27 factory { 28 label = "factory"; 29 linux,code = <BTN_0>; 30 gpios = <&pio 0 0>; 31 }; 32 33 wps { 34 label = "wps"; 35 linux,code = <KEY_WPS_BUTTON>; 36 gpios = <&pio 102 0>; 37 }; 38 }; 39 40 memory { 41 reg = <0 0x40000000 0 0x3F000000>; 42 }; 43}; 44 45&pio { 46 /* eMMC is shared pin with parallel NAND */ 47 emmc_pins_default: emmc-pins-default { 48 mux { 49 function = "emmc", "emmc_rst"; 50 groups = "emmc"; 51 }; 52 }; 53 54 emmc_pins_uhs: emmc-pins-uhs { 55 mux { 56 function = "emmc"; 57 groups = "emmc"; 58 }; 59 }; 60 61 eth_pins: eth-pins { 62 mux { 63 function = "eth"; 64 groups = "mdc_mdio", "rgmii_via_gmac2"; 65 }; 66 }; 67 68 i2c1_pins: i2c1-pins { 69 mux { 70 function = "i2c"; 71 groups = "i2c1_0"; 72 }; 73 }; 74 75 i2c2_pins: i2c2-pins { 76 mux { 77 function = "i2c"; 78 groups = "i2c2_0"; 79 }; 80 }; 81 82 i2s1_pins: i2s1-pins { 83 mux { 84 function = "i2s"; 85 groups = "i2s_out_bclk_ws_mclk", 86 "i2s1_in_data", 87 "i2s1_out_data"; 88 }; 89 }; 90 91 irrx_pins: irrx-pins { 92 mux { 93 function = "ir"; 94 groups = "ir_1_rx"; 95 }; 96 }; 97 98 irtx_pins: irtx-pins { 99 mux { 100 function = "ir"; 101 groups = "ir_1_tx"; 102 }; 103 }; 104 105 /* Parallel nand is shared pin with eMMC */ 106 parallel_nand_pins: parallel-nand-pins { 107 mux { 108 function = "flash"; 109 groups = "par_nand"; 110 }; 111 }; 112 113 pcie0_pins: pcie0-pins { 114 mux { 115 function = "pcie"; 116 groups = "pcie0_pad_perst", 117 "pcie0_1_waken", 118 "pcie0_1_clkreq"; 119 }; 120 }; 121 122 pcie1_pins: pcie1-pins { 123 mux { 124 function = "pcie"; 125 groups = "pcie1_pad_perst", 126 "pcie1_0_waken", 127 "pcie1_0_clkreq"; 128 }; 129 }; 130 131 pmic_bus_pins: pmic-bus-pins { 132 mux { 133 function = "pmic"; 134 groups = "pmic_bus"; 135 }; 136 }; 137 138 pwm7_pins: pwm1-2-pins { 139 mux { 140 function = "pwm"; 141 groups = "pwm_ch7_2"; 142 }; 143 }; 144 145 wled_pins: wled-pins { 146 mux { 147 function = "led"; 148 groups = "wled"; 149 }; 150 }; 151 152 sd0_pins_default: sd0-pins-default { 153 mux { 154 function = "sd"; 155 groups = "sd_0"; 156 }; 157 }; 158 159 sd0_pins_uhs: sd0-pins-uhs { 160 mux { 161 function = "sd"; 162 groups = "sd_0"; 163 }; 164 }; 165 166 /* Serial NAND is shared pin with SPI-NOR */ 167 serial_nand_pins: serial-nand-pins { 168 mux { 169 function = "flash"; 170 groups = "snfi"; 171 }; 172 }; 173 174 spic0_pins: spic0-pins { 175 mux { 176 function = "spi"; 177 groups = "spic0_0"; 178 }; 179 }; 180 181 spic1_pins: spic1-pins { 182 mux { 183 function = "spi"; 184 groups = "spic1_0"; 185 }; 186 }; 187 188 /* SPI-NOR is shared pin with serial NAND */ 189 spi_nor_pins: spi-nor-pins { 190 mux { 191 function = "flash"; 192 groups = "spi_nor"; 193 }; 194 }; 195 196 /* serial NAND is shared pin with SPI-NOR */ 197 serial_nand_pins: serial-nand-pins { 198 mux { 199 function = "flash"; 200 groups = "snfi"; 201 }; 202 }; 203 204 uart0_pins: uart0-pins { 205 mux { 206 function = "uart"; 207 groups = "uart0_0_tx_rx" ; 208 }; 209 }; 210 211 uart2_pins: uart2-pins { 212 mux { 213 function = "uart"; 214 groups = "uart2_1_tx_rx" ; 215 }; 216 }; 217 218 watchdog_pins: watchdog-pins { 219 mux { 220 function = "watchdog"; 221 groups = "watchdog"; 222 }; 223 }; 224}; 225 226&pwrap { 227 pinctrl-names = "default"; 228 pinctrl-0 = <&pmic_bus_pins>; 229 230 status = "okay"; 231}; 232 233&uart0 { 234 status = "okay"; 235}; 236