1/* 2 * Copyright (c) 2017 MediaTek Inc. 3 * Author: Ming Huang <ming.huang@mediatek.com> 4 * Sean Wang <sean.wang@mediatek.com> 5 * 6 * SPDX-License-Identifier: (GPL-2.0 OR MIT) 7 */ 8 9/dts-v1/; 10#include <dt-bindings/input/input.h> 11 12#include "mt7622.dtsi" 13#include "mt6380.dtsi" 14 15/ { 16 model = "MediaTek MT7622 RFB1 board"; 17 compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622"; 18 19 chosen { 20 bootargs = "console=ttyS0,115200n1"; 21 }; 22 23 cpus { 24 cpu@0 { 25 proc-supply = <&mt6380_vcpu_reg>; 26 sram-supply = <&mt6380_vm_reg>; 27 }; 28 29 cpu@1 { 30 proc-supply = <&mt6380_vcpu_reg>; 31 sram-supply = <&mt6380_vm_reg>; 32 }; 33 }; 34 35 gpio-keys { 36 compatible = "gpio-keys-polled"; 37 poll-interval = <100>; 38 39 factory { 40 label = "factory"; 41 linux,code = <BTN_0>; 42 gpios = <&pio 0 0>; 43 }; 44 45 wps { 46 label = "wps"; 47 linux,code = <KEY_WPS_BUTTON>; 48 gpios = <&pio 102 0>; 49 }; 50 }; 51 52 memory { 53 reg = <0 0x40000000 0 0x3F000000>; 54 }; 55}; 56 57&pio { 58 /* eMMC is shared pin with parallel NAND */ 59 emmc_pins_default: emmc-pins-default { 60 mux { 61 function = "emmc", "emmc_rst"; 62 groups = "emmc"; 63 }; 64 }; 65 66 emmc_pins_uhs: emmc-pins-uhs { 67 mux { 68 function = "emmc"; 69 groups = "emmc"; 70 }; 71 }; 72 73 eth_pins: eth-pins { 74 mux { 75 function = "eth"; 76 groups = "mdc_mdio", "rgmii_via_gmac2"; 77 }; 78 }; 79 80 i2c1_pins: i2c1-pins { 81 mux { 82 function = "i2c"; 83 groups = "i2c1_0"; 84 }; 85 }; 86 87 i2c2_pins: i2c2-pins { 88 mux { 89 function = "i2c"; 90 groups = "i2c2_0"; 91 }; 92 }; 93 94 i2s1_pins: i2s1-pins { 95 mux { 96 function = "i2s"; 97 groups = "i2s_out_bclk_ws_mclk", 98 "i2s1_in_data", 99 "i2s1_out_data"; 100 }; 101 }; 102 103 irrx_pins: irrx-pins { 104 mux { 105 function = "ir"; 106 groups = "ir_1_rx"; 107 }; 108 }; 109 110 irtx_pins: irtx-pins { 111 mux { 112 function = "ir"; 113 groups = "ir_1_tx"; 114 }; 115 }; 116 117 /* Parallel nand is shared pin with eMMC */ 118 parallel_nand_pins: parallel-nand-pins { 119 mux { 120 function = "flash"; 121 groups = "par_nand"; 122 }; 123 }; 124 125 pcie0_pins: pcie0-pins { 126 mux { 127 function = "pcie"; 128 groups = "pcie0_pad_perst", 129 "pcie0_1_waken", 130 "pcie0_1_clkreq"; 131 }; 132 }; 133 134 pcie1_pins: pcie1-pins { 135 mux { 136 function = "pcie"; 137 groups = "pcie1_pad_perst", 138 "pcie1_0_waken", 139 "pcie1_0_clkreq"; 140 }; 141 }; 142 143 pmic_bus_pins: pmic-bus-pins { 144 mux { 145 function = "pmic"; 146 groups = "pmic_bus"; 147 }; 148 }; 149 150 pwm7_pins: pwm1-2-pins { 151 mux { 152 function = "pwm"; 153 groups = "pwm_ch7_2"; 154 }; 155 }; 156 157 wled_pins: wled-pins { 158 mux { 159 function = "led"; 160 groups = "wled"; 161 }; 162 }; 163 164 sd0_pins_default: sd0-pins-default { 165 mux { 166 function = "sd"; 167 groups = "sd_0"; 168 }; 169 }; 170 171 sd0_pins_uhs: sd0-pins-uhs { 172 mux { 173 function = "sd"; 174 groups = "sd_0"; 175 }; 176 }; 177 178 /* Serial NAND is shared pin with SPI-NOR */ 179 serial_nand_pins: serial-nand-pins { 180 mux { 181 function = "flash"; 182 groups = "snfi"; 183 }; 184 }; 185 186 spic0_pins: spic0-pins { 187 mux { 188 function = "spi"; 189 groups = "spic0_0"; 190 }; 191 }; 192 193 spic1_pins: spic1-pins { 194 mux { 195 function = "spi"; 196 groups = "spic1_0"; 197 }; 198 }; 199 200 /* SPI-NOR is shared pin with serial NAND */ 201 spi_nor_pins: spi-nor-pins { 202 mux { 203 function = "flash"; 204 groups = "spi_nor"; 205 }; 206 }; 207 208 /* serial NAND is shared pin with SPI-NOR */ 209 serial_nand_pins: serial-nand-pins { 210 mux { 211 function = "flash"; 212 groups = "snfi"; 213 }; 214 }; 215 216 uart0_pins: uart0-pins { 217 mux { 218 function = "uart"; 219 groups = "uart0_0_tx_rx" ; 220 }; 221 }; 222 223 uart2_pins: uart2-pins { 224 mux { 225 function = "uart"; 226 groups = "uart2_1_tx_rx" ; 227 }; 228 }; 229 230 watchdog_pins: watchdog-pins { 231 mux { 232 function = "watchdog"; 233 groups = "watchdog"; 234 }; 235 }; 236}; 237 238&bch { 239 status = "disabled"; 240}; 241 242&btif { 243 status = "okay"; 244}; 245 246&cir { 247 pinctrl-names = "default"; 248 pinctrl-0 = <&irrx_pins>; 249 status = "okay"; 250}; 251 252ð { 253 pinctrl-names = "default"; 254 pinctrl-0 = <ð_pins>; 255 status = "okay"; 256 257 gmac1: mac@1 { 258 compatible = "mediatek,eth-mac"; 259 reg = <1>; 260 phy-handle = <&phy5>; 261 }; 262 263 mdio-bus { 264 #address-cells = <1>; 265 #size-cells = <0>; 266 267 phy5: ethernet-phy@5 { 268 reg = <5>; 269 phy-mode = "sgmii"; 270 }; 271 }; 272}; 273 274&i2c1 { 275 pinctrl-names = "default"; 276 pinctrl-0 = <&i2c1_pins>; 277 status = "okay"; 278}; 279 280&i2c2 { 281 pinctrl-names = "default"; 282 pinctrl-0 = <&i2c2_pins>; 283 status = "okay"; 284}; 285 286&nandc { 287 pinctrl-names = "default"; 288 pinctrl-0 = <¶llel_nand_pins>; 289 status = "disabled"; 290}; 291 292&nor_flash { 293 pinctrl-names = "default"; 294 pinctrl-0 = <&spi_nor_pins>; 295 status = "disabled"; 296 297 flash@0 { 298 compatible = "jedec,spi-nor"; 299 reg = <0>; 300 }; 301}; 302 303&pwm { 304 pinctrl-names = "default"; 305 pinctrl-0 = <&pwm7_pins>; 306 status = "okay"; 307}; 308 309&pwrap { 310 pinctrl-names = "default"; 311 pinctrl-0 = <&pmic_bus_pins>; 312 313 status = "okay"; 314}; 315 316&spi0 { 317 pinctrl-names = "default"; 318 pinctrl-0 = <&spic0_pins>; 319 status = "okay"; 320}; 321 322&spi1 { 323 pinctrl-names = "default"; 324 pinctrl-0 = <&spic1_pins>; 325 status = "okay"; 326}; 327 328&uart0 { 329 pinctrl-names = "default"; 330 pinctrl-0 = <&uart0_pins>; 331 status = "okay"; 332}; 333 334&uart2 { 335 pinctrl-names = "default"; 336 pinctrl-0 = <&uart2_pins>; 337 status = "okay"; 338}; 339 340&watchdog { 341 pinctrl-names = "default"; 342 pinctrl-0 = <&watchdog_pins>; 343 status = "okay"; 344}; 345