1/* 2 * Copyright (c) 2017 MediaTek Inc. 3 * Author: Ming Huang <ming.huang@mediatek.com> 4 * Sean Wang <sean.wang@mediatek.com> 5 * 6 * SPDX-License-Identifier: (GPL-2.0 OR MIT) 7 */ 8 9/dts-v1/; 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/gpio/gpio.h> 12 13#include "mt7622.dtsi" 14#include "mt6380.dtsi" 15 16/ { 17 model = "MediaTek MT7622 RFB1 board"; 18 compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622"; 19 20 chosen { 21 bootargs = "console=ttyS0,115200n1"; 22 }; 23 24 cpus { 25 cpu@0 { 26 proc-supply = <&mt6380_vcpu_reg>; 27 sram-supply = <&mt6380_vm_reg>; 28 }; 29 30 cpu@1 { 31 proc-supply = <&mt6380_vcpu_reg>; 32 sram-supply = <&mt6380_vm_reg>; 33 }; 34 }; 35 36 gpio-keys { 37 compatible = "gpio-keys-polled"; 38 poll-interval = <100>; 39 40 factory { 41 label = "factory"; 42 linux,code = <BTN_0>; 43 gpios = <&pio 0 0>; 44 }; 45 46 wps { 47 label = "wps"; 48 linux,code = <KEY_WPS_BUTTON>; 49 gpios = <&pio 102 0>; 50 }; 51 }; 52 53 memory { 54 reg = <0 0x40000000 0 0x3F000000>; 55 }; 56 57 reg_1p8v: regulator-1p8v { 58 compatible = "regulator-fixed"; 59 regulator-name = "fixed-1.8V"; 60 regulator-min-microvolt = <1800000>; 61 regulator-max-microvolt = <1800000>; 62 regulator-always-on; 63 }; 64 65 reg_3p3v: regulator-3p3v { 66 compatible = "regulator-fixed"; 67 regulator-name = "fixed-3.3V"; 68 regulator-min-microvolt = <3300000>; 69 regulator-max-microvolt = <3300000>; 70 regulator-boot-on; 71 regulator-always-on; 72 }; 73 74 reg_5v: regulator-5v { 75 compatible = "regulator-fixed"; 76 regulator-name = "fixed-5V"; 77 regulator-min-microvolt = <5000000>; 78 regulator-max-microvolt = <5000000>; 79 regulator-boot-on; 80 regulator-always-on; 81 }; 82}; 83 84&pcie { 85 pinctrl-names = "default"; 86 pinctrl-0 = <&pcie0_pins>; 87 status = "okay"; 88 89 pcie@0,0 { 90 status = "okay"; 91 }; 92}; 93 94&pio { 95 /* eMMC is shared pin with parallel NAND */ 96 emmc_pins_default: emmc-pins-default { 97 mux { 98 function = "emmc", "emmc_rst"; 99 groups = "emmc"; 100 }; 101 102 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7", 103 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4, 104 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively 105 */ 106 conf-cmd-dat { 107 pins = "NDL0", "NDL1", "NDL2", 108 "NDL3", "NDL4", "NDL5", 109 "NDL6", "NDL7", "NRB"; 110 input-enable; 111 bias-pull-up; 112 }; 113 114 conf-clk { 115 pins = "NCLE"; 116 bias-pull-down; 117 }; 118 }; 119 120 emmc_pins_uhs: emmc-pins-uhs { 121 mux { 122 function = "emmc"; 123 groups = "emmc"; 124 }; 125 126 conf-cmd-dat { 127 pins = "NDL0", "NDL1", "NDL2", 128 "NDL3", "NDL4", "NDL5", 129 "NDL6", "NDL7", "NRB"; 130 input-enable; 131 drive-strength = <4>; 132 bias-pull-up; 133 }; 134 135 conf-clk { 136 pins = "NCLE"; 137 drive-strength = <4>; 138 bias-pull-down; 139 }; 140 }; 141 142 eth_pins: eth-pins { 143 mux { 144 function = "eth"; 145 groups = "mdc_mdio", "rgmii_via_gmac2"; 146 }; 147 }; 148 149 i2c1_pins: i2c1-pins { 150 mux { 151 function = "i2c"; 152 groups = "i2c1_0"; 153 }; 154 }; 155 156 i2c2_pins: i2c2-pins { 157 mux { 158 function = "i2c"; 159 groups = "i2c2_0"; 160 }; 161 }; 162 163 i2s1_pins: i2s1-pins { 164 mux { 165 function = "i2s"; 166 groups = "i2s_out_bclk_ws_mclk", 167 "i2s1_in_data", 168 "i2s1_out_data"; 169 }; 170 }; 171 172 irrx_pins: irrx-pins { 173 mux { 174 function = "ir"; 175 groups = "ir_1_rx"; 176 }; 177 }; 178 179 irtx_pins: irtx-pins { 180 mux { 181 function = "ir"; 182 groups = "ir_1_tx"; 183 }; 184 }; 185 186 /* Parallel nand is shared pin with eMMC */ 187 parallel_nand_pins: parallel-nand-pins { 188 mux { 189 function = "flash"; 190 groups = "par_nand"; 191 }; 192 }; 193 194 pcie0_pins: pcie0-pins { 195 mux { 196 function = "pcie"; 197 groups = "pcie0_pad_perst", 198 "pcie0_1_waken", 199 "pcie0_1_clkreq"; 200 }; 201 }; 202 203 pcie1_pins: pcie1-pins { 204 mux { 205 function = "pcie"; 206 groups = "pcie1_pad_perst", 207 "pcie1_0_waken", 208 "pcie1_0_clkreq"; 209 }; 210 }; 211 212 pmic_bus_pins: pmic-bus-pins { 213 mux { 214 function = "pmic"; 215 groups = "pmic_bus"; 216 }; 217 }; 218 219 pwm7_pins: pwm1-2-pins { 220 mux { 221 function = "pwm"; 222 groups = "pwm_ch7_2"; 223 }; 224 }; 225 226 wled_pins: wled-pins { 227 mux { 228 function = "led"; 229 groups = "wled"; 230 }; 231 }; 232 233 sd0_pins_default: sd0-pins-default { 234 mux { 235 function = "sd"; 236 groups = "sd_0"; 237 }; 238 239 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN", 240 * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1, 241 * DAT2, DAT3, CMD, CLK for SD respectively. 242 */ 243 conf-cmd-data { 244 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", 245 "I2S2_IN","I2S4_OUT"; 246 input-enable; 247 drive-strength = <8>; 248 bias-pull-up; 249 }; 250 conf-clk { 251 pins = "I2S3_OUT"; 252 drive-strength = <12>; 253 bias-pull-down; 254 }; 255 conf-cd { 256 pins = "TXD3"; 257 bias-pull-up; 258 }; 259 }; 260 261 sd0_pins_uhs: sd0-pins-uhs { 262 mux { 263 function = "sd"; 264 groups = "sd_0"; 265 }; 266 267 conf-cmd-data { 268 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", 269 "I2S2_IN","I2S4_OUT"; 270 input-enable; 271 bias-pull-up; 272 }; 273 274 conf-clk { 275 pins = "I2S3_OUT"; 276 bias-pull-down; 277 }; 278 }; 279 280 /* Serial NAND is shared pin with SPI-NOR */ 281 serial_nand_pins: serial-nand-pins { 282 mux { 283 function = "flash"; 284 groups = "snfi"; 285 }; 286 }; 287 288 spic0_pins: spic0-pins { 289 mux { 290 function = "spi"; 291 groups = "spic0_0"; 292 }; 293 }; 294 295 spic1_pins: spic1-pins { 296 mux { 297 function = "spi"; 298 groups = "spic1_0"; 299 }; 300 }; 301 302 /* SPI-NOR is shared pin with serial NAND */ 303 spi_nor_pins: spi-nor-pins { 304 mux { 305 function = "flash"; 306 groups = "spi_nor"; 307 }; 308 }; 309 310 /* serial NAND is shared pin with SPI-NOR */ 311 serial_nand_pins: serial-nand-pins { 312 mux { 313 function = "flash"; 314 groups = "snfi"; 315 }; 316 }; 317 318 uart0_pins: uart0-pins { 319 mux { 320 function = "uart"; 321 groups = "uart0_0_tx_rx" ; 322 }; 323 }; 324 325 uart2_pins: uart2-pins { 326 mux { 327 function = "uart"; 328 groups = "uart2_1_tx_rx" ; 329 }; 330 }; 331 332 watchdog_pins: watchdog-pins { 333 mux { 334 function = "watchdog"; 335 groups = "watchdog"; 336 }; 337 }; 338}; 339 340&bch { 341 status = "disabled"; 342}; 343 344&btif { 345 status = "okay"; 346}; 347 348&cir { 349 pinctrl-names = "default"; 350 pinctrl-0 = <&irrx_pins>; 351 status = "okay"; 352}; 353 354ð { 355 pinctrl-names = "default"; 356 pinctrl-0 = <ð_pins>; 357 status = "okay"; 358 359 gmac1: mac@1 { 360 compatible = "mediatek,eth-mac"; 361 reg = <1>; 362 phy-handle = <&phy5>; 363 }; 364 365 mdio-bus { 366 #address-cells = <1>; 367 #size-cells = <0>; 368 369 phy5: ethernet-phy@5 { 370 reg = <5>; 371 phy-mode = "sgmii"; 372 }; 373 }; 374}; 375 376&i2c1 { 377 pinctrl-names = "default"; 378 pinctrl-0 = <&i2c1_pins>; 379 status = "okay"; 380}; 381 382&i2c2 { 383 pinctrl-names = "default"; 384 pinctrl-0 = <&i2c2_pins>; 385 status = "okay"; 386}; 387 388&mmc0 { 389 pinctrl-names = "default", "state_uhs"; 390 pinctrl-0 = <&emmc_pins_default>; 391 pinctrl-1 = <&emmc_pins_uhs>; 392 status = "okay"; 393 bus-width = <8>; 394 max-frequency = <50000000>; 395 cap-mmc-highspeed; 396 mmc-hs200-1_8v; 397 vmmc-supply = <®_3p3v>; 398 vqmmc-supply = <®_1p8v>; 399 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>; 400 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; 401 non-removable; 402}; 403 404&mmc1 { 405 pinctrl-names = "default", "state_uhs"; 406 pinctrl-0 = <&sd0_pins_default>; 407 pinctrl-1 = <&sd0_pins_uhs>; 408 status = "okay"; 409 bus-width = <4>; 410 max-frequency = <50000000>; 411 cap-sd-highspeed; 412 r_smpl = <1>; 413 cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>; 414 vmmc-supply = <®_3p3v>; 415 vqmmc-supply = <®_3p3v>; 416 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>; 417 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; 418}; 419 420&nandc { 421 pinctrl-names = "default"; 422 pinctrl-0 = <¶llel_nand_pins>; 423 status = "disabled"; 424}; 425 426&nor_flash { 427 pinctrl-names = "default"; 428 pinctrl-0 = <&spi_nor_pins>; 429 status = "disabled"; 430 431 flash@0 { 432 compatible = "jedec,spi-nor"; 433 reg = <0>; 434 }; 435}; 436 437&pwm { 438 pinctrl-names = "default"; 439 pinctrl-0 = <&pwm7_pins>; 440 status = "okay"; 441}; 442 443&pwrap { 444 pinctrl-names = "default"; 445 pinctrl-0 = <&pmic_bus_pins>; 446 447 status = "okay"; 448}; 449 450&sata { 451 status = "okay"; 452}; 453 454&sata_phy { 455 status = "okay"; 456}; 457 458&spi0 { 459 pinctrl-names = "default"; 460 pinctrl-0 = <&spic0_pins>; 461 status = "okay"; 462}; 463 464&spi1 { 465 pinctrl-names = "default"; 466 pinctrl-0 = <&spic1_pins>; 467 status = "okay"; 468}; 469 470&ssusb { 471 vusb33-supply = <®_3p3v>; 472 vbus-supply = <®_5v>; 473 status = "okay"; 474}; 475 476&u3phy { 477 status = "okay"; 478}; 479 480&uart0 { 481 pinctrl-names = "default"; 482 pinctrl-0 = <&uart0_pins>; 483 status = "okay"; 484}; 485 486&uart2 { 487 pinctrl-names = "default"; 488 pinctrl-0 = <&uart2_pins>; 489 status = "okay"; 490}; 491 492&watchdog { 493 pinctrl-names = "default"; 494 pinctrl-0 = <&watchdog_pins>; 495 status = "okay"; 496}; 497