1/* 2 * Copyright (c) 2017 MediaTek Inc. 3 * Author: Ming Huang <ming.huang@mediatek.com> 4 * Sean Wang <sean.wang@mediatek.com> 5 * 6 * SPDX-License-Identifier: (GPL-2.0 OR MIT) 7 */ 8 9/dts-v1/; 10#include <dt-bindings/input/input.h> 11 12#include "mt7622.dtsi" 13#include "mt6380.dtsi" 14 15/ { 16 model = "MediaTek MT7622 RFB1 board"; 17 compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622"; 18 19 chosen { 20 bootargs = "console=ttyS0,115200n1"; 21 }; 22 23 cpus { 24 cpu@0 { 25 proc-supply = <&mt6380_vcpu_reg>; 26 sram-supply = <&mt6380_vm_reg>; 27 }; 28 29 cpu@1 { 30 proc-supply = <&mt6380_vcpu_reg>; 31 sram-supply = <&mt6380_vm_reg>; 32 }; 33 }; 34 35 gpio-keys { 36 compatible = "gpio-keys-polled"; 37 poll-interval = <100>; 38 39 factory { 40 label = "factory"; 41 linux,code = <BTN_0>; 42 gpios = <&pio 0 0>; 43 }; 44 45 wps { 46 label = "wps"; 47 linux,code = <KEY_WPS_BUTTON>; 48 gpios = <&pio 102 0>; 49 }; 50 }; 51 52 memory { 53 reg = <0 0x40000000 0 0x3F000000>; 54 }; 55}; 56 57&pcie { 58 pinctrl-names = "default"; 59 pinctrl-0 = <&pcie0_pins>; 60 status = "okay"; 61 62 pcie@0,0 { 63 status = "okay"; 64 }; 65}; 66 67&pio { 68 /* eMMC is shared pin with parallel NAND */ 69 emmc_pins_default: emmc-pins-default { 70 mux { 71 function = "emmc", "emmc_rst"; 72 groups = "emmc"; 73 }; 74 }; 75 76 emmc_pins_uhs: emmc-pins-uhs { 77 mux { 78 function = "emmc"; 79 groups = "emmc"; 80 }; 81 }; 82 83 eth_pins: eth-pins { 84 mux { 85 function = "eth"; 86 groups = "mdc_mdio", "rgmii_via_gmac2"; 87 }; 88 }; 89 90 i2c1_pins: i2c1-pins { 91 mux { 92 function = "i2c"; 93 groups = "i2c1_0"; 94 }; 95 }; 96 97 i2c2_pins: i2c2-pins { 98 mux { 99 function = "i2c"; 100 groups = "i2c2_0"; 101 }; 102 }; 103 104 i2s1_pins: i2s1-pins { 105 mux { 106 function = "i2s"; 107 groups = "i2s_out_bclk_ws_mclk", 108 "i2s1_in_data", 109 "i2s1_out_data"; 110 }; 111 }; 112 113 irrx_pins: irrx-pins { 114 mux { 115 function = "ir"; 116 groups = "ir_1_rx"; 117 }; 118 }; 119 120 irtx_pins: irtx-pins { 121 mux { 122 function = "ir"; 123 groups = "ir_1_tx"; 124 }; 125 }; 126 127 /* Parallel nand is shared pin with eMMC */ 128 parallel_nand_pins: parallel-nand-pins { 129 mux { 130 function = "flash"; 131 groups = "par_nand"; 132 }; 133 }; 134 135 pcie0_pins: pcie0-pins { 136 mux { 137 function = "pcie"; 138 groups = "pcie0_pad_perst", 139 "pcie0_1_waken", 140 "pcie0_1_clkreq"; 141 }; 142 }; 143 144 pcie1_pins: pcie1-pins { 145 mux { 146 function = "pcie"; 147 groups = "pcie1_pad_perst", 148 "pcie1_0_waken", 149 "pcie1_0_clkreq"; 150 }; 151 }; 152 153 pmic_bus_pins: pmic-bus-pins { 154 mux { 155 function = "pmic"; 156 groups = "pmic_bus"; 157 }; 158 }; 159 160 pwm7_pins: pwm1-2-pins { 161 mux { 162 function = "pwm"; 163 groups = "pwm_ch7_2"; 164 }; 165 }; 166 167 wled_pins: wled-pins { 168 mux { 169 function = "led"; 170 groups = "wled"; 171 }; 172 }; 173 174 sd0_pins_default: sd0-pins-default { 175 mux { 176 function = "sd"; 177 groups = "sd_0"; 178 }; 179 }; 180 181 sd0_pins_uhs: sd0-pins-uhs { 182 mux { 183 function = "sd"; 184 groups = "sd_0"; 185 }; 186 }; 187 188 /* Serial NAND is shared pin with SPI-NOR */ 189 serial_nand_pins: serial-nand-pins { 190 mux { 191 function = "flash"; 192 groups = "snfi"; 193 }; 194 }; 195 196 spic0_pins: spic0-pins { 197 mux { 198 function = "spi"; 199 groups = "spic0_0"; 200 }; 201 }; 202 203 spic1_pins: spic1-pins { 204 mux { 205 function = "spi"; 206 groups = "spic1_0"; 207 }; 208 }; 209 210 /* SPI-NOR is shared pin with serial NAND */ 211 spi_nor_pins: spi-nor-pins { 212 mux { 213 function = "flash"; 214 groups = "spi_nor"; 215 }; 216 }; 217 218 /* serial NAND is shared pin with SPI-NOR */ 219 serial_nand_pins: serial-nand-pins { 220 mux { 221 function = "flash"; 222 groups = "snfi"; 223 }; 224 }; 225 226 uart0_pins: uart0-pins { 227 mux { 228 function = "uart"; 229 groups = "uart0_0_tx_rx" ; 230 }; 231 }; 232 233 uart2_pins: uart2-pins { 234 mux { 235 function = "uart"; 236 groups = "uart2_1_tx_rx" ; 237 }; 238 }; 239 240 watchdog_pins: watchdog-pins { 241 mux { 242 function = "watchdog"; 243 groups = "watchdog"; 244 }; 245 }; 246}; 247 248&bch { 249 status = "disabled"; 250}; 251 252&btif { 253 status = "okay"; 254}; 255 256&cir { 257 pinctrl-names = "default"; 258 pinctrl-0 = <&irrx_pins>; 259 status = "okay"; 260}; 261 262ð { 263 pinctrl-names = "default"; 264 pinctrl-0 = <ð_pins>; 265 status = "okay"; 266 267 gmac1: mac@1 { 268 compatible = "mediatek,eth-mac"; 269 reg = <1>; 270 phy-handle = <&phy5>; 271 }; 272 273 mdio-bus { 274 #address-cells = <1>; 275 #size-cells = <0>; 276 277 phy5: ethernet-phy@5 { 278 reg = <5>; 279 phy-mode = "sgmii"; 280 }; 281 }; 282}; 283 284&i2c1 { 285 pinctrl-names = "default"; 286 pinctrl-0 = <&i2c1_pins>; 287 status = "okay"; 288}; 289 290&i2c2 { 291 pinctrl-names = "default"; 292 pinctrl-0 = <&i2c2_pins>; 293 status = "okay"; 294}; 295 296&nandc { 297 pinctrl-names = "default"; 298 pinctrl-0 = <¶llel_nand_pins>; 299 status = "disabled"; 300}; 301 302&nor_flash { 303 pinctrl-names = "default"; 304 pinctrl-0 = <&spi_nor_pins>; 305 status = "disabled"; 306 307 flash@0 { 308 compatible = "jedec,spi-nor"; 309 reg = <0>; 310 }; 311}; 312 313&pwm { 314 pinctrl-names = "default"; 315 pinctrl-0 = <&pwm7_pins>; 316 status = "okay"; 317}; 318 319&pwrap { 320 pinctrl-names = "default"; 321 pinctrl-0 = <&pmic_bus_pins>; 322 323 status = "okay"; 324}; 325 326&spi0 { 327 pinctrl-names = "default"; 328 pinctrl-0 = <&spic0_pins>; 329 status = "okay"; 330}; 331 332&spi1 { 333 pinctrl-names = "default"; 334 pinctrl-0 = <&spic1_pins>; 335 status = "okay"; 336}; 337 338&uart0 { 339 pinctrl-names = "default"; 340 pinctrl-0 = <&uart0_pins>; 341 status = "okay"; 342}; 343 344&uart2 { 345 pinctrl-names = "default"; 346 pinctrl-0 = <&uart2_pins>; 347 status = "okay"; 348}; 349 350&watchdog { 351 pinctrl-names = "default"; 352 pinctrl-0 = <&watchdog_pins>; 353 status = "okay"; 354}; 355