1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Ming Huang <ming.huang@mediatek.com>
4 *	   Sean Wang <sean.wang@mediatek.com>
5 *
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 */
8
9/dts-v1/;
10#include <dt-bindings/input/input.h>
11
12#include "mt7622.dtsi"
13#include "mt6380.dtsi"
14
15/ {
16	model = "MediaTek MT7622 RFB1 board";
17	compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
18
19	chosen {
20		bootargs = "console=ttyS0,115200n1";
21	};
22
23	cpus {
24		cpu@0 {
25			proc-supply = <&mt6380_vcpu_reg>;
26			sram-supply = <&mt6380_vm_reg>;
27		};
28
29		cpu@1 {
30			proc-supply = <&mt6380_vcpu_reg>;
31			sram-supply = <&mt6380_vm_reg>;
32		};
33	};
34
35	gpio-keys {
36		compatible = "gpio-keys-polled";
37		poll-interval = <100>;
38
39		factory {
40			label = "factory";
41			linux,code = <BTN_0>;
42			gpios = <&pio 0 0>;
43		};
44
45		wps {
46			label = "wps";
47			linux,code = <KEY_WPS_BUTTON>;
48			gpios = <&pio 102 0>;
49		};
50	};
51
52	memory {
53		reg = <0 0x40000000 0 0x3F000000>;
54	};
55
56	reg_3p3v: regulator-3p3v {
57		compatible = "regulator-fixed";
58		regulator-name = "fixed-3.3V";
59		regulator-min-microvolt = <3300000>;
60		regulator-max-microvolt = <3300000>;
61		regulator-boot-on;
62		regulator-always-on;
63	};
64
65	reg_5v: regulator-5v {
66		compatible = "regulator-fixed";
67		regulator-name = "fixed-5V";
68		regulator-min-microvolt = <5000000>;
69		regulator-max-microvolt = <5000000>;
70		regulator-boot-on;
71		regulator-always-on;
72	};
73};
74
75&pcie {
76	pinctrl-names = "default";
77	pinctrl-0 = <&pcie0_pins>;
78	status = "okay";
79
80	pcie@0,0 {
81		status = "okay";
82	};
83};
84
85&pio {
86	/* eMMC is shared pin with parallel NAND */
87	emmc_pins_default: emmc-pins-default {
88		mux {
89			function = "emmc", "emmc_rst";
90			groups = "emmc";
91		};
92	};
93
94	emmc_pins_uhs: emmc-pins-uhs {
95		mux {
96			function = "emmc";
97			groups = "emmc";
98		};
99	};
100
101	eth_pins: eth-pins {
102		mux {
103			function = "eth";
104			groups = "mdc_mdio", "rgmii_via_gmac2";
105		};
106	};
107
108	i2c1_pins: i2c1-pins {
109		mux {
110			function = "i2c";
111			groups =  "i2c1_0";
112		};
113	};
114
115	i2c2_pins: i2c2-pins {
116		mux {
117			function = "i2c";
118			groups =  "i2c2_0";
119		};
120	};
121
122	i2s1_pins: i2s1-pins {
123		mux {
124			function = "i2s";
125			groups =  "i2s_out_bclk_ws_mclk",
126				  "i2s1_in_data",
127				  "i2s1_out_data";
128		};
129	};
130
131	irrx_pins: irrx-pins {
132		mux {
133			function = "ir";
134			groups =  "ir_1_rx";
135		};
136	};
137
138	irtx_pins: irtx-pins {
139		mux {
140			function = "ir";
141			groups =  "ir_1_tx";
142		};
143	};
144
145	/* Parallel nand is shared pin with eMMC */
146	parallel_nand_pins: parallel-nand-pins {
147		mux {
148			function = "flash";
149			groups = "par_nand";
150		};
151	};
152
153	pcie0_pins: pcie0-pins {
154		mux {
155			function = "pcie";
156			groups = "pcie0_pad_perst",
157				 "pcie0_1_waken",
158				 "pcie0_1_clkreq";
159		};
160	};
161
162	pcie1_pins: pcie1-pins {
163		mux {
164			function = "pcie";
165			groups = "pcie1_pad_perst",
166				 "pcie1_0_waken",
167				 "pcie1_0_clkreq";
168		};
169	};
170
171	pmic_bus_pins: pmic-bus-pins {
172		mux {
173			function = "pmic";
174			groups = "pmic_bus";
175		};
176	};
177
178	pwm7_pins: pwm1-2-pins {
179		mux {
180			function = "pwm";
181			groups = "pwm_ch7_2";
182		};
183	};
184
185	wled_pins: wled-pins {
186		mux {
187			function = "led";
188			groups = "wled";
189		};
190	};
191
192	sd0_pins_default: sd0-pins-default {
193		mux {
194			function = "sd";
195			groups = "sd_0";
196		};
197	};
198
199	sd0_pins_uhs: sd0-pins-uhs {
200		mux {
201			function = "sd";
202			groups = "sd_0";
203		};
204	};
205
206	/* Serial NAND is shared pin with SPI-NOR */
207	serial_nand_pins: serial-nand-pins {
208		mux {
209			function = "flash";
210			groups = "snfi";
211		};
212	};
213
214	spic0_pins: spic0-pins {
215		mux {
216			function = "spi";
217			groups = "spic0_0";
218		};
219	};
220
221	spic1_pins: spic1-pins {
222		mux {
223			function = "spi";
224			groups = "spic1_0";
225		};
226	};
227
228	/* SPI-NOR is shared pin with serial NAND */
229	spi_nor_pins: spi-nor-pins {
230		mux {
231			function = "flash";
232			groups = "spi_nor";
233		};
234	};
235
236	/* serial NAND is shared pin with SPI-NOR */
237	serial_nand_pins: serial-nand-pins {
238		mux {
239			function = "flash";
240			groups = "snfi";
241		};
242	};
243
244	uart0_pins: uart0-pins {
245		mux {
246			function = "uart";
247			groups = "uart0_0_tx_rx" ;
248		};
249	};
250
251	uart2_pins: uart2-pins {
252		mux {
253			function = "uart";
254			groups = "uart2_1_tx_rx" ;
255		};
256	};
257
258	watchdog_pins: watchdog-pins {
259		mux {
260			function = "watchdog";
261			groups = "watchdog";
262		};
263	};
264};
265
266&bch {
267	status = "disabled";
268};
269
270&btif {
271	status = "okay";
272};
273
274&cir {
275	pinctrl-names = "default";
276	pinctrl-0 = <&irrx_pins>;
277	status = "okay";
278};
279
280&eth {
281	pinctrl-names = "default";
282	pinctrl-0 = <&eth_pins>;
283	status = "okay";
284
285	gmac1: mac@1 {
286		compatible = "mediatek,eth-mac";
287		reg = <1>;
288		phy-handle = <&phy5>;
289	};
290
291	mdio-bus {
292		#address-cells = <1>;
293		#size-cells = <0>;
294
295		phy5: ethernet-phy@5 {
296			reg = <5>;
297			phy-mode = "sgmii";
298		};
299	};
300};
301
302&i2c1 {
303	pinctrl-names = "default";
304	pinctrl-0 = <&i2c1_pins>;
305	status = "okay";
306};
307
308&i2c2 {
309	pinctrl-names = "default";
310	pinctrl-0 = <&i2c2_pins>;
311	status = "okay";
312};
313
314&nandc {
315	pinctrl-names = "default";
316	pinctrl-0 = <&parallel_nand_pins>;
317	status = "disabled";
318};
319
320&nor_flash {
321	pinctrl-names = "default";
322	pinctrl-0 = <&spi_nor_pins>;
323	status = "disabled";
324
325	flash@0 {
326		compatible = "jedec,spi-nor";
327		reg = <0>;
328	};
329};
330
331&pwm {
332	pinctrl-names = "default";
333	pinctrl-0 = <&pwm7_pins>;
334	status = "okay";
335};
336
337&pwrap {
338	pinctrl-names = "default";
339	pinctrl-0 = <&pmic_bus_pins>;
340
341	status = "okay";
342};
343
344&sata {
345	status = "okay";
346};
347
348&sata_phy {
349	status = "okay";
350};
351
352&spi0 {
353	pinctrl-names = "default";
354	pinctrl-0 = <&spic0_pins>;
355	status = "okay";
356};
357
358&spi1 {
359	pinctrl-names = "default";
360	pinctrl-0 = <&spic1_pins>;
361	status = "okay";
362};
363
364&ssusb {
365	vusb33-supply = <&reg_3p3v>;
366	vbus-supply = <&reg_5v>;
367	status = "okay";
368};
369
370&u3phy {
371	status = "okay";
372};
373
374&uart0 {
375	pinctrl-names = "default";
376	pinctrl-0 = <&uart0_pins>;
377	status = "okay";
378};
379
380&uart2 {
381	pinctrl-names = "default";
382	pinctrl-0 = <&uart2_pins>;
383	status = "okay";
384};
385
386&watchdog {
387	pinctrl-names = "default";
388	pinctrl-0 = <&watchdog_pins>;
389	status = "okay";
390};
391