1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Mars.C <mars.cheng@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11 * GNU General Public License for more details.
12 */
13
14#include <dt-bindings/clock/mt6797-clk.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/interrupt-controller/arm-gic.h>
17#include <dt-bindings/pinctrl/mt6797-pinfunc.h>
18
19/ {
20	compatible = "mediatek,mt6797";
21	interrupt-parent = <&sysirq>;
22	#address-cells = <2>;
23	#size-cells = <2>;
24
25	psci {
26		compatible = "arm,psci-0.2";
27		method = "smc";
28	};
29
30	cpus {
31		#address-cells = <1>;
32		#size-cells = <0>;
33
34		cpu0: cpu@0 {
35			device_type = "cpu";
36			compatible = "arm,cortex-a53";
37			enable-method = "psci";
38			reg = <0x000>;
39		};
40
41		cpu1: cpu@1 {
42			device_type = "cpu";
43			compatible = "arm,cortex-a53";
44			enable-method = "psci";
45			reg = <0x001>;
46		};
47
48		cpu2: cpu@2 {
49			device_type = "cpu";
50			compatible = "arm,cortex-a53";
51			enable-method = "psci";
52			reg = <0x002>;
53		};
54
55		cpu3: cpu@3 {
56			device_type = "cpu";
57			compatible = "arm,cortex-a53";
58			enable-method = "psci";
59			reg = <0x003>;
60		};
61
62		cpu4: cpu@100 {
63			device_type = "cpu";
64			compatible = "arm,cortex-a53";
65			enable-method = "psci";
66			reg = <0x100>;
67		};
68
69		cpu5: cpu@101 {
70			device_type = "cpu";
71			compatible = "arm,cortex-a53";
72			enable-method = "psci";
73			reg = <0x101>;
74		};
75
76		cpu6: cpu@102 {
77			device_type = "cpu";
78			compatible = "arm,cortex-a53";
79			enable-method = "psci";
80			reg = <0x102>;
81		};
82
83		cpu7: cpu@103 {
84			device_type = "cpu";
85			compatible = "arm,cortex-a53";
86			enable-method = "psci";
87			reg = <0x103>;
88		};
89
90		cpu8: cpu@200 {
91			device_type = "cpu";
92			compatible = "arm,cortex-a72";
93			enable-method = "psci";
94			reg = <0x200>;
95		};
96
97		cpu9: cpu@201 {
98			device_type = "cpu";
99			compatible = "arm,cortex-a72";
100			enable-method = "psci";
101			reg = <0x201>;
102		};
103	};
104
105	clk26m: oscillator@0 {
106		compatible = "fixed-clock";
107		#clock-cells = <0>;
108		clock-frequency = <26000000>;
109		clock-output-names = "clk26m";
110	};
111
112	timer {
113		compatible = "arm,armv8-timer";
114		interrupt-parent = <&gic>;
115		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
116			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
117			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
118			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
119	};
120
121	topckgen: topckgen@10000000 {
122		compatible = "mediatek,mt6797-topckgen";
123		reg = <0 0x10000000 0 0x1000>;
124		#clock-cells = <1>;
125	};
126
127	infrasys: infracfg_ao@10001000 {
128		compatible = "mediatek,mt6797-infracfg", "syscon";
129		reg = <0 0x10001000 0 0x1000>;
130		#clock-cells = <1>;
131	};
132
133	pio: pinctrl@10005000 {
134		compatible = "mediatek,mt6797-pinctrl";
135		reg = <0 0x10005000 0 0x1000>,
136		      <0 0x10002000 0 0x400>,
137		      <0 0x10002400 0 0x400>,
138		      <0 0x10002800 0 0x400>,
139		      <0 0x10002C00 0 0x400>;
140		reg-names = "gpio", "iocfgl", "iocfgb",
141			    "iocfgr", "iocfgt";
142		gpio-controller;
143		#gpio-cells = <2>;
144
145		uart0_pins_a: uart0 {
146			pins0 {
147				pinmux = <MT6797_GPIO234__FUNC_UTXD0>,
148					 <MT6797_GPIO235__FUNC_URXD0>;
149			};
150		};
151
152		uart1_pins_a: uart1 {
153			pins1 {
154				pinmux = <MT6797_GPIO232__FUNC_URXD1>,
155					 <MT6797_GPIO233__FUNC_UTXD1>;
156			};
157		};
158
159		i2c0_pins_a: i2c0 {
160			pins0 {
161				pinmux = <MT6797_GPIO37__FUNC_SCL0_0>,
162					 <MT6797_GPIO38__FUNC_SDA0_0>;
163			};
164		};
165
166		i2c1_pins_a: i2c1 {
167			pins1 {
168				pinmux = <MT6797_GPIO55__FUNC_SCL1_0>,
169					 <MT6797_GPIO56__FUNC_SDA1_0>;
170			};
171		};
172
173		i2c2_pins_a: i2c2 {
174			pins2 {
175				pinmux = <MT6797_GPIO96__FUNC_SCL2_0>,
176					 <MT6797_GPIO95__FUNC_SDA2_0>;
177			};
178		};
179
180		i2c3_pins_a: i2c3 {
181			pins3 {
182				pinmux = <MT6797_GPIO75__FUNC_SDA3_0>,
183					 <MT6797_GPIO74__FUNC_SCL3_0>;
184			};
185		};
186
187		i2c4_pins_a: i2c4 {
188			pins4 {
189				pinmux = <MT6797_GPIO238__FUNC_SDA4_0>,
190					 <MT6797_GPIO239__FUNC_SCL4_0>;
191			};
192		};
193
194		i2c5_pins_a: i2c5 {
195			pins5 {
196				pinmux = <MT6797_GPIO240__FUNC_SDA5_0>,
197					 <MT6797_GPIO241__FUNC_SCL5_0>;
198			};
199		};
200
201		i2c6_pins_a: i2c6 {
202			pins6 {
203				pinmux = <MT6797_GPIO152__FUNC_SDA6_0>,
204					 <MT6797_GPIO151__FUNC_SCL6_0>;
205			};
206		};
207
208		i2c7_pins_a: i2c7 {
209			pins7 {
210				pinmux = <MT6797_GPIO154__FUNC_SDA7_0>,
211					 <MT6797_GPIO153__FUNC_SCL7_0>;
212			};
213		};
214	};
215
216	scpsys: power-controller@10006000 {
217		compatible = "mediatek,mt6797-scpsys";
218		#power-domain-cells = <1>;
219		reg = <0 0x10006000 0 0x1000>;
220		clocks = <&topckgen CLK_TOP_MUX_MFG>,
221			 <&topckgen CLK_TOP_MUX_MM>,
222			 <&topckgen CLK_TOP_MUX_VDEC>;
223		clock-names = "mfg", "mm", "vdec";
224		infracfg = <&infrasys>;
225	};
226
227	watchdog: watchdog@10007000 {
228		compatible = "mediatek,mt6797-wdt", "mediatek,mt6589-wdt";
229		reg = <0 0x10007000 0 0x100>;
230	};
231
232	apmixedsys: apmixed@1000c000 {
233		compatible = "mediatek,mt6797-apmixedsys";
234		reg = <0 0x1000c000 0 0x1000>;
235		#clock-cells = <1>;
236	};
237
238	sysirq: intpol-controller@10200620 {
239		compatible = "mediatek,mt6797-sysirq",
240			     "mediatek,mt6577-sysirq";
241		interrupt-controller;
242		#interrupt-cells = <3>;
243		interrupt-parent = <&gic>;
244		reg = <0 0x10220620 0 0x20>,
245		      <0 0x10220690 0 0x10>;
246	};
247
248	uart0: serial@11002000 {
249		compatible = "mediatek,mt6797-uart",
250			     "mediatek,mt6577-uart";
251		reg = <0 0x11002000 0 0x400>;
252		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
253		clocks = <&infrasys CLK_INFRA_UART0>,
254			 <&infrasys CLK_INFRA_AP_DMA>;
255		clock-names = "baud", "bus";
256		status = "disabled";
257	};
258
259	uart1: serial@11003000 {
260		compatible = "mediatek,mt6797-uart",
261			     "mediatek,mt6577-uart";
262		reg = <0 0x11003000 0 0x400>;
263		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
264		clocks = <&infrasys CLK_INFRA_UART1>,
265			 <&infrasys CLK_INFRA_AP_DMA>;
266		clock-names = "baud", "bus";
267		status = "disabled";
268	};
269
270	uart2: serial@11004000 {
271		compatible = "mediatek,mt6797-uart",
272			     "mediatek,mt6577-uart";
273		reg = <0 0x11004000 0 0x400>;
274		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
275		clocks = <&infrasys CLK_INFRA_UART2>,
276			 <&infrasys CLK_INFRA_AP_DMA>;
277		clock-names = "baud", "bus";
278		status = "disabled";
279	};
280
281	uart3: serial@11005000 {
282		compatible = "mediatek,mt6797-uart",
283			     "mediatek,mt6577-uart";
284		reg = <0 0x11005000 0 0x400>;
285		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
286		clocks = <&infrasys CLK_INFRA_UART3>,
287			 <&infrasys CLK_INFRA_AP_DMA>;
288		clock-names = "baud", "bus";
289		status = "disabled";
290	};
291
292	i2c0: i2c@11007000 {
293		compatible = "mediatek,mt6797-i2c",
294			     "mediatek,mt6577-i2c";
295		id = <0>;
296		reg = <0 0x11007000 0 0x1000>,
297		      <0 0x11000100 0 0x80>;
298		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
299		clocks = <&infrasys CLK_INFRA_I2C0>,
300			 <&infrasys CLK_INFRA_AP_DMA>;
301		clock-names = "main", "dma";
302		clock-div = <10>;
303		#address-cells = <1>;
304		#size-cells = <0>;
305		status = "disabled";
306	};
307
308	i2c1: i2c@11008000 {
309		compatible = "mediatek,mt6797-i2c",
310			     "mediatek,mt6577-i2c";
311		id = <1>;
312		reg = <0 0x11008000 0 0x1000>,
313		      <0 0x11000180 0 0x80>;
314		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
315		clocks = <&infrasys CLK_INFRA_I2C1>,
316			 <&infrasys CLK_INFRA_AP_DMA>;
317		clock-names = "main", "dma";
318		clock-div = <10>;
319		#address-cells = <1>;
320		#size-cells = <0>;
321		status = "disabled";
322	};
323
324	i2c8: i2c@11009000 {
325		compatible = "mediatek,mt6797-i2c",
326			     "mediatek,mt6577-i2c";
327		id = <8>;
328		reg = <0 0x11009000 0 0x1000>,
329		      <0 0x11000200 0 0x80>;
330		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
331		clocks = <&infrasys CLK_INFRA_I2C2>,
332			 <&infrasys CLK_INFRA_AP_DMA>,
333			 <&infrasys CLK_INFRA_I2C2_ARB>;
334		clock-names = "main", "dma", "arb";
335		clock-div = <10>;
336		#address-cells = <1>;
337		#size-cells = <0>;
338		status = "disabled";
339	};
340
341	i2c9: i2c@1100d000 {
342		compatible = "mediatek,mt6797-i2c",
343			     "mediatek,mt6577-i2c";
344		id = <9>;
345		reg = <0 0x1100d000 0 0x1000>,
346		      <0 0x11000280 0 0x80>;
347		interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
348		clocks = <&infrasys CLK_INFRA_I2C3>,
349			 <&infrasys CLK_INFRA_AP_DMA>,
350			 <&infrasys CLK_INFRA_I2C3_ARB>;
351		clock-names = "main", "dma", "arb";
352		clock-div = <10>;
353		#address-cells = <1>;
354		#size-cells = <0>;
355		status = "disabled";
356	};
357
358	i2c6: i2c@1100e000 {
359		compatible = "mediatek,mt6797-i2c",
360			     "mediatek,mt6577-i2c";
361		id = <6>;
362		reg = <0 0x1100e000 0 0x1000>,
363		      <0 0x11000500 0 0x80>;
364		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
365		clocks = <&infrasys CLK_INFRA_I2C_APPM>,
366			 <&infrasys CLK_INFRA_AP_DMA>;
367		clock-names = "main", "dma";
368		clock-div = <10>;
369		#address-cells = <1>;
370		#size-cells = <0>;
371		status = "disabled";
372	};
373
374	i2c7: i2c@11010000 {
375		compatible = "mediatek,mt6797-i2c",
376			     "mediatek,mt6577-i2c";
377		id = <7>;
378		reg = <0 0x11010000 0 0x1000>,
379		      <0 0x11000580 0 0x80>;
380		interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
381		clocks = <&infrasys CLK_INFRA_I2C_GPUPM>,
382			 <&infrasys CLK_INFRA_AP_DMA>;
383		clock-names = "main", "dma";
384		clock-div = <10>;
385		#address-cells = <1>;
386		#size-cells = <0>;
387		status = "disabled";
388	};
389
390	i2c4: i2c@11011000 {
391		compatible = "mediatek,mt6797-i2c",
392			     "mediatek,mt6577-i2c";
393		id = <4>;
394		reg = <0 0x11011000 0 0x1000>,
395		      <0 0x11000300 0 0x80>;
396		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
397		clocks = <&infrasys CLK_INFRA_I2C4>,
398			 <&infrasys CLK_INFRA_AP_DMA>;
399		clock-names = "main", "dma";
400		clock-div = <10>;
401		#address-cells = <1>;
402		#size-cells = <0>;
403		status = "disabled";
404	};
405
406	i2c2: i2c@11013000 {
407		compatible = "mediatek,mt6797-i2c",
408			     "mediatek,mt6577-i2c";
409		id = <2>;
410		reg = <0 0x11013000 0 0x1000>,
411		      <0 0x11000400 0 0x80>;
412		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
413		clocks = <&infrasys CLK_INFRA_I2C2_IMM>,
414			 <&infrasys CLK_INFRA_AP_DMA>,
415			 <&infrasys CLK_INFRA_I2C2_ARB>;
416		clock-names = "main", "dma", "arb";
417		clock-div = <10>;
418		#address-cells = <1>;
419		#size-cells = <0>;
420		status = "disabled";
421	};
422
423	i2c3: i2c@11014000 {
424		compatible = "mediatek,mt6797-i2c",
425			     "mediatek,mt6577-i2c";
426		id = <3>;
427		reg = <0 0x11014000 0 0x1000>,
428		      <0 0x11000480 0 0x80>;
429		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
430		clocks = <&infrasys CLK_INFRA_I2C3_IMM>,
431			 <&infrasys CLK_INFRA_AP_DMA>,
432			 <&infrasys CLK_INFRA_I2C3_ARB>;
433		clock-names = "main", "dma", "arb";
434		clock-div = <10>;
435		#address-cells = <1>;
436		#size-cells = <0>;
437		status = "disabled";
438	};
439
440	i2c5: i2c@1101c000 {
441		compatible = "mediatek,mt6797-i2c",
442			     "mediatek,mt6577-i2c";
443		id = <5>;
444		reg = <0 0x1101c000 0 0x1000>,
445		      <0 0x11000380 0 0x80>;
446		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
447		clocks = <&infrasys CLK_INFRA_I2C5>,
448			 <&infrasys CLK_INFRA_AP_DMA>;
449		clock-names = "main", "dma";
450		clock-div = <10>;
451		#address-cells = <1>;
452		#size-cells = <0>;
453		status = "disabled";
454	};
455
456	mmsys: mmsys_config@14000000 {
457		compatible = "mediatek,mt6797-mmsys", "syscon";
458		reg = <0 0x14000000 0 0x1000>;
459		#clock-cells = <1>;
460	};
461
462	imgsys: imgsys_config@15000000  {
463		compatible = "mediatek,mt6797-imgsys", "syscon";
464		reg = <0 0x15000000 0 0x1000>;
465		#clock-cells = <1>;
466	};
467
468	vdecsys: vdec_gcon@16000000 {
469		compatible = "mediatek,mt6797-vdecsys", "syscon";
470		reg = <0 0x16000000 0 0x10000>;
471		#clock-cells = <1>;
472	};
473
474	vencsys: venc_gcon@17000000 {
475		compatible = "mediatek,mt6797-vencsys", "syscon";
476		reg = <0 0x17000000 0 0x1000>;
477		#clock-cells = <1>;
478	};
479
480	gic: interrupt-controller@19000000 {
481		compatible = "arm,gic-v3";
482		#interrupt-cells = <3>;
483		interrupt-parent = <&gic>;
484		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
485		interrupt-controller;
486		reg = <0 0x19000000 0 0x10000>,    /* GICD */
487		      <0 0x19200000 0 0x200000>,   /* GICR */
488		      <0 0x10240000 0 0x2000>;     /* GICC */
489	};
490};
491