1/* 2 * Copyright (c) 2017 MediaTek Inc. 3 * Author: Mars.C <mars.cheng@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/clock/mt6797-clk.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17 18/ { 19 compatible = "mediatek,mt6797"; 20 interrupt-parent = <&sysirq>; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 psci { 25 compatible = "arm,psci-0.2"; 26 method = "smc"; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a53"; 36 enable-method = "psci"; 37 reg = <0x000>; 38 }; 39 40 cpu1: cpu@1 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a53"; 43 enable-method = "psci"; 44 reg = <0x001>; 45 }; 46 47 cpu2: cpu@2 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a53"; 50 enable-method = "psci"; 51 reg = <0x002>; 52 }; 53 54 cpu3: cpu@3 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a53"; 57 enable-method = "psci"; 58 reg = <0x003>; 59 }; 60 61 cpu4: cpu@100 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a53"; 64 enable-method = "psci"; 65 reg = <0x100>; 66 }; 67 68 cpu5: cpu@101 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a53"; 71 enable-method = "psci"; 72 reg = <0x101>; 73 }; 74 75 cpu6: cpu@102 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a53"; 78 enable-method = "psci"; 79 reg = <0x102>; 80 }; 81 82 cpu7: cpu@103 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a53"; 85 enable-method = "psci"; 86 reg = <0x103>; 87 }; 88 89 cpu8: cpu@200 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a72"; 92 enable-method = "psci"; 93 reg = <0x200>; 94 }; 95 96 cpu9: cpu@201 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a72"; 99 enable-method = "psci"; 100 reg = <0x201>; 101 }; 102 }; 103 104 clk26m: oscillator@0 { 105 compatible = "fixed-clock"; 106 #clock-cells = <0>; 107 clock-frequency = <26000000>; 108 clock-output-names = "clk26m"; 109 }; 110 111 clk32k: oscillator@1 { 112 compatible = "fixed-clock"; 113 #clock-cells = <0>; 114 clock-frequency = <32000>; 115 clock-output-names = "clk32k"; 116 }; 117 118 timer { 119 compatible = "arm,armv8-timer"; 120 interrupt-parent = <&gic>; 121 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 122 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 123 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 124 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 125 }; 126 127 topckgen: topckgen@10000000 { 128 compatible = "mediatek,mt6797-topckgen"; 129 reg = <0 0x10000000 0 0x1000>; 130 #clock-cells = <1>; 131 }; 132 133 infrasys: infracfg_ao@10001000 { 134 compatible = "mediatek,mt6797-infracfg", "syscon"; 135 reg = <0 0x10001000 0 0x1000>; 136 #clock-cells = <1>; 137 }; 138 139 scpsys: scpsys@10006000 { 140 compatible = "mediatek,mt6797-scpsys"; 141 #power-domain-cells = <1>; 142 reg = <0 0x10006000 0 0x1000>; 143 clocks = <&topckgen CLK_TOP_MUX_MFG>, 144 <&topckgen CLK_TOP_MUX_MM>, 145 <&topckgen CLK_TOP_MUX_VDEC>; 146 clock-names = "mfg", "mm", "vdec"; 147 infracfg = <&infrasys>; 148 }; 149 150 watchdog: watchdog@10007000 { 151 compatible = "mediatek,mt6797-wdt", "mediatek,mt6589-wdt"; 152 reg = <0 0x10007000 0 0x100>; 153 }; 154 155 apmixedsys: apmixed@1000c000 { 156 compatible = "mediatek,mt6797-apmixedsys"; 157 reg = <0 0x1000c000 0 0x1000>; 158 #clock-cells = <1>; 159 }; 160 161 sysirq: intpol-controller@10200620 { 162 compatible = "mediatek,mt6797-sysirq", 163 "mediatek,mt6577-sysirq"; 164 interrupt-controller; 165 #interrupt-cells = <3>; 166 interrupt-parent = <&gic>; 167 reg = <0 0x10220620 0 0x20>, 168 <0 0x10220690 0 0x10>; 169 }; 170 171 uart0: serial@11002000 { 172 compatible = "mediatek,mt6797-uart", 173 "mediatek,mt6577-uart"; 174 reg = <0 0x11002000 0 0x400>; 175 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 176 clocks = <&infrasys CLK_INFRA_UART0>, 177 <&infrasys CLK_INFRA_AP_DMA>; 178 clock-names = "baud", "bus"; 179 status = "disabled"; 180 }; 181 182 uart1: serial@11003000 { 183 compatible = "mediatek,mt6797-uart", 184 "mediatek,mt6577-uart"; 185 reg = <0 0x11003000 0 0x400>; 186 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 187 clocks = <&infrasys CLK_INFRA_UART1>, 188 <&infrasys CLK_INFRA_AP_DMA>; 189 clock-names = "baud", "bus"; 190 status = "disabled"; 191 }; 192 193 uart2: serial@11004000 { 194 compatible = "mediatek,mt6797-uart", 195 "mediatek,mt6577-uart"; 196 reg = <0 0x11004000 0 0x400>; 197 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 198 clocks = <&infrasys CLK_INFRA_UART2>, 199 <&infrasys CLK_INFRA_AP_DMA>; 200 clock-names = "baud", "bus"; 201 status = "disabled"; 202 }; 203 204 uart3: serial@11005000 { 205 compatible = "mediatek,mt6797-uart", 206 "mediatek,mt6577-uart"; 207 reg = <0 0x11005000 0 0x400>; 208 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; 209 clocks = <&infrasys CLK_INFRA_UART3>, 210 <&infrasys CLK_INFRA_AP_DMA>; 211 clock-names = "baud", "bus"; 212 status = "disabled"; 213 }; 214 215 mmsys: mmsys_config@14000000 { 216 compatible = "mediatek,mt6797-mmsys", "syscon"; 217 reg = <0 0x14000000 0 0x1000>; 218 #clock-cells = <1>; 219 }; 220 221 imgsys: imgsys_config@15000000 { 222 compatible = "mediatek,mt6797-imgsys", "syscon"; 223 reg = <0 0x15000000 0 0x1000>; 224 #clock-cells = <1>; 225 }; 226 227 vdecsys: vdec_gcon@16000000 { 228 compatible = "mediatek,mt6797-vdecsys", "syscon"; 229 reg = <0 0x16000000 0 0x10000>; 230 #clock-cells = <1>; 231 }; 232 233 vencsys: venc_gcon@17000000 { 234 compatible = "mediatek,mt6797-vencsys", "syscon"; 235 reg = <0 0x17000000 0 0x1000>; 236 #clock-cells = <1>; 237 }; 238 239 gic: interrupt-controller@19000000 { 240 compatible = "arm,gic-v3"; 241 #interrupt-cells = <3>; 242 interrupt-parent = <&gic>; 243 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 244 interrupt-controller; 245 reg = <0 0x19000000 0 0x10000>, /* GICD */ 246 <0 0x19200000 0 0x200000>, /* GICR */ 247 <0 0x10240000 0 0x2000>; /* GICC */ 248 }; 249}; 250